JPH0414133A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To increase the processing speed of an arithmetic unit by giving the control information of different kinds to each arithmetic cell and actuating these cells in parallel with each other to plural bit fields stored in a single word length. CONSTITUTION:A cell control information storage means 2 stores the different m-bit control information (m X n) which control (n) pieces of arithmetic cells 1. Each cell 1 consists of a carry selection part 3 and an arithmetic part 4. The part 3 receives an m-bit control signal selects one of the carry output and logic 0 or 1 of a slave arithmetic cell 1 as a carry input. Thus a connection range of bit fields can be changed according to a fact whether the carry output of the slave arithmetic cell 1 should be selected or not. In such a way, the cell 1 can perform different actions for each bit when different kinds of control information are given to the cell 1. As a result, plural bit fields can be processed in parallel with each other and the processing speed of an arithmetic unit is increased.

Description

[Detailed Description of the Invention] [Summary] This invention relates to an arithmetic device, and more specifically to an arithmetic device that mainly processes bit fields. The purpose of the present invention is to provide an arithmetic device that can perform processing and speed up the processing, and includes a plurality of arithmetic cells that perform arithmetic processing on each bit assigned to data based on control information, and each of the above-mentioned arithmetic cells. An arithmetic device comprising cell control information storage means for storing a plurality of different pieces of control information for controlling respective arithmetic cells,
Each of the arithmetic cells has a carry selector that selects one of the carry output, logical zero, or logical one of the lower arithmetic cell as a carry input based on control information; The present invention includes an arithmetic unit that performs a logical operation or addition/subtraction between a carry input and two data bits, and outputs the result of the operation and the carry.

Further, a bit division information storage means for storing a bit width detection range, a calculation result and carry for each bit outputted from each arithmetic cell, and information in each detection range based on the division information of the bit division information storage means. A flag detection circuit for detecting flags is provided.

[Industrial Field of Application] The present invention relates to an arithmetic device, and more particularly, to an arithmetic device that mainly performs bit field processing.

BACKGROUND OF THE INVENTION With the increase in the word pit width handled by computers in recent years and the increase in simulation work, there is a demand for arithmetic devices that can process bit fields at high speed.

BACKGROUND ART In a conventional arithmetic device, as shown in FIG. When there is a bit field BF, the processing of this bit field BF is to first cut out the bit field BF as shown in FIG. After that, the arithmetic logic unit (Arithmatic Logic Uni
The same control information is given to each arithmetic cell in t) to perform logical operations or addition/subtraction over the entire n bits as shown in FIG. 8(b), and then as shown in FIG. 8(a). This has been executed by a processing group that inserts the bit field BF into the data D shown.

[Problem to be solved by the invention] However, these processing groups take time to execute;
In particular, in simulator processing, etc., a large number of words with a data structure such as multiple bit fields stored in a word length are processed, and the cumulative execution time becomes enormous. This was a hindering factor.

The present invention has been made in order to solve the above-mentioned problems, and has the following features: 1) Processing can be performed by operating arithmetic cells in parallel on multiple bit fields stored in a word length, resulting in faster processing; An object of the present invention is to provide an arithmetic device that can perform the following functions.

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of a second invention including the first invention.

The plurality of arithmetic cells 1 perform arithmetic processing on each bit to which data is assigned based on control information. The cell control information storage means 2 stores a plurality of different control information for controlling each calculation cell 1, for example, n
Each m-bit control information for each of the arithmetic cells 1 is stored as mxn memories.

Each arithmetic cell (3) consists of a carry selection section 3 and an arithmetic section 4, and the carry selection section 3 receives, for example, an m-bit control signal, and selects the carry output of the lower arithmetic cell 1, a logic zero, or a logic one. One is selected as the carry input. Similarly, the calculation unit 4 receives an m-bit control signal,
It performs a logical operation or addition/subtraction between the carry input selected by the carry selector 3 and two data bits, and outputs the result of the operation and the carry.

Then, when the processing of each arithmetic cell 1 is addition and subtraction, if the carry of the lower arithmetic cell is selected, it will operate as a series of bit fields.

Further, the bit division information storage means 5 stores the detection range of the bit width in a word. Flag detection circuit 6
Detects flags in each detection range based on the bit-by-bit operation result and carry output from each operation cell 1 and the division information in the bit division information storage means 5.

[Function] Since different control information is given to each calculation cell 1, each calculation cell 1 can perform different operations for each bit. In other words, multiple bit field processes can be executed in parallel. become. Also, carry selection section 3
Since one of the carry output, logic zero, or logic one of lower arithmetic cell 1 is selected as the carry input based on the control information, bit field concatenation is determined by whether or not the carry output of lower arithmetic cell 1 is selected. The range can be changed.

Further, the flag detection circuit 6 detects the flag in each detection range based on the bit-by-bit operation result and carry output from each calculation cell 1 and the division information in the bit division information storage means 5. Therefore, flag detection in numerical bit fields becomes easy.

[Example] An example embodying the present invention will be described below with reference to FIGS. 2 to 7.

Components that are the same as those shown in FIG. 1 are given the same reference numerals, and a portion of the explanation will be omitted.

FIG. 2 shows an embodiment in which the present invention is embodied in an arithmetic processing processor 10, such as a microprocessor. The processor 10 includes first and second memories 11 and 12, and the first memory 11 receives a control information signal and a bit division information signal from the outside. The same memory 11 has an ALU
(Operation) The cell control information storage section 2 and the bit division information storage section 5 are connected, and the control information signal is transferred to the ALU cell control information storage section 2 under transfer control by the control circuit 13, and the bit division information storage section 5 is connected to the cell control information storage section 2. The bit division information signal is transferred to section 5. The second memory 12 stores data used in logical operations, addition and subtraction, etc. from the outside, and the data in the memory I2 is stored in the control circuit 1.
As shown in Fig. 3, each ALU
One bit each of data Xi and Yi is transferred to cell I.

As shown in FIG. 3, the ALU cell control information storage section 2 has m
It is configured with xn memory cells, and n A
m bits for each LU cell 1 (7 in this example)
Control information signals C6 to CO of bits) are provided. For example, as shown in FIG. 3, bit "0" has XandY, bit rlJ has not(Y), and bits "2J~r
A control information signal indicating X-Y processing is input to n-IJ.

FIG. 4 is a logic circuit diagram showing the configuration of the ALU cell 1. As shown in FIG. To explain FIG. 4, a logic generation section 25 is constituted by three-input AND circuits 20 to 23 which input any one of data Xi, Yi and control information signal Co-C5, and an OR circuit 24. .

Also, an AND circuit 26 inputting the control information signals C5 and C4.
, control information signals C5 and C4, and an AND circuit 27 and an OR circuit 28 which receive the carry Cin from the lower ALU cell as inputs. The carry selection section 3 selects one of carry Cin, logic zero, or logic one as a carry input.

For example, if the control information signals C5, C4 are rl'', r(N, logical zero is selected as the carry input, and if the control information signals C5, C, C4 are rl'', rl'', logical one is selected as the carry input. Also, when the control information signals C5 and C4 are rob and rlJ, carry Cin is selected as the carry input.Then, carry Cin, that is,
The concatenated range of bit fields can be changed depending on whether or not the carry output of the lower arithmetic cell l is selected as the carry input.

Further, an AND circuit 30 receives the output of the carry selection section 3 and data Yi, and an Ex circuit receives the output of the carry selection section 3, the control information signal C5, and the data Xi as inputs.
AND circuit 3L which inputs the output of OR circuit 34
A whose inputs are the output of the ExOR circuit 34 and data Yi
A carry generation section 29 is configured by the ND circuit 32 and the OR circuit 33, and the generated carry Co is sent to the upper ALU.
It is output to cell l and the flag detection circuit 6.

Furthermore, the logic generation section 25 and the carry selection section 3
An arithmetic result is generated by the ExOR 35 which receives two output signals as inputs, and is outputted to the flag detection circuit 6.

The bit division information storage section 5 is configured with a storage area for the number of bits of a word, and the word length is 4 as shown in FIG.
The bit division information storage unit 5 in the case of bits is shown. The detection range of the bit width in a word, ie, the bit field range, is designated by writing "1" into the bit division information storage section 5.

FIG. 7 shows details of the flag detection circuit 6. This flag detection circuit 6 has a word length of 4 bits, similar to the bit division information storage section 5. The four preceding first detection cells 36 are respectively connected to the four signal lines of the divided information bus B1, and each preceding first detection cell 36 is connected to an AND circuit 37 whose one input is the signal of the corresponding signal line. It is composed of an OR circuit 38. Top (7th
AND circuit 3 of the preceding detection cell 36 (left end in the figure)
7 and the other input terminal of the OR circuit 38, "0" is inputted, and the output of the OR circuit 38 is sequentially inputted to the lower preceding one detection cell.

The code flag detection section 39 includes four AND circuits 40A to 40.
D, and an OR circuit 41 which receives these output signals as input, and each AND circuit 40A to 40D receives a signal from the corresponding signal line of the first information bus B4 as one input, and outputs signals from each ALU cell 1. The signal on the corresponding signal line of the extending data information bus B2 is used as the other input.

The carry flag detection section 42 includes four AND circuits 43A~
43D and an OR circuit 44 which receives these output signals as inputs.
Each of the AND circuits 43A to 43D receives the signal of the corresponding signal line of the first preceding information bus B4 as one input, and
The signal on the corresponding signal line of the carry information bus B3 extending from each ALU cell 1 is used as the other input.

Furthermore, the zero flag detection section 45 includes four AND circuits 46A.
-46D, and a NOR circuit 47 which receives these output signals as input, and each AND circuit 46A-46D receives the signal of the corresponding signal line of the divided information bus Bl as one input, and connects the data information bus B2. The signal on the corresponding signal line is used as the other input.

Therefore, for example, if the division information is "01" as shown in FIG.
11", the preceding one detection information becomes "0100". Also, the data information is "1Ooo" and the carry information is ro.
110J, the output from the code flag detection section 39 is "0" and the output from the carry flag detection section 42 is "l".
”, and the output from the zero flag detection unit 45 becomes “1”.

In this way, in this embodiment, the ALU cell control information storage unit 2
is configured with mxn memory cells and n ALUs.
Control information signal C6~ of m bits each for cell l
Since the CO is given and different control information is given to each arithmetic cell 1, the conventional extraction operation for bit fields is eliminated, and each ALU cell 1 can perform different operations for each bit. , multiple bitfield operations can be performed in parallel. Therefore, it is possible to improve the performance of a simulation computer, etc.

Furthermore, the carry selector 3 can select one of the carry output, logic zero, or logic one of the lower arithmetic cell l as the carry input based on the control information, so that the lower arithmetic cell l
The concatenation range of bit fields can be changed depending on whether carry output is selected or not.

Further, the flag detection circuit 6 detects the flag in each detection range based on the operation result and carry for each bit output from each ALU cell 1 and the division information in the bit division information storage means 5. Therefore, flag detection in numerical bit fields can be easily performed.

In this embodiment, when setting the control information signal to the ALU cell control information storage unit 2, access is performed n times with m bit input, but the contents of the bit division control information storage unit 5 Accordingly, the ALU cell control information storage unit 2 corresponding to the ALU cell l that performs the same bit field operation
The circuit may be configured to automatically allocate the same control code to the storage areas.

[Effects of the Invention] As detailed above, according to the present invention, arithmetic cells can be operated in parallel to process multiple bit fields stored in one word length, and processing speed can be increased. There are excellent effects that can be achieved.

FIG. 3 is a detailed diagram of the ALU cell control information storage section; FIG. 4 is a logic circuit diagram showing the configuration of the ALU cell; FIG. 5 is an explanatory diagram of the logical operation of the ALU cell; 7 is a logic circuit diagram showing a flag detection circuit, and FIGS. 8(a) and 8(b) are explanatory diagrams of conventional bit field processing.

In the figure, 1 operation cell, 2. cell control information storage means; 3. Carry selection section, 4 arithmetic section, 5 bit division information storage means;

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, Figure 2 shows the embodiment of the present invention in an arithmetic processing processor. figure Details of ALU cell control information storage unit No. figure Diagram showing Pi9 division information storage section (b) B Hi

Claims (1)

[Claims] 1. A plurality of arithmetic cells (1) that perform arithmetic processing on each bit to which data is allocated based on control information, and a plurality of different control information that respectively control each of the arithmetic cells (1). and a cell control information storage means (2) for storing a cell control information storage means (2), wherein each arithmetic cell (1) stores a carry output, a logic zero or a logic one of a lower arithmetic cell (1) based on the control information. A carry selection section (3) that selects one of them as a carry input, and a logical operation or addition/subtraction between the carry input selected by the carry selection section (3) and two data bits according to control information. 1. An arithmetic device comprising: an arithmetic unit (4) that performs the arithmetic operation and outputs the arithmetic result and a carry. 2. A bit division information storage means (5) for storing a bit width detection range; a calculation result and carry for each bit outputted from each calculation cell (1); and the bit division information storage means (5).
2. The arithmetic device according to claim 1, further comprising a flag detection circuit (6) that detects a flag in each detection range based on the division information.