KR960024997A - Digital array processor for multi-instruction multi-data type neural network and system configured using same - Google Patents

Abstract

In digital processor design using Very Large Scale Intergration (VLSI) technology, the present invention relates to an implementation of a neural network dedicated processor or an implementation of a neural network dedicated parallel processor.

The present invention provides a memory and general purpose register block 10, a program memory and control block 11 having a separate memory configuration (WM, XM) for the pipeline operation of the operation, an operator block 12 for performing various operations and Four blocks of communication blocks 13 for interprocessor communication; And a bus (BUS), which is divided into a program bus 14 and a data bus 15, and is a hardware (chip) for simulating a neural network model using current digital VLSI technology. ) Can be produced stably.

Description

Digital array processor for multi-instruction multi-data type neural network and system configured using same

Since this is an open matter, no full text was included.

FIG. 1 is a schematic diagram of an array processor, FIG. 2 is a schematic diagram of an array processor operator, FIG. 3 is a schematic diagram of an array processor memory, FIG. 4 is a schematic diagram of an array processor communication, and FIG. 6 is a neural network important for hardware design. Schematic diagram of the model.

Claims (9)

In a digital processor for neural network using VLSI technology, memory and general register block (10), program memory and control block (11), two-stage pipeline with separate memory configurations (WM, XM) for pipeline operation of operation Comprising a parallel-parallel multiplier (20), a parallel add / subtracter (21), a logic unit (22), and an accumulator (23) for performing various necessary operations, and a communication block for communication between processors ( Four blocks of 13); And a bus (BUS) in the form of a bus divided into a program bus 14 for up / down loading a program and a data bus 15 for transferring data. Digital Array Processor for Type Neural Networks. 2. The operator block (12) according to claim 1, wherein the operator block (12) is a two-stage pipelined parallel-parallel multiplier (20) for multiplying operations, a parallel add / subtractor (21) for adding and subtracting operations, logical operations and their associated operations. Logic unit 22 for performing arithmetic operation, accumulator 23 for storing the operation result again, carry flag (AC), overflow flag (AV), and a flag indicating that the value of the accumulator is negative / zero / positive (AN / AZ And a flag register (24) for storing data, a register (25) for temporarily storing data, and a mux for data selection (MUX). The digital multiplier for MIMD type neural network according to claim 1, wherein the multiplier 20 performs a two-stage pipeline operation and is connected in series with a multiplier / subtracter to perform a three-stage pipeline operation. Array processor. 4. The operator (12) according to claim 3, wherein the operator (12) separates a memory (WM) 30 having an input weight and a memory (XM) 31 having an input value for continuous data supply. A digital array processor dedicated to a MIMD type neural network, characterized by having a structured memory. 5. The data path of the operator (12) according to claim 4, wherein the data path of the operator (12) comes from outside with the accumulator (22) outside the accumulator (23) in order to select the shortest possible path and to equalize the path of the data flowing in the processor. A digital array processor for a MIMD type neural network, wherein the IO value is configured to flow only as short a path as possible. 2. The memory of claim 1, wherein the memory and general purpose register block comprises: general purpose registers used for repetitive use of variables to improve performance of a processor; SRAM 30 for storing weights, multiple pointer registers 32 for designating groups of contiguous memory addresses, adder 34 for calculating addresses, and registers 37 for temporarily storing addresses. A weight memory (WM) consisting of; SRAM 31 for storing input values, multiple pointer registers 33 for specifying groups of consecutive memory addresses, incrementers 35 for calculating addresses, and registers 37 for storing addresses arbitrarily. An input value memory (XM) consisting of; And an address bus (38) for up / down loading of data from outside of the array processor. The communication block (13) according to claim 1, wherein the communication block (13) selects data from a flag (IRS) 47 indicating a state for input, a buffer 42 for storing data, and one of four data upon data input. An input port block 40 comprising a receiving mux 44; Flags for status (ORS) 48 for output, buffer 43 for data storage, and demux 45 for sending data to one of four data buffers upon data output. MIMD type neural network dedicated digital array processor, characterized in that it comprises an output port block (41) including and a register (46) having a port for inputting and outputting data in advance. The digital array processor of claim 1, wherein the processor communicates in four directions and uses a communication direction of four directions in advance in the register 46. In a system consisting of a neural network dedicated digital array processor, a connection circuit 51 for connecting the processor 50 arranged in a 2-dimension form, a connection circuit 51 for connecting a host computer 53, and an external memory 54 (52), a data bus (55) capable of bidirectional data exchange and an address bus (56) for sending an address unidirectionally from a host computer (53). ※ Note: The disclosure is based on the initial application.