JPH0432480B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Object of the Invention [Field of Industrial Application] The present invention relates to improving the DC offset characteristics of a track-and-hold circuit.

[Conventional technology]

A track and hold circuit (hereinafter referred to as T/H circuit) is a circuit that has the function of passing or holding the introduced analog signal Vi according to a control signal.For example, it is used in the input stage of an AD conversion circuit. Used for etc.

FIG. 4 shows a conventional track and hold circuit. In the same figure, R ₁ and R ₂ are resistors, U is an amplifier,
Ch is a hold capacitor, and S ₁ to _{S 4} are switches. These switches S ₁ to _{S 4} are turned on and off by a track mode/hold mode switching control signal M (in this specification, this signal is simply referred to as a control signal M), and in FIG.
illustration is omitted. Here, the operations of switches _S1 to _S4 in track mode and halt mode are as follows.

During track: S ₁ and S ₃ are off, S ₂ and S ₄ are on. During hold: S ₁ and S ₃ are on, S ₂ and S ₄ are off.
(effect, transistor) input type low bias operational amplifier is used. In the circuit shown in FIG. 3, during tracking, an amplifier circuit with a gain of R ₂ /R ₁ is formed, and a capacitor Ch is connected to the output terminal of the circuit. Therefore, the voltage of capacitor Ch is the analog signal
The voltage follows the change in Vi.

On the other hand, during hold, a capacitor Ch is connected between the input and output terminals of the amplifier U, and the amplifier U holds and outputs the voltage of the capacitor Ch.

[Problem that the invention seeks to solve]

However, the T,H circuit shown in FIG. 4 has poor offset characteristics. The offset when holding is
3.V _ps (V _ps is the offset voltage of amplifier U). The reason is that when tracking, R ₁
=R ₂ , R ₁ +R ₂ /R ₁ =2. Furthermore, during hold, V _ps is added as is, so the total is tripled. Therefore, in order to obtain high accuracy, for example as an amplifier U, the offset V _ps
In order to reduce the size of the amplifier, a composite amplifier must be used, but this is complicated and undesirable in terms of response, noise, etc.

An object of the present invention is to provide a highly accurate T and H circuit that has a simple configuration and solves the offset problem as described above.

B "Structure of the Invention" [Means for Solving the Problems] In order to solve the above problems, the present invention has two input terminals A and B, and the polarity of the input stage is changed by a control signal when tracking. A differential amplifier that can be inverted during hold and an output terminal of this differential amplifier and one input terminal B.
A series circuit consisting of a resistor R ₃ and a capacitor Ch connected between the resistor R 3 and the capacitor Ch, a resistor R ₄ installed between the connection point of this resistor R ₃ and the capacitor Ch, and the circuit ground, and the other side of the differential amplifier during tracking. A resistor _R2 connected between the input terminal A and the output terminal of the input terminal A, a resistor _R1 connected to this input terminal A, a switch means s3 connecting the input terminal B to the circuit ground, and a differential voltage at the time of hold. switch means s2 for connecting the other input terminal A of the amplifier to circuit ground;
and means for switching the connection during the track and hold times, and the following relationship is provided between the four resistors.

R ₁ +R ₂ /R ₁ =R ₃ +R ₄ /R ₃ [Example] The present invention will be described in detail below with reference to the drawings.
FIG. 1 is a diagram showing an embodiment of a T,H circuit according to the present invention. In the same figure, R ₁ and R ₂ are resistors for setting the gain during tracking, R ₃ and R ₄
is the resistance for setting the gain during hold, s
-s3 is a switch that is turned on and off by the control signal M, Ch is a hold capacitor, and 10 is a differential amplifier whose input stage polarity can be inverted by the control signal M.

Differential amplifier 10 has two input terminals A, B and an output terminal F. Terminal A is connected to circuit ground via switch s2 and to terminal F via switch s1 and resistor _R2 .
Furthermore, terminal A is connected via switch s1 and resistor _R1 to a terminal into which an analog input signal Vi is introduced. On the other hand, terminal B is connected to circuit ground via switch s3, and capacitor Ch
and is connected to terminal F via resistor _R3 . Further, a resistor _R4 is provided between the connection point of the capacitor Ch and the resistor _R3 and the circuit ground.

A control signal M is applied to the switches s1 to s3 and the differential amplifier 10, causing switching operations to be performed during track and hold times.

During track: s1 and s3 are on, s2 is off When holding: s1 and s3 are off, s2 is on Control signal M is a signal consisting of two logic signals M _T and M _H , and when selecting track mode For example, the signal M _T becomes “high”, and conversely,
When selecting the hold mode, the signal M _H becomes "high".

FIG. 2 is a diagram showing a specific example of the configuration of the differential amplifier 10 shown in FIG. 1, in which the polarity of its input stage can be inverted by the control signal M. In Figure 2, A, B and F
are input/output terminals of the differential amplifier 10, M _T ,
M _H is a logic signal constituting the control signal M.

In the figure, 1 is an amplifier, 2 is a bias current source, _Q1 to _Q4 are transistors, and _J1 and _J2 are FETs. Known elements can be used for these. FETJ ₁ and J ₂ newly constitute a differential amplifier, and these two gates become input terminals A and B of the differential amplifier 10. Further, the two sources are connected to a bias current source 2. The drains of J ₁ and J ₂ are
It is connected to an inverting input terminal and a non-inverting input terminal of amplifier 1 via transistors Q ₁ to Q ₄ . Transistors Q ₁ and Q ₂ , Q ₃ and Q ₄ constitute a transistor switch for polarity switching, and the drains of FETs J ₁ and J ₂ are controlled by control signals M _T and M _H applied to each base. Switched to amplifier 1 and connected. Control signal M _T is applied to the bases of Q ₁ and Q ₄ , and control signal M _H is applied to the bases of Q ₂ and Q ₃ . The emitters of Q ₁ and Q ₂ are connected to the drain of J ₁ , and the emitters of Q ₃ and Q ₄
The emitter of is connected to the drain of _J2 .

Also, the collectors of Q ₁ and Q ₃ are connected to the non-inverting input terminal of amplifier 1, and the collectors of Q ₂ and Q ₄ are connected to the non-inverting input terminal of amplifier 1.
Connected to the inverting input terminal of amplifier 1.

The operations shown in FIGS. 1 and 2 will be explained.

<During Tracking> During tracking, switches s1 and s3 are on, and switch s2 is off. Also, since the control signal M _T is "high" at this time, transistors Q ₁ and Q ₄ are turned on, so the drain of FET J ₁ is connected to the non-inverting input terminal (+) of amplifier 1, and J ₂ The drain of is connected to the inverting input terminal (-). That is, the input terminal A of the differential amplifier 10 becomes an inverting input terminal, and the input terminal B becomes a non-inverting input terminal. Therefore, the output voltage V _OT of the differential amplifier 10 in FIG. 1 in this case is expressed by equation (1).

V _OT = −R ₂ /R ₁・Vi+R ₁ +R ₂ /R ₁・V _Off ...(1) V _Off is the offset voltage of the differential amplifier 10. At this time, the potential Vh charged in the capacitor Ch is
It is expressed by equation (2).

Vh=R ₄ /R ₃ +R ₄ ·V _OT (2) <Holding> During hold, switches s1 and s3 are off, and switch s2 is on. Also, since the control signal M _H is "high" at this time, transistors Q ₂ and Q ₃ are turned on, so the drain of FET J ₁ is connected to the inverting input terminal (-) of amplifier 1, and the drain of J _2. is connected to the non-inverting input terminal (+). That is, the input terminal B of the differential amplifier 10 becomes an inverting input terminal, and the input terminal A becomes a non-inverting input terminal. At this time, if the offset voltage V _Off does not change, the output V _OH is expressed by equation (3).

R ₄ /R ₃ +R ₄・V _OH =Vh−V _Off Therefore, V _OH =R ₃ +R ₄ /R ₄・(Vh−V _Off )……(3) From equations (2) and (1), V _OH =V _OT −R ₃ +R ₄ /R ₄・V _Off =−R ₂ /R ₁・Vi +R ₁ +R ₂ /R ₁・V _Off −R ₃ +R ₄ /R ₃・V _Off ……(4 ) Therefore, if R ₁ +R ₂ /R ₁ =R ₃ +R ₄ /R ₃ , then V _OH =-R ₂ /R ₁ ·Vi, and the offset term can be set to 0.

Note that the present invention is applicable to the switches s1 to s1 shown in FIG.
There is no need to limit the number to s3. FIG. 3 shows an example in which the number of switches is increased. According to the configuration shown in FIG. 3, the degree to which an input signal leaks to the output during holding, that is, characteristics such as feed-through are improved. This is because the midpoint between R ₁ and R ₂ is grounded by a switch, which reduces leakage through R ₂ . In FIG. 3, switches s1, s3, and s6 are turned on during track, and switches s2, s4, and s5 are turned on during hold. The rest of the configuration is the same as that in FIG. 1, so a description of its operation will be omitted.

Furthermore, although the polarity switching of the differential amplifier 10 is performed at the front stage of the amplifier 1 as shown in FIG. 2, it may be performed at the rear stage. In other words, the configuration of the amplifier 10 may be any configuration as long as the polarity of the input stage can be arbitrarily switched by the control signal M.

C. ``Effects of the present invention'' As described above, according to the present invention, the output during hold does not include offset, so it can be used in devices that require high precision and high stability, such as AD converters. I can do it.

Further, the present invention requires only a few additional circuit elements compared to the conventional circuit, and therefore the manufacturing cost does not increase much.

The switch shown in FIG. 1 has almost no potential applied to it when it is on or off, and is used at circuit ground potential, so it is easy to drive the switch.

Four resistors are required, but as you can see from the equation, it is the pair of R ₁ and R ₂ that determines the gain accuracy, and the pair of R ₃ ,
R ₄ does not require precision.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a configuration example of a T, H circuit according to the present invention, FIG. 2 is a diagram showing a configuration example of the differential amplifier 10 of FIG. 1, and FIG. 3 is a diagram showing a configuration example of a T, H circuit according to the present invention. FIG. 4 is a diagram illustrating a conventional example. _R1 to _R4 ...Resistance, s1 to s6...Switch,
Ch...Capacitor, 10...Differential amplifier.

Claims (1)

[Claims] 1. A differential amplifier having two input terminals A and B, and capable of inverting the polarity of the input stage during tracking and holding using a control signal; and an output terminal of this differential amplifier. and one input terminal B
A series circuit consisting of a resistor R ₃ and a capacitor Ch connected between the resistor R 3 and the capacitor Ch, a resistor R ₄ installed between the connection point of this resistor R ₃ and the capacitor Ch, and the circuit ground, and the other side of the differential amplifier during tracking. A resistor _R2 connected between the input terminal A and the output terminal of the input terminal A, a resistor _R1 connected to this input terminal A, a switch means s3 connecting the input terminal B to the circuit ground, and a differential voltage at the time of hold. switch means s2 for connecting the other input terminal A of the amplifier to circuit ground;
and means for switching the connection between the track time and the hold time, and a track/hold circuit characterized in that the following relationship is established between the four resistors. R ₁ +R ₂ /R ₁ =R ₃ +R ₄ /R ₃