SU943853A1 - Analog storage - Google Patents

Description

The invention relates to a measurement technique and can be used as an input device in an analog digital converter.

An analog memory device containing a key on a field-effect transistor, which is controlled by a gate circuit, and a capacitor are known. The control bus through the inverter is also connected to the gate of an additional field-effect transistor (switch), the drain of which is connected to the drain of the key field-effect transistor. An additional field effect transistor is used to compensate for spurious emissions due to the passage of control fronts through the parasitic capacitances of the switch. Emissions to the capacitor arrive at the para-phase (due to the inclusion of an inverter) and compensate each other 1.

However, complete emission compensation is possible only if the field-effect transistor parameters are completely identical and the pulse fronts are strictly equal in the control bus and at the output of the inverter, which is practically difficult under serial production conditions.

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An analogue memory cell is also known to contain two series-connected keys on field-effect transistors, the gates of which are connected to the zero bus through capacitors, and the control voltage is applied to the moving contact of the variable resistor connected between the gates of both keys. The inclusion of two consecutive keys, one of which advances or lags behind in operation due to the inclusion of adjustable RC circuits in the gates of both transistors, makes it possible to eliminate the interference signal on the storage capacitor with a high degree of accuracy, exclude the inverter from the circuit and apply any pairs of transistors of the same type without preliminary selection by parameters (2).

However, this memory cell has a large aperture error caused by an increase in the time of the switched keys due to the introduction of

25 capacitors in the circuit of the transistor gates.

The closest in technical essence to the present invention is an analog storage device;

30 contains a key on a field-effect transistor, a storage capacitor, a compensating capacitor, two keys on bipolar transistors, to which different polarity control signals are supplied. The collector of one of the keys is connected to the gate of the key field-effect transistor, the collector of the second bipolar key is connected to one plate of the compensating capacitance, the second plate of which is connected to the output of the key on the field-effect transistor.

Due to the presence of adjustment in the collector of the second bipolar key (POSSIBLE change of the compensating signal coming through the compensating capacitance. This device also provides a small aperture error, since there are no reactive elements in the gate circuit of the key field-effect transistor (3.

A disadvantage of the known device is the relatively low memory accuracy due to the compensation of the passage of the emissions from the switching voltage to the storage capacity. This is due to the fact that the field-effect transistor control circuit is based on saturated keys, and when switching from sampling mode to filling mode, one key bipolar transistor switches from locking mode to saturation mode, while the other key transistor switches from saturation mode to lock up If the transition from locking to saturation in transistors is carried out in a relatively short time (i.e. with a steep front), then the reverse switching time is usually longer, i.e. Switching is carried out with a long front due to the process of resorption of carriers in the base of the bipolar transistor. Moreover, the duration of the out-of-out front depends on a variety of factors — on the ambient temperature, the coefficient of transfer of the current of the transistor, the magnitude of the base current, etc. Since the value of the interfering Signal on the storage capacitance depends on the duration of the front of the controlling and compensating signal, this causes its dependence on the listed factors, and therefore causes a deterioration in the accuracy and stability of the entire storage device.

The purpose of the invention is to improve the accuracy of the device.

The goal is achieved in that the device containing the first amplifier, the output of which is connected to the first storage element, for example one of the plates of the first capacitor, the second accumulation element, for example the second capacitor, one of which plates is connected to the zero potential bus, the other capacitor plates connected to the output of the key and are the output of the device, the first input of the switch is connected to the input bus, the second amplifier, the output of which is connected to the second input of the switch, the first inputs of amplifiers with the current switch, the first and second nonlinear elements, the first terminals of which are connected respectively to the current switch outputs, the first and second current switch inputs are the control inputs of the device, the third current switch input connected to the first power bus, the terminals of the nonlinear elements are connected to the second power bus, the third terminals of the nonlinear elements are connected to the corresponding second inputs of the amplifiers and to the corresponding first terminals of the nonlinear elements ENTOV, amplifier outputs are connected via resistors to the first supply bus.

The drawing shows a functional diagram of the proposed device.

The device contains amplifiers 1 and 2, nonlinear elements 3 and 4, a current switch 5, a bus 6 of zero potential, storage cells, such as capacitors 7 and 8, a switch 9, an input bus 10, power buses 11 and 12, an output of device 13.

Current switch 5 is made on transistors 14 and 15; amplifier 1 on the transistor 16 and the resistor 17; amplifier 2 - transistor 18 and resistor 19; nonlinear elements on transistors 20 and 21; a switch 9 on the field-effect transistor 22. The emitters of the transistors 14 and 15 are connected to the power supply bus 11 via a resistor 23. The transistors 16 and 20, 18 and 21 form current reflectors, the loads of which are resistors 17 and 19, respectively.

The proposed device operates as follows.

In the initial state, the control inputs Bx and Bx 2 are supplied. The levels are provided to ensure the locking of the transistor 14 and the opening of the transistor 15 of the current switch 5. The collector current of the transistor 15 provides a direct bias of the transistor 21 of the nonlinear element 4, which causes the current to flow through the transistor 18 and the collector current of the transistor 18 is equal to the collector current of the transistor 15 with identical parameters of the transistors 18 and 21 (this is the principle of the current reflector); The collector current of transistor 18 creates a voltage drop across resistor 19,

on the gate of the half transistor 22 and keep the key 9 in the open state in the akneee. The input signal is reproduced at the output of the device with a delay characteristic of the integrating Rc circuit, where R is the parasitic resistance of the off transistor 22; C is the value of the capacitor 8.

When switching to memory mode, logic levels are switched at inputs B) (4 and VXy and the current set by resistor 23 is switched by transistors 14 and 15 into current reflector formed by transistors 20 and 16. At the same time, current of current reflector at transistors 18 and 21 is turned off. This ensures the formation of a negative voltage drop across the gate of the field-effect transistor 22, as a result of which the transistor 22 closes and the device switches to the voltage storage mode present in this MONteHT on the capacitor 8. At the same time, the resistor 17 forms the positive voltage drop coming from the movable contact of resistor 17 through capacitor 7 to capacitor 8, thereby compensating for the passage of the interfering signal through the parasitic capacitances of transistor 22. By changing the position of the moving contact of resistor 17, the amplitude of the compensating signal is changed and possible compensation of the interference is not condenser 8.

A characteristic feature of the proposed device is the use of unsaturated switches (current switches) in it as drivers of control and compensation signals. This provides a high speed of the device with a small amount of aperture errors, almost equal in duration to the fronts of the control and compensating signals. The device does not require an additional inverter to receive a compensating signal, since in the symmetric switching circuit the inverse control signal is generated automatically. The use of current reflectors makes it possible to obtain control resistor on the gate of the key transistor 22, varying from a magnitude-E to a magnitude + E, i.e. In this device, the voltage of the power sources is fully used to form a control signal, which cannot be achieved in a conventional current switch circuit, where the signal to be generated is usually significant (less than the values of the supply voltages. The increase in the control voltages at the gate of the transistor 22) expands switching signal input range. The use of a symmetric switching circuit provides power supply and housing circuits magnified by magnitude bursts, reduces the level of pickup and It improves the accuracy of the storage Ms1lyh signgshov.

Claims (3)

1. Author's certificate of the USSR 462216, cl. G 11 C 27/00, 1974. 2. Authors certificate of the USSR 733031, cl. G 11 C 27/00, 1979. 3. Instruments and elements of automation and computing. ExpressInfo Aci, 36, 1979, p. 23 (prototype). jk / w.