SU762190A1 - Readout amplifier - Google Patents

Description

The invention relates to a pulse technique, can be used to build digital devices.

Lime high-speed current switch containing diode array, trigger, controlled keys [1].

The drawbacks of the device is its complexity, low reliability.

The closest technical solution, taken as a prototype, is a read amplifier, containing a symmetric trigger with cross-links on the first, second, third and fourth MDP transistors, two restoring MOS transistors, connected by their sources to the outputs of the information and reference shift registers, respectively, to the first gates clock bus, drains - to the power bus [2].

The disadvantage of this device is a small dynamic range.

The purpose of the invention is to expand the dynamic range of the circuit.

This goal is achieved by the fact that the reading amplifier, containing a symmetric trigger with cross-links on the first, second, third and fourth MOS transistors, the first and second restoring MOS transistors, the sources of which are connected respectively to you

moves information and reference shift registers, closures - to the first clock bus, and drains - to the power bus, entered the first and second switching,

5 the first and second grounding, the first and second input MOSFETS, the gates of the input transistors are connected respectively to the outputs of the information and reference registers, the drain of the first input 10 and the gate of the second switching MDPtransistor are connected to one output of the trigger, the drain of the second input and the gate of the first switching MIS- transistors - to the opposite output of the trigger 15, the sources of the first and second input MOS transistors are connected respectively to the drains of the first and second switching MIS transistors, the first the grounding MOS transistor is connected 20 between the connection point of the sources of the switching MOS transistors and the device common bus, the second grounding MDP transistor is between the connection point of the sources of the first and second MIS transistors of the trigger and the device common bus, the drains of the third and fourth transistors of the trigger are connected to the power bus, their gates - to the second clock shi1-sh, the gate of the first grounding MDP30 transistor - to the third clock bus,

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the gate of the second grounding MOS transistor - to the fourth clock bus.

The drawing shows a diagram of the device.

The device contains a trigger on the first, second, third, fourth MOS transistors 1-4, the first and second restoring MOS transistors 5, 6, information and reference shift registers 7.8, the first clock bus 9, the power bus 10, the first and second input MOSFET 11, 12, the first and second switching MOSFET 13, 14, the first and second grounding MOSFET 15, 16, the second, third, fourth clock bus 17-19.

On the first clock bus, an impulse F _b is fed to the second clock bus - an impulse F ₂ , on a third clock bus - an impulse F ₃ , on a fourth clock bus - an impulse F ₄ .

The device works as follows. During the pulse Φι, the reducing MOSFETs 5, '6 are open, and the potentials of the reading nodes (outputs of registers 7, 8) increase to equally high levels. Since the grounding MIS transistors 15, 16 are closed, and the load MOS transistors 3, 4 of the flip-flop are open (F ₂ , F ₃ pulses are low, and F ₄ - high levels), the voltage at the output nodes (outputs of registers 7 , 8) are also growing to equally high levels. The end pulse F F _{s 4} readers nodes (outputs of the registers 7, 8) pass into the floating potential mode and load MDPtranzistory 3, 4 are closed. At the same time, the readout charge comes from the output of register 7, and the reference charge from the output of register 8. As a result, the initial voltage imbalance at the gates of the input MOS transistors 11, 12 and the corresponding unbalance of the resistances of the channels of the MIS transistors 11, 12 are created.

With the arrival of the pulse F ₂ , the grounding MOS transistor 15 is opened, and the capacitances connected to the output (outputs of registers 7, 8) begin to discharge through the series-connected MOS transistors 11, 13, 15 and 12, 14, 16, respectively. When reading the charge of a logical unit, the resistance of the channel of the MIS transistor 11 is greater than the resistance of the channel of the MIS transistor 12. Therefore, the drain voltage of the MOS transistor 4 decreases faster than the drain voltage of the MDP transistor 3 and an output voltage imbalance occurs. Due to the presence of positive feedback in the bit circuits (due to the cross-connection of the gates of the switching MOS transistors 13, 14), the regenerative process occurs in the process of the output voltage decrease and the initial imbalance is amplified.

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With the arrival of pulses F ₃ , F ₄ , MOSFETs 3, 4, 16 open, and the trigger is connected to the power bus 10 and the common point of the circuit. As a result, the unbalance of the output voltages is amplified, as in conventional trigger read amplifiers used in single-transistor random-access memory devices. When reading the charge of logical zero, the channel resistance of the input MOS transistor 11 is less than the channel resistance of the MOS transistor 12. With the arrival of the pulse F] and the end of the pulses F ₂ , F _{3, the} reducing MDP transistors 5, 6 open, 14 and active MOS transistors 1, 2 triggers are disconnected from the common point of the circuit. As a result, a high voltage level is restored, i.e. the circuit returns to its original state.

Claims (1)

Claim A read amplifier containing a symmetric trigger with cross-connections on the first, second, third, fourth MOS transistors, the first and second restoring MOS transistors, whose sources are connected respectively to the outputs of the information and reference shift registers, gates to the first clock bus, and drains - to the power bus, characterized in that, in order to expand the dynamic range, the first and second switching, first and second grounding, first and second MOS transistors, and the gates input MOS transistors are connected respectively to the outputs of the information and reference resistors, the drain of the first input and the gate of the second switching MOS transistors are connected to one output of the trigger, the drain of the second input and the gate of the first switching MOS transistors to the opposite output of the trigger, the sources of the first and second input MOS transistors are connected respectively to the drains of the first and second switching MOS transistors, the first grounding MOS transistor is connected between the source connection point and the switch transistors and a common bus device, the second grounding MDPtransistor - between the connection point of the sources of the first and second transistors of the trigger and the common bus device, drains of the third and fourth transistors of the trigger are connected to the power bus, and their gates to the second clock bus, while the gate of the first grounding MDPtransistor is connected to the third clock bus, and the gate of the second ground bus 762190 five MOSFET - to the fourth clock bus.