JPH04324379A - Testing apparatus for integrated circuit - Google Patents

Abstract

PURPOSE:To reduce labor for preparing test data and to shorten a testing time. CONSTITUTION:A field programmable gate array 3 has procedure data for testing an integrated circuit stored therein and generates the test pattern and expected value pattern inputted to the integrated circuit according to the procedure data and compares the output pattern from an integrated circuit 5 to be tested to which the test pattern is inputted with the expected value pattern to output the comparison result. A load means 2 outputs the procedure data for testing the integrated circuit to the field programmable gate array 3. A connection means 4 connects the integrated circuit 5 to be tested to the field programmable gate array 3 and an output means 6 outputs the test result obtained from the field programmable gate array 3 to the outside.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit testing device, and more particularly to an integrated circuit testing device for confirming that a manufactured integrated circuit functions normally.

0002

2. Description of the Related Art Conventionally, this type of integrated circuit testing equipment loads an input pattern created in advance for testing an integrated circuit under test and an expected value pattern of its output, and then tests the integrated circuit under test. The integrated circuit under test was tested to see if it operated correctly by inputting input patterns one by one and checking whether the output values matched the expected values.

0003

[Problems to be Solved by the Invention] The conventional integrated circuit testing apparatus described above loads the input pattern and the expected value pattern of the output that have been created in advance for testing the integrated circuit under test, and then tests the integrated circuit under test. Since we were testing whether the integrated circuit under test operates correctly by inputting input patterns to the circuit one by one and checking whether the output value matches the expected value, the input pattern and expected value pattern It had the disadvantage of requiring a large amount of preparation.

[0004] Furthermore, in order to enable testing of a plurality of types of integrated circuits, the integrated circuit testing apparatus also requires application of an input pattern,
In addition, since the output pattern and the expected value pattern are compared by software means, it has the disadvantage that the test time for the integrated circuit becomes long.

[0005] An object of the present invention is to provide an integrated circuit testing device that can reduce the effort required to create test data and shorten testing time.

[0006]

[Means for Solving the Problems] The integrated circuit testing device of the present invention compares a pattern output from the integrated circuit when a test pattern is input to the integrated circuit with a preset expected value pattern to test the integrated circuit. (A) storing procedure information for testing the integrated circuit, generating the test pattern and the expected value pattern to be input to the integrated circuit according to the procedure information; a field programmable gate array that compares an output pattern output from an input integrated circuit under test with the expected value pattern and outputs the result; (B) procedure information for testing the integrated circuit; and (C) connection means for connecting the integrated circuit under test to the field programmable gate array.

[0007]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an integrated circuit testing apparatus according to the present invention.

As shown in FIG. 1, the integrated circuit testing apparatus of this embodiment stores procedure information for testing an integrated circuit, and generates a test pattern and an expected value pattern to be input to the integrated circuit according to the procedure information. , a field programmable gate array that compares an output pattern from an integrated circuit under test to which a test pattern is inputted with an expected value pattern, and outputs the result.
Able Gate Array (hereinafter referred to as FPGA)
3. Procedural information for testing integrated circuits is
Loading means 2 outputs to PGA3, F
It is comprised of a connecting means 4 that connects to the PGA 3, and an output means 6 that outputs the test results obtained from the FPGA 3 to the outside.

Next, the operation will be explained.

In FIG. 1, loading means 2 inputs into FPGA 3 a test procedure 1 that procedurally represents a method for generating an input pattern and its expected value pattern. FPGA
In step 3, according to test procedure 1, a logic circuit indicated by test procedure 1 is automatically constructed from a logic circuit using a built-in gate array.

Next, in the FPGA 3 in which the logic circuit according to the test procedure 1 is configured, the test procedure is executed according to the test procedure 1 by operating the configured logic circuit, and the generated input pattern is as follows. The signal is inputted to the integrated circuit under test 5 through the connecting means 4 . Further, the FPGA 3 reads an output pattern output from the integrated circuit to which the input pattern has been inputted, through the connecting means 4, and compares the expected value generated from the logic circuit with the output pattern output from the integrated circuit, If they match, a signal indicating that the test is normal is output to the output means 6, and if they do not match, a signal indicating that the test is defective is output to the output means 6.

In this way, an FPGA that automatically generates an input pattern and an expected value pattern is provided, and this FPGA
By connecting A and the integrated circuit under test and testing the integrated circuit, it is possible to reduce the effort required to create test data and to shorten the test time.

[0014]

As explained above, the integrated circuit testing device of the present invention is provided with a field programmable gate array that automatically generates an input pattern and an expected value pattern. - By connecting the array and the integrated circuit under test to test the integrated circuit, it is possible to reduce the effort required to create test data and to shorten the test time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an integrated circuit testing device of the present invention.

[Explanation of symbols]

1 Test procedure 2 Loading means 3 Field programmable gate array (FPGA) 4 Connection means 5 Integrated circuit under test 6 Output means

Claims (1)

[Claims] 1. An integrated circuit testing device that tests the integrated circuit by comparing a pattern output from the integrated circuit with a preset expected value pattern when a test pattern is input to the integrated circuit, comprising: Procedure information for testing an integrated circuit is stored, the test pattern and the expected value pattern are generated to be input to the integrated circuit according to the procedure information, and the output is output from the integrated circuit under test to which the test pattern has been input. a field programmable gate array for comparing a pattern with the expected value pattern and outputting the result; (B) loading means for outputting procedural information for testing the integrated circuit to the field programmable gate array; , (C) connection means for connecting the integrated circuit under test to the field programmable gate array.