JPH09203771A - Data processing method and inspecting device for use in it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To compress the test data to a great extent, lessen the capacity of test data, and enhance the efficiency in the inspecting operations. SOLUTION: The regular form patterns and deformation patterns prepared by a test pattern producing part 2 are accommodated in an accommodation part 3a. Among the regular form patterns, any desired is stored in a memory part 3d, and a CPU 3c overwrites a deformation pattern to make Test T1 accommodated in the part 3a on that regular form pattern which is stored in the memory part 3d, and thus the intended test pattern is prepared, and thereupon the inspection of Test T1 is executed. After inspection, the deformation pattern to perform Test T2 is taken in from the accommodation part 3a, and this pattern is again overwritten on the regular form pattern stored in the memory part 3d, and the inspection of the test T2 is executed. Repetition of this operating cycle produces test patterns in (n) pieces, and test runs are conducted till Test Tn.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing method and an inspection apparatus used therefor, and more particularly to a technique effective when applied to compression of a test pattern for inspecting the electrical characteristics of a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art According to a study made by the present inventor, for example, in an inspection apparatus for screening a semiconductor integrated circuit device, a Hi signal and a Lo signal are applied in a test sequence, that is, a test pattern is applied to the semiconductor integrated circuit. The electrical characteristics of the semiconductor integrated circuit device are inspected by applying to each pin of the device.

The test pattern stored in the inspection apparatus is compressed by storing only the value at the time when the signal such as the Hi signal to the Lo signal or the Lo signal to the Hi signal changes. It is being appreciated.

[0004] As an example in which this type of screening is described in detail, as an example, November 25, 1993, published by Press Journal, Inc.
Volume 2, No. 16, Shigetoshi Kiura (ed.) "'94 latest semiconductor process technology-Technology &Equipment"
-"P373 to P376, and this document describes trends in testing technology in semiconductor integrated circuit devices.

[0005]

However, the inventors of the present invention have found that the above-described test pattern compression technique has the following problems.

In recent years, as the scale of semiconductor integrated circuit devices has increased, test data has also tended to increase.

As a result, the capacity of the memory for storing the test data also increases, resulting in a larger size of the inspection apparatus and a higher cost of the inspection apparatus itself.

Further, as the test data increases, the transfer time of the test data becomes longer and the inspection cost also increases.

An object of the present invention is to provide a data processing method capable of significantly compressing test data to reduce the test data capacity and improving inspection efficiency, and an inspection apparatus used therefor.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the data processing method of the present invention separates a plurality of test data for inspecting a semiconductor integrated circuit device by a scan method into a plurality of fixed patterns having no data change and a plurality of modified patterns having data change. , An arbitrary one of the plurality of fixed patterns and a plurality of modified patterns are stored, and any one of the fixed patterns is stored.
A plurality of deformation patterns corresponding to one fixed pattern are repeatedly overwritten to generate a plurality of test data.

In the data processing method of the present invention, the fixed pattern is scan-in data which is data of a writing procedure to a flip-flop and scan-out data which is data of a reading procedure of the flip-flop, and the modified pattern. Is composed of a scan-in value which is write data to the flip-flop and a scan-out expected value which determines whether the output pattern output from the semiconductor integrated circuit device is acceptable or not.

From the above, a plurality of test patterns corresponding to each inspection can be generated by storing only one arbitrary fixed pattern having no data change, so that the data memory capacity can be reduced. Therefore, the transfer time of the test pattern can be significantly reduced.

Further, the inspection apparatus of the present invention separates a plurality of test data for inspecting a semiconductor integrated circuit device by a scan method into a plurality of fixed patterns having no data change and a plurality of modified patterns having data change. A test pattern generating means for generating and a test pattern data editing means for generating a test data by synthesizing a plurality of modified patterns with any one of the fixed patterns generated by the test pattern generating means. And are provided.

Further, in the inspection device of the present invention, the test pattern data editing means stores the arbitrary one fixed pattern and a plurality of modified patterns, and the one fixed shape stored in the storage means. The data generating means is configured to repeatedly overwrite a plurality of modified patterns corresponding to the pattern to generate a plurality of test data.

Further, in the inspection apparatus of the present invention, the fixed pattern generated by the test pattern generating means is scan-in data which is data of a writing procedure to the flip-flop and scan-out which is data of a reading procedure of the flip-flop. The modified pattern generated by the test pattern generation means, which is data, is based on a scan-in value that is write data to the flip-flop and a scan-out expected value that determines pass / fail of an output pattern output from the semiconductor integrated circuit device. It will be.

From the above, if only one arbitrary fixed pattern having no data change is stored in the storage means, the test pattern data editing means generates a plurality of test patterns corresponding to each inspection. The memory capacity can be reduced, and the test pattern transfer time can be significantly reduced.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor integrated circuit device inspection apparatus according to an embodiment of the present invention, and FIG.
4 is a flow chart of data processing in the inspection apparatus according to one embodiment of the present invention, FIG. 3 is an explanatory diagram of an inspection procedure in the inspection apparatus according to one embodiment of the present invention, FIG.
(A) is a configuration diagram of a test pattern before inspection according to an embodiment of the present invention, (b) is a configuration diagram of a test pattern at the time of inspection, and FIG. 5 is according to an embodiment of the present invention It is a schematic diagram of a test pattern before and after data processing.

In the present embodiment, the inspection apparatus 1 for inspecting a semiconductor integrated circuit device by a scan method is, for example, an object to be inspected based on data such as various set values of an object to be inspected DUT such as a semiconductor integrated circuit device. A test pattern generation unit (test pattern generation means) 2 for generating a plurality of test patterns (test data) TP (FIG. 4B) for performing a plurality of inspections in the DUT is provided.

The plurality of test patterns TP generated by the test pattern generator 2 are pattern data required for a writing procedure to a flip-flop (hereinafter referred to as FF) provided with a scan circuit in the DUT. Is scan-in data or pattern data necessary for FF read-out procedure. For example, various types of data such as FF addressing pattern and scan-out data which is an SE (Scan Enable) signal for activating or deactivating a scan circuit. The fixed pattern TTP (FIG. 4A) in which the pattern does not change in the inspection and the modified pattern HTP (FIG. 4A) in which the pattern changes in each inspection such as the scan-in value and the scan-out expected value.
(A)).

Then, a plurality of fixed patterns TTP and a plurality of modified patterns HT generated for each inspection.
P is generated separately.

In addition, the inspection device 1 has a fixed pattern TTP.
And a test pattern editing unit (test pattern data editing means) 3 for compressing data in the modified pattern HTP is provided, and the fixed pattern TTP and the modified pattern HTP output from the test pattern generation unit 2 are input to the test pattern editing unit 3. Are connected as they are.

Then, the test pattern editing unit 3 generates the fixed pattern TT generated by the test pattern generating unit 2.
A storage unit (storage unit) 3a for storing P and the modified pattern HTP is provided, and the test pattern generation unit 2 is connected to the storage unit 3a.

Further, the test pattern editing unit 3 includes an input unit 3b to which the fixed pattern TTP and the modified pattern HTP stored in the storage unit 3a are input, and a test pattern T.
A central processing unit (data generation unit) 3c that controls the generation of P and the overall control of the test pattern editing unit 3 and a storage unit (storage unit) 3d that stores any one fixed pattern TTP among a plurality of fixed patterns TTP. Is provided, the input unit 3b is connected to the central processing unit 3c, and the storage unit 3d is also connected to the central processing unit 3c.

Further, the test pattern editing section 3 outputs an output section 3e for outputting the various test patterns TP thus generated.
In addition, a display unit 3f for displaying data and the like is provided, and the test pattern TP generated by the central processing unit 3c is connected so as to be output via the output unit 3e. 3c is connected.

Further, in the inspection device 1, the tester 4 for inspecting the inspection object DUT based on the pattern data TP output from the output section 3e in the test pattern editing section 3.
A display unit 5 for displaying the inspection result and the like is provided, and the tester 4 is connected to the test pattern editing unit 3 and the display unit 5.

Next, the operation of this embodiment will be described with reference to the flowchart of FIG.

First, data such as set values for various inspections are input to the test pattern generator 2 to separately generate the fixed pattern TTP and the modified pattern HTP.

Here, for example, when there are n kinds of inspections from the tests T1 to Tn, there are n fixed patterns TTP.
And n modified patterns HTP will be generated.

The fixed pattern TTP and the modified pattern HTP are generated by the test pattern generation unit 2
Standard pattern TT, not generated by hardware
It may be generated by software using a program for generating P and the modified pattern HTP.

Next, a plurality of generated fixed patterns TT
P and the plurality of modified patterns HTP are output from the test pattern generation unit 2 and stored in the storage unit 3a.

Here, the fixed pattern TTP and the modified pattern HTP stored in the storage section 3a are formed by separately storing a plurality of fixed patterns TTP and a plurality of n kinds of modified patterns HTP of the tests T1 to Tn. There is.

After that, among a plurality of fixed patterns TTP,
Any one fixed pattern TTP is stored in the storage unit 3d via the input unit 3b of the test pattern editing unit 3 (step S101).

Then, the central processing unit 3c inputs, from the storage unit 3a, a deformation pattern HTP corresponding to the fixed pattern TTP stored in the storage unit 3d among the plurality of deformation patterns HTP stored in the storage unit 3a. It is taken in via the unit 3d and overwritten on the fixed pattern TTP (step S102).

Next, the test pattern TP for performing the test T1 in which the fixed pattern TTP is overwritten with the modified pattern HTP is output to the tester 4 via the output unit 3e of the test pattern editing unit 3.

After that, the tester 4 executes the inspection of the inspection object DUT by the test T1 based on the input test pattern TP, for example, by repeating the process shown in FIG. 3 (step S103).

Then, the scan-out value, which is the output pattern output from the inspection object DUT, and the expected scan-out value are compared, and the acceptance / rejection of the inspection object DUT is judged, for example,
It is displayed on the display unit 5.

When the test T1 is completed (step S10)
4), of the n modified patterns HTP, the modified pattern HTP for performing the test T2 is fetched from the storage unit 3a and stored again in the storage unit 3d.
The modified pattern HTP is overwritten on P, and the inspection by the test T2 is performed.

Further, since there are a plurality of modified patterns HTP, n test patterns TP are generated by the test pattern editing section 3 by repeating steps S102 and S103, and the test is repeated n times up to the test Tn. Will be performed (step S105).

Further, when there are a plurality of fixed patterns TTP, the same number of steps as the fixed patterns TTP are used in step S.
The steps 101 to S103 are repeated.

Therefore, this central processing unit 3c is shown in FIG.
As shown in (a), one type of fixed pattern TTP includes a plurality of n types of modified patterns HT from tests T1 to Tn.
By repeatedly overwriting P, as shown in FIG. 4B, n test patterns TP from test T1 to test Tn can be generated.

Here, in FIG. 4, the hatched quadrangle is the deformed pattern HTP, and the other portions are the fixed pattern TTP.

When the tests T1 to Tn are inspected, the uncompressed test pattern TP shown on the left side in FIG. 5 is converted into one type of fixed pattern TTP as shown on the right side in FIG. It is only necessary to overwrite the n types of modified patterns HTP, and it is not necessary to store the other fixed patterns TTP (shown by dotted lines) after the test T2.

Again, in FIG. 5, similarly, the hatched quadrangle is the deformation pattern HTP,
The other part shows the fixed pattern TTP.

As a result, according to the present embodiment, the data can be significantly compressed by the test pattern editing unit 3, so that the transfer time of the test pattern TP to the tester 4 can be shortened and the inspection efficiency of the DUT to be inspected is improved. Can be made.

Further, a large-capacity storage device for storing the test pattern TP is unnecessary, and the cost of the inspection device 1 can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0050]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the test pattern data editing means repeatedly generates a plurality of test patterns corresponding to each inspection by repeatedly overwriting the modified pattern on the fixed pattern having no data change. The data memory capacity can be reduced, and the test pattern transfer time can be significantly reduced.

(2) Further, in the present invention, according to the above (1), the semiconductor integrated circuit device can be efficiently inspected, and a large-capacity memory is not required, so that the cost and man-hours of the inspection device are reduced. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram of an inspection apparatus for a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a flowchart of data processing in the inspection device according to the embodiment of the present invention.

FIG. 3 is an explanatory diagram of an inspection procedure in the inspection device according to the embodiment of the present invention.

FIG. 4A is a configuration explanatory diagram of a test pattern before inspection according to an embodiment of the present invention, and FIG. 4B is a configuration explanatory diagram of a test pattern during inspection.

FIG. 5 is a schematic diagram of test patterns before and after data processing according to an embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 inspection device 2 test pattern generation part (test pattern generation means) 3 test pattern editing part (test pattern data editing means) 3a storage part (storage means) 3b input part 3c central processing part (data generation means) 3d storage part (storage) Means) 3e output section 3f display section 4 tester 5 display section DUT inspected object TP test pattern (test data) TTP fixed pattern HTP deformation pattern T1 to Tn test

Claims (5)

[Claims] 1. A data processing method of a plurality of test data for inspecting a semiconductor integrated circuit device by a scan method, wherein the plurality of test data in each inspection are a plurality of fixed patterns having no data change and a change of data. The plurality of modified patterns that are separated into a plurality of modified patterns, store one of the fixed patterns and the plurality of modified patterns among the plurality of fixed patterns, and correspond to the arbitrary one of the fixed patterns. Is repeatedly overwritten to generate a plurality of test data, which is a data processing method. 2. The data processing method according to claim 1, wherein the fixed pattern is scan-in data which is data of a writing procedure to a flip-flop and scan-out data which is data of a reading procedure of the flip-flop, A data processing method, wherein the modified pattern is a scan-in value that is write data to the flip-flop and a scan-out expected value that determines pass / fail of an output pattern output from the semiconductor integrated circuit device. 3. An inspection apparatus for performing a predetermined inspection of a semiconductor integrated circuit device by a scan method, wherein a plurality of test data in each inspection are subjected to a plurality of fixed patterns having no data change and a plurality of modified patterns having a data change. And a test pattern generating unit that generates the test data by combining the plurality of modified patterns with any one of the standard patterns generated by the test pattern generating unit. An inspection apparatus comprising: a test pattern data editing unit for generating the test pattern data. 4. The inspection apparatus according to claim 3, wherein the test pattern data editing unit stores a single fixed pattern and the plurality of modified patterns, and an arbitrary storage unit stored in the storage unit. 2. An inspection apparatus comprising: a data generating unit that repeatedly overwrites the plurality of modified patterns corresponding to the one fixed pattern of 1 to generate a plurality of test data. 5. The inspection apparatus according to claim 3, wherein the fixed pattern generated by the test pattern generation means is scan-in data that is data of a writing procedure to a flip-flop and a reading procedure of the flip-flop. It is scan-out data which is data, and the pass / fail judgment of the scan-in value, which is the write-in data to the flip-flop, and the output pattern output from the semiconductor integrated circuit device, is performed for the modified pattern generated by the test pattern generation means. The inspection device characterized by the expected scan-out value.