JPH0778495A - Semiconductor storage device with built-in high speed self testing circuit - Google Patents

Abstract

PURPOSE:To reduce a testing cost and to reduce the shipping cost of an LSI by shortening the testing time of a memory LSI and diagnosing a high speed operation using of an expensive and low speed tester. CONSTITUTION:At the time of a testing, the inside of the LSI is operated with an external multiplied frequency by providing an internal clock generating PLL for multiplying an external clock. At this time, circuits (are an AGU and a DGU respectively) generating automatically the one part of an address and a data inputting signal with an internal frequency are mounted on a device. The data inputting signal is constituted so that the signal is started by an input signal from the outside and the '0' and '1' of the signal are switched alternately with the internal frequency. Moreover, a decision circuit DC deciding whether the output signal from the internal circuit is of the alternation of '0' and '1' or not, and the output signal coincides with an expected value from the outside or not is mounted in the device. With those circuits, the memory circuit of the inside of the LSI is tested with the external multiplied frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a large scale, a short test time, and a low cost.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit (LSI),
When diagnosing (testing) the internal operation of the LSI, a test pattern is applied to the input pin from the outside, and it is checked whether the LSI outputs the expected value from the output pin. Particularly, in a memory LSI, an address designation signal, a write data signal, and a write / read control signal are given as inputs, and a write / read operation of information to / from a memory cell is performed for all memory cells while changing an input address pattern. To do. Figure 3
FIG. 4 shows a circuit configuration example of a conventional memory, and FIG. 4 shows its operation timing chart. Since the LSI shown in FIG. 3 operates in synchronization with the external clock frequency (f), this LSI is
In order to diagnose the function of, the input signal as shown in FIG. 4 is input at the frequency f, and at the same time, an apparatus for determining the output result is required. Currently, a dedicated device called an LSI tester is used to perform the functional test of these LSIs. FIG. 5 shows a configuration diagram when performing a functional diagnosis of an LSI using an LSI tester. The LSI tester has a test pattern generator, an expected output value pattern generator, and an output result judging device. The signal generated by the test pattern generator is applied as an input signal to the LSI under test,
The output signal from the LSI under test is compared with the expected value in the tester to judge whether the LSI under test is good or bad. On the other hand, on the other hand, a diagnostic circuit for the LSI function, which this LSI tester has, is built in the LSI, and the circuit is used to
An invention for testing itself is described in JP-A-63-184989.

[0003]

However, the above-mentioned LSI
The tester is required to have at least an operation speed higher than that of the LSI to be evaluated. However, due to the increase in speed and scale of LSIs in recent years, high-speed L
Investment in the SI tester is required, and the increase in the LSI tester occupying time for testing the LSI is one of the major factors increasing the shipping cost of the LSI. Further, in recent years, since the speed of the interface circuit with the outside of the LSI is not accompanied by the speed increase of the LSI internal circuit, it is possible to correctly evaluate the operation speed of the LSI internal circuit that can operate at high speed. The problem of not being is emerging.

An object of the present invention is to provide an auxiliary additional circuit in the LSI for diagnosing the function of the LSI itself at a high speed, thereby improving the test efficiency and shortening the test time, and also for a low-speed tester. This enables high-speed LSI diagnosis and realizes a reduction in LSI shipping cost.

[0005]

SUMMARY OF THE INVENTION A first invention is a circuit for internally multiplying the frequency of a signal applied from the outside for the diagnosis of its function, and an output result corresponding to an input signal of the multiplied frequency. Is provided with a circuit for compressing so that the signal frequency becomes equal to the externally applied signal frequency, and internal diagnosis is possible at a rate of multiplication of the externally applied signal frequency.

Further, in the circuit for multiplying the frequency of the signal applied from the outside, 1-bit data to be written in the internal semiconductor memory device to be diagnosed is generated as alternating columns of 1 and 0, and the head data of the column is generated. Correspond to an externally applied input signal.

In the circuit for time-compressing the output result, the read data from the internal semiconductor memory device to be diagnosed is an alternating sequence of 1s and 0s and has an expected value applied from the outside. If the leading data of the read signal sequence corresponds, a signal indicating normal operation is output.

[0008]

According to the present invention, it is possible to suppress an increase in test cost even if the scale-up and speed-up of the LSI are further advanced.

[0009]

EXAMPLES Next, examples of the present invention will be described with reference to FIG. FIG. 1 is a circuit configuration diagram when testing an LSI having a static memory (SRAM) as an internal circuit. FIG. 2 shows an operation timing chart. The external clock (CLK) and the address input data input are given at the frequency (f). The clock is multiplied (4 times in this embodiment) by a phase locked loop circuit (PLL) circuit inside the LSI. In addition, a part of the address (in this embodiment, L
Since the quadruple clock is used inside the SI, the lower 2 bits are internal address automatic incrementer (AGU)
Is incremented by the internal clock frequency.
As shown in FIG. 2, the internal data is 1-0-1-0 when the external data is 1, and 0-1-0- when the external data is 0.
1 and the write data generation circuit DGU are automatically generated at the internal frequency. These input signals are S in the LSI.
It is applied to the RAM macro and the LSI internal circuit is tested by multiplying the external frequency. The output data is an expected value pattern (1 if 1-0-1-0, if 0, 0-1-0- in the output value comparison / compression circuit DC) given from the outside.
1) and the multiplication cycle are sequentially compared, and the output data is 0
It is an alternating sequence of 1 and 1, and it is determined whether the leading data matches the expected value data, and the result is output at the external frequency. In this embodiment, the external clock 1
Since the memory operation can be performed four times by the internal clock that is quadrupled during the cycle, the test time can be reduced to 1 /
It can be 4. Also, the input / output circuit of the LSI is
Since it is sufficient to operate with an external clock, it is possible to diagnose an internal circuit that can operate at a higher speed than the external clock frequency through a low-speed input / output circuit. Furthermore, a high speed LSI can be diagnosed even with a low speed tester. For example, even with an inexpensive tester operating at about 50 MHz,
It is possible to diagnose a high-speed LSI operating at 200 MHz.

By combining the present invention with a conventional multi-bit parallel test method for simultaneously activating a plurality of memory cell blocks, reading a plurality of bits at the same time, and detecting a match of the results, LSI test efficiency is further improved. To be done.

[0011]

The effect of the present invention is to improve the test efficiency, shorten the test time, and enable the diagnosis of high-speed LSI even with a low-speed tester by the structure described in the claims, and the shipping cost of the LSI. The goal is to achieve the reduction of

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a timing diagram showing the operation of the circuit of FIG.

FIG. 3 is a configuration diagram showing a conventional example.

FIG. 4 is a timing chart showing an operation of a conventional example.

FIG. 5 is a configuration diagram showing evaluation of an LSI by a conventional LSI tester.

[Explanation of symbols]

PLL (x4) Quadruple cycle clock generation phase locked loop circuit AGU 2-bit address automatic increment circuit DGU write data generation circuit DC 4 cycle data compression comparison circuit AO-An address input signal D data input signal WE write control signal Q data output signal CLK clock signal

Claims (3)

[Claims] 1. A circuit for internally multiplying a frequency of a signal applied from the outside for diagnosing its function, and an output result corresponding to an input signal of the multiplied frequency becomes equal to the signal frequency of the external application. As described above, a semiconductor memory device having a compression circuit and capable of performing internal diagnosis at a rate of multiplication of an externally applied signal frequency. 2. In the circuit for multiplying the frequency of a signal applied from the outside, 1-bit data to be written in an internal semiconductor memory device to be diagnosed is generated as alternating columns of 1 and 0, and the head of the column is generated. 2. The semiconductor memory device according to claim 1, wherein the data is made to correspond to an externally applied input signal. 3. In the circuit for time-compressing the output result, the read data from the internal semiconductor memory device to be diagnosed is an alternating sequence of 1 and 0 and has an expected value applied from the outside. 2. The semiconductor memory device according to claim 1, wherein a signal indicating normal operation is output if the leading data of the read-out signal sequence corresponds.