JPH0431974A - Defect inspecting device for rectangular member - Google Patents

Defect inspecting device for rectangular member

Info

Publication number
JPH0431974A
JPH0431974A JP2139236A JP13923690A JPH0431974A JP H0431974 A JPH0431974 A JP H0431974A JP 2139236 A JP2139236 A JP 2139236A JP 13923690 A JP13923690 A JP 13923690A JP H0431974 A JPH0431974 A JP H0431974A
Authority
JP
Japan
Prior art keywords
image
area
inspected
binary image
chip resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2139236A
Other languages
Japanese (ja)
Inventor
Masatomo Haraguchi
原口 正友
Seiji Furukawa
古川 征次
Kiyoshi Miyamoto
宮本 潔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Corp
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Corp, Omron Tateisi Electronics Co filed Critical Omron Corp
Priority to JP2139236A priority Critical patent/JPH0431974A/en
Publication of JPH0431974A publication Critical patent/JPH0431974A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

PURPOSE:To perform inspection with high efficiency and accuracy by discriminating the normal/defective condition of a member to be inspected by comparing an area obtained by setting a pair of line areas intersecting orthogonally to each other with the area obtained by setting a plane area for a binary image obtained by image-picking up the member to be inspected. CONSTITUTION:A chip resistor 12 introduced to an inspection position is image- picked up by an image pickup device 11, and an input image is binarized, and is stored in image memory 23. A CPU 25, after measuring the number (l, w) of black picture elements of a binary image located at first and second line windows 32, 33, performs an arithmetic operation of S' = l X w, and finds the area S' of a body part 29. The CPU 25 measures the number S of black picture elements of the binary image included in a rectangular window 34. The CPU 25 discriminates the coincidence/noncoincidence of the measured values S' and S. Both measured values S' and S show noncoincidence when a defective part such as a pin hole 36, etc., exists in the chip resistor 12.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 この発明は、チップ抵抗やチップコンデンサなどの小型
で矩形状をなす電子部品を検査するのに用いられる検査
装置に関連し、殊にこの発明は、その種形状の部品の欠
け、ピンホール。
[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to an inspection device used for inspecting small, rectangular electronic components such as chip resistors and chip capacitors. This is the type of chipped or pinhole shaped part.

クラッタなどの不良を検査するのに好適な矩形部材の不
良検査装置に関する。
The present invention relates to a rectangular member defect inspection device suitable for inspecting defects such as clutter.

〈従来の技術〉 たとえばチップ抵抗1は、第7図に示すような矩形平板
状の外観を有しており、本体部2の両端に電極部3.4
を備えている。このようなチップ抵抗1の品質を外観よ
り判断する場合、全体形状はおよそ矩形平板状であれば
よく、縦方向および横方向の寸法に多少の許容範囲を有
している。ところが本体部5に、第7図に示すようなピ
ンホール5が存在していたり、周縁部が欠けていたりす
ると、これを不良品として厳密に抽出する必要がある。
<Prior art> For example, a chip resistor 1 has a rectangular flat plate-like appearance as shown in FIG.
It is equipped with When judging the quality of such a chip resistor 1 from its appearance, it is sufficient that the overall shape is approximately rectangular and flat, with some tolerance in the vertical and horizontal dimensions. However, if the main body part 5 has a pinhole 5 as shown in FIG. 7 or if the peripheral edge is missing, it is necessary to precisely extract this as a defective product.

〈発明が解決しようとする問題点〉 従来ではこのような小型でかつ矩形状の電子部品などの
検査は、人手によって行われているため、検査に熟練を
要し、また検査の作業効率が低く、検査結果が検査員に
よってばらつくなどの問題がある。
<Problems to be Solved by the Invention> Conventionally, inspection of such small and rectangular electronic components has been performed manually, which requires skill and has low inspection work efficiency. , there are problems such as the test results vary depending on the inspector.

この発明は、上記問題を解消するためのものであって、
特に矩形部材の不良について効率が良くかつ高精度の自
動検査を行うことができる矩形部材の不良検査装置を提
供することを目的とする。
This invention is intended to solve the above problem,
In particular, it is an object of the present invention to provide a defect inspection device for rectangular members that can perform efficient and highly accurate automatic inspection of defects in rectangular members.

〈問題点を解決するための手段〉 この発明は、撮像部と画像処理部とを有する矩形部材の
不良検査装置であって、撮像部は被検査部材の真上に位
置して被検査部材の全体を撮像する。
<Means for Solving the Problems> The present invention is a defect inspection device for a rectangular member that has an imaging section and an image processing section, and the imaging section is located directly above the member to be inspected. Capture the entire image.

画像処理部は2値化手段と第1.第2の領域設定手段と
第1.第2の面積計測手段と、不良判別手段とを有する
。2値化手段は撮像部で得た入力画像を2値化して2値
画像を生成する。
The image processing section includes a binarization means and a first . The second area setting means and the first area setting means. It has a second area measuring means and a defect determining means. The binarization means binarizes the input image obtained by the imaging unit to generate a binary image.

第1の領域設定手段は2値画像に対し互いに直交する一
対の線領域を設定する。第2の領域設定手段は2値画像
に対し画像全体を含む面領域を設定する。第1の面積計
測手段は各線領域上に位置する被検査部材の構成画素数
を求めて、各画素数の積から被検査部材の画像部分の面
積を計測し、第2の面積計測手段は面領域に含まれる被
検査部材の構成画素数を被検査部材の画像部分の面積と
して計測する。不良判定手段は第1.第2の各面積計測
手段による計測結果を比較して被検査部材の良否を判別
する。
The first region setting means sets a pair of mutually orthogonal line regions on the binary image. The second area setting means sets a plane area including the entire image for the binary image. The first area measuring means calculates the number of constituent pixels of the inspected member located on each line area, and measures the area of the image portion of the inspected member from the product of each pixel number. The number of constituent pixels of the inspected member included in the region is measured as the area of the image portion of the inspected member. The defect determination means is the first one. The measurement results obtained by each of the second area measuring means are compared to determine the quality of the inspected member.

〈作用〉 被検査部材が良品であれば、第1.第2の各面積計測手
段による計測値は一致するか、もし不良品であれば、そ
れぞれの計測値は不一致となる。従って再計測値が一致
するが否かにより被検査部材の良否を容易に判定でき、
検査効率の高い高精度の自動検査が可能である。
<Operation> If the inspected member is a good product, the first. The measured values by each of the second area measuring means match, or if the product is defective, the measured values do not match. Therefore, it is possible to easily judge whether the inspected parts are good or bad depending on whether the remeasured values match or not.
Highly accurate automatic inspection with high inspection efficiency is possible.

〈実施例〉 第1図は、この発明の一実施例にががる小型部品の不良
検査装置11の外観を示す。
<Embodiment> FIG. 1 shows the external appearance of a defect inspection apparatus 11 for small parts according to an embodiment of the present invention.

図示例の小型部品は平面形状が矩形状をなすチップ抵抗
12であって、各チップ抵抗12が帯状体15に形成さ
れた個別の収納孔13にそれぞれ収納された形態で検査
に供される。各収納孔13はチップ抵抗12の全体がち
ょうど嵌まる平面矩形状に形成されており、このためチ
ップ抵抗12は収納孔13内においてはその傾きや変位
が規制される。
The illustrated small component is a chip resistor 12 having a rectangular planar shape, and each chip resistor 12 is housed in an individual housing hole 13 formed in a strip 15 for inspection. Each housing hole 13 is formed into a planar rectangular shape into which the entire chip resistor 12 fits, so that the inclination and displacement of the chip resistor 12 within the housing hole 13 is restricted.

帯状体15は図中矢印16の方向に搬送されており、チ
ップ抵抗12が検査位置に到達すると、搬送動作が停止
して検査が実施される。なお帯状体15には複数の位置
決め用孔14が等間隔かつ一列に設けてあり、その位置
用決め孔14を利用して停止位置の制御が可能である。
The strip 15 is being conveyed in the direction of the arrow 16 in the figure, and when the chip resistor 12 reaches the inspection position, the conveyance operation is stopped and the inspection is performed. A plurality of positioning holes 14 are provided in the band-shaped body 15 in a line at equal intervals, and the stop position can be controlled using the positioning holes 14.

検査位置にはその真上に撮像装置19が、また両側に照
明装置17.18が、それぞれ配置してあり、各照明装
置L7,1Bより検査すべきチップ抵抗12に対しほぼ
水平方向から光が照射される。このような照明によるチ
ップ抵抗12の光学像は撮像装置19により撮像され、
その画像信号は画像処理装置20に取り込まれて2値化
などの所定の処理が実施され、またその2値画像が表示
装置21に表示される。
An imaging device 19 is placed directly above the inspection position, and illumination devices 17 and 18 are placed on both sides of the inspection position, and each illumination device L7, 1B illuminates the chip resistor 12 to be inspected from a substantially horizontal direction. irradiated. An optical image of the chip resistor 12 due to such illumination is captured by an imaging device 19,
The image signal is taken into the image processing device 20 and subjected to predetermined processing such as binarization, and the binary image is displayed on the display device 21.

第2図は、画像処理装置20の概略構成を示している。FIG. 2 shows a schematic configuration of the image processing device 20. As shown in FIG.

同図において、撮像装置、19からのアナログ量の画像
信号は画像処理装置20に入力されて2値化回路22で
2値化され、画像メモリ23に記憶される。この2値画
像はCRTインタフェース回路24を介してCRTなど
の表示装置21に表示される。このような動作を制御す
るCPU25がパスライン26を介して画像メモリ23
に接続されており、前記パスライン26には、部品検査
のためのプログラムなどが格納されるROM27や、各
種データなどが格納されるRAM28が接続される。
In the figure, an analog image signal from an imaging device 19 is input to an image processing device 20, binarized by a binarization circuit 22, and stored in an image memory 23. This binary image is displayed on a display device 21 such as a CRT via a CRT interface circuit 24. The CPU 25 that controls such operations is connected to the image memory 23 via the pass line 26.
The path line 26 is connected to a ROM 27 in which programs for inspecting components are stored, and a RAM 28 in which various data are stored.

第3図は、画像メモリ23に格納された2値画像31を
示している。
FIG. 3 shows a binary image 31 stored in the image memory 23.

この2値画像31は、黒画素より成る物体部分29と白
画素より成る背景部分30とを含むもので、この2値画
像31に対し相互に直交しかつ線状をなす第1.第2の
ラインウィンドウ32.33 (第3図(1)に示す)
と、物体部分29を含む範囲の矩形ウィンドウ34(第
3図(2)に示す)とが設定されて、後記する部品検査
が実行される。この実施例では、前記ラインウィンドウ
32.33はその線幅を1画素に設定する。
This binary image 31 includes an object portion 29 made of black pixels and a background portion 30 made of white pixels. Second line window 32.33 (shown in Figure 3 (1))
and a rectangular window 34 (shown in FIG. 3(2)) including the object portion 29 are set, and a component inspection to be described later is executed. In this embodiment, the line windows 32, 33 have their line width set to one pixel.

第4図は、この実施例による検査手順を示している。ま
ず同図のステップ1(図中rsT I Jで示す)にお
いて、検査位置に導かれたチップ抵抗12が撮像装置1
1で撮像され、つぎのステップ2でその入力画像が2値
化されて画像メモリ23に格納される。つぎにステップ
3では、CPU25はこの2値画像に対し、まず第1の
ラインウィンドウ32を設定してそのラインウィンドウ
32上に位置する黒画素の数、すなわち物体部分29の
縦方向の長さlを計測する。
FIG. 4 shows the testing procedure according to this embodiment. First, in step 1 in the figure (indicated by rsT I J in the figure), the chip resistor 12 guided to the inspection position is connected to the imaging device 1.
1, and in the next step 2, the input image is binarized and stored in the image memory 23. Next, in step 3, the CPU 25 first sets a first line window 32 for this binary image and determines the number of black pixels located on the line window 32, that is, the length l in the vertical direction of the object portion 29. Measure.

つぎにCPU25は、ステップ4で第2のラインウィン
ドウ33を設定して、同様に物体部分29の横方向の長
さWを計測した後、ステップ5でつぎの0式の演算を行
って物体部分29の面積S′を求める。
Next, the CPU 25 sets the second line window 33 in step 4 and similarly measures the lateral length W of the object portion 29, and then calculates the following equation 0 in step 5 to determine the object portion 29. Find the area S' of 29.

S’ =ffiXw  ・・・・■ ついでステップ6では、CPU25は前記2値画像に対
し矩形ウィンドウ34を設定して、そのウィンドウ34
内に含まれる黒画素の数、すなわち直像の物体部分29
の面積Sを計測する。
S' = ffiXw...■ Next, in step 6, the CPU 25 sets a rectangular window 34 for the binary image, and displays the window 34.
The number of black pixels contained in the object part 29 of the direct image
Measure the area S.

かくしてCPU25は、ステップ7において、ステップ
5の計測値S′とステップ6の計測値Sとが一致するか
否かを判定する。この両針測値s’、sは、チップ抵抗
12の2値画像に第5図(2)〜(6)に示すようなピ
ンホール361周縁部の欠け37.クラック38などの
不良箇所が存在する場合には不一致となり、また第5図
(1)に示すような不良箇所が存在しない場合には一致
する。
Thus, in step 7, the CPU 25 determines whether the measured value S' of step 5 and the measured value S of step 6 match. These two-point measurement values s', s are based on the chip resistor 12 in the binary image of the chip resistor 12 as shown in FIGS. 5(2) to 5(6). If a defective location such as a crack 38 exists, there is no match, and if there is no defective location as shown in FIG. 5(1), there is a match.

その結果、ステップ7が“YES”であれば良品と判断
され、ステップ8でその旨の判定が出力される。またス
テップ7がパNO”であれば、前述したいずれか不良箇
所が存する不良品であると判断され、ステップ9でその
旨の不良判定が出力される。
As a result, if step 7 is "YES", it is determined that the product is non-defective, and a determination to that effect is outputted in step 8. Further, if the result in step 7 is ``NO'', it is determined that the product is defective because it has any of the defective parts described above, and a defect determination to that effect is output in step 9.

このように従来は人手で行っていたチップ抵抗12など
の小型矩形状部品の良否検査を、画像処理を行う装置に
よって自動的に行うようにしたので、検査の効率や精度
における従来技術の問題点が解消される。またラインウ
ィンドウ32.33を用いて求めた面積S′と、矩形ウ
ィンドウ34を用いて求めた面積Sとを比較することに
より良否判定を行うので、チップ抵抗12の縦横各方向
の長さに誤差があってもその誤差に起因して不良品と判
断されるおそれはない さらに画像の物体部分29がラインウィンドウ32に対
して、第6図に示すように角度θだけ傾いていても、そ
の角度θがゼロに近ければ、前記ステップ5で計測され
る面積S′はその誤差を無視し得、前述の処理が成立す
る。
In this way, the quality inspection of small rectangular components such as the chip resistor 12, which was conventionally done manually, is now automatically done using an image processing device, which solves the problems of the conventional technology in terms of inspection efficiency and accuracy. is resolved. In addition, since the pass/fail judgment is made by comparing the area S' obtained using the line windows 32 and 33 with the area S obtained using the rectangular window 34, there is an error in the length of the chip resistor 12 in the vertical and horizontal directions. Even if the object part 29 of the image is tilted by an angle θ with respect to the line window 32 as shown in FIG. If θ is close to zero, the error in the area S' measured in step 5 can be ignored, and the above-described process is established.

なお第4図のステップ7では、面積S′sを比較してそ
の一致、不一致により部品の良否判定を行っているが、
これに限らず、次式の算出値Cが所定の基準値以下であ
れば良判定を、基準値より大きければ不良判定を、それ
ぞれ行うようにしてもよい。
In step 7 of FIG. 4, the areas S's are compared and the quality of the parts is judged based on whether they match or do not match.
However, the present invention is not limited to this, and if the calculated value C of the following equation is less than or equal to a predetermined reference value, a good judgment may be made, and if it is greater than the reference value, a bad judgment may be made.

また上記の実施例は、チップ抵抗12の良否を検査する
ものであるが、平面形状が矩形状のものであれは、その
他の電子部品の検査や電子部品以外の物の検査にも適用
できる。
Further, although the above embodiment is for testing the quality of the chip resistor 12, it can also be applied to testing other electronic components or items other than electronic components as long as the planar shape is rectangular.

〈発明の効果〉 この発明は上記の如く、被検査部材を撮像して得た2値
画像に対し、互いに直交する一対の線領域を設定して求
めた画像の面積と、面領域を設定して求めた画像の面積
とを比較して被検査部材の良否を判別するようにしたか
ら、矩形部材のピンホール、周縁部の欠けやクランクな
どの不良検査を人手によらない自動化された検査作業で
実現でき、効率の良い高精度の検査を行うことができる
<Effects of the Invention> As described above, the present invention sets the area and surface area of the image obtained by setting a pair of mutually orthogonal line areas on a binary image obtained by imaging a member to be inspected. Since the quality of the inspected part is determined by comparing the area of the image obtained by This enables efficient and highly accurate inspection.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例にかかる不良検査装置の外
観を示す斜面図、第2図は画像処理装置の電気的構成を
示すブロック図、第3図は2値画像とその画像上に設定
されるウィンドウを示す説明図、第4図はこの実施例の
動作手順を示すフローチャート、第5図は良品および不
良品の2値画像を示す説明図、第6図は画像が傾いた場
合を示す説明図、第7図はチップ抵抗の形状を示す斜面
図である。 11・・・・検査装置    12・・・・チップ抵抗
19・・・・撮像装置    20・・・・画像処理装
置22・・・・2値化回路   23・・・・画像メモ
リ25・・・・CPU
FIG. 1 is a perspective view showing the external appearance of a defect inspection device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the electrical configuration of the image processing device, and FIG. 3 is a binary image and FIG. 4 is a flowchart showing the operating procedure of this embodiment. FIG. 5 is an explanatory diagram showing binary images of non-defective and defective products. FIG. 6 is a diagram showing the case where the image is tilted. The explanatory diagram shown in FIG. 7 is an oblique view showing the shape of the chip resistor. 11...Inspection device 12...Chip resistor 19...Imaging device 20...Image processing device 22...Binarization circuit 23...Image memory 25... CPU

Claims (1)

【特許請求の範囲】 撮像部と画像処理装置とを有する矩形部材の不良検査装
置であって、 撮像部は、被検査部材の真上に位置して被検査部材の全
体を撮像し、 画像処理部は、2値化手段と、第1,第2の領域設定手
段と、第1,第2の面積計測手段と、不良判別手段とを
有し、 2値化手段は、撮像部で得た入力画像を2値化して2値
画像を生成し、 第1の領域設定手段は、2値画像に対し互いに直交する
一対の線領域を設定し、 第2の領域設定手段は、2値画像に対し画像全体を含む
面領域を設定し、 第1の面積計測手段は、各線領域上に位置する被検査部
材の構成画素数を求めて、各画素数の積から被検査部材
の画像部分の面積を計測し、第2の面積計測手段は、面
領域に含まれる被検査部材の構成画素数を被検査部材の
画像部分の面積として計測し、 不良判定手段は、第1,第2の各面積計測手段による計
測結果を比較して被検査部材の良否を判別する矩形部材
の不良検査装置。
[Scope of Claims] A rectangular member defect inspection device having an imaging section and an image processing device, the imaging section being located directly above the inspected member and capturing an image of the entire inspected member, and performing image processing. The section includes a binarization means, first and second area setting means, first and second area measurement means, and a defect determination means, and the binarization means includes a binarization means that detects the area obtained by the imaging section. The input image is binarized to generate a binary image, the first region setting means sets a pair of mutually orthogonal line regions on the binary image, and the second region setting means sets a pair of line regions perpendicular to each other on the binary image. On the other hand, a surface area including the entire image is set, and the first area measuring means calculates the number of constituent pixels of the inspected member located on each line area, and calculates the area of the image portion of the inspected member from the product of each pixel number. The second area measuring means measures the number of constituent pixels of the inspected member included in the surface area as the area of the image portion of the inspected member, and the defect determination means measures each of the first and second areas. A defect inspection device for a rectangular member that compares measurement results by a measuring means to determine the quality of the inspected member.
JP2139236A 1990-05-29 1990-05-29 Defect inspecting device for rectangular member Pending JPH0431974A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2139236A JPH0431974A (en) 1990-05-29 1990-05-29 Defect inspecting device for rectangular member

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2139236A JPH0431974A (en) 1990-05-29 1990-05-29 Defect inspecting device for rectangular member

Publications (1)

Publication Number Publication Date
JPH0431974A true JPH0431974A (en) 1992-02-04

Family

ID=15240646

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2139236A Pending JPH0431974A (en) 1990-05-29 1990-05-29 Defect inspecting device for rectangular member

Country Status (1)

Country Link
JP (1) JPH0431974A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06229942A (en) * 1993-02-03 1994-08-19 Nippondenso Co Ltd Inspection apparatus for pinhole
JP2004055599A (en) * 2002-07-16 2004-02-19 Nagoya Electric Works Co Ltd Method and apparatus for inspecting mounting board
JP2010175558A (en) * 2010-04-01 2010-08-12 Daiichi Jitsugyo Viswill Co Ltd Inspection device
CN106706650A (en) * 2015-08-20 2017-05-24 昆山市和博电子科技有限公司 Chip resistor detection process device
CN107037057A (en) * 2015-08-20 2017-08-11 昆山市和博电子科技有限公司 Chip-R detection means
CN111693778A (en) * 2020-05-25 2020-09-22 珠海格力电器股份有限公司 Patch resistor abnormality detection method, device, system, equipment and storage medium

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06229942A (en) * 1993-02-03 1994-08-19 Nippondenso Co Ltd Inspection apparatus for pinhole
JP2004055599A (en) * 2002-07-16 2004-02-19 Nagoya Electric Works Co Ltd Method and apparatus for inspecting mounting board
JP2010175558A (en) * 2010-04-01 2010-08-12 Daiichi Jitsugyo Viswill Co Ltd Inspection device
CN106706650A (en) * 2015-08-20 2017-05-24 昆山市和博电子科技有限公司 Chip resistor detection process device
CN107037057A (en) * 2015-08-20 2017-08-11 昆山市和博电子科技有限公司 Chip-R detection means
CN111693778A (en) * 2020-05-25 2020-09-22 珠海格力电器股份有限公司 Patch resistor abnormality detection method, device, system, equipment and storage medium
CN111693778B (en) * 2020-05-25 2021-07-20 珠海格力电器股份有限公司 Patch resistor abnormality detection method, device, system, equipment and storage medium

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