JPH04318716A - Destuff control circuit - Google Patents

Abstract

PURPOSE:To configurate the control circuit with low speed devices and to reduce power consumption by applying serial parallel conversion to an input signal so as to decrease the operating speed, generating a destuff pulse in the lock system at a slow operating speed and restoring the speed to the speed of the input signal. CONSTITUTION:A serial parallel conversion circuit 2 expands an input signal 1 whose word consists of n-bits being an asynchronizing signal in the unit of words in parallel by n-sets to decrease the signal speed to 1/n. A stuff decision circuit 3 decides the presence of destuff of the received signal from the circuit 2 based on the majority decision of bits in the stuff control in the clock system of a fundamental frequency or the like, and a pulse generating circuit 4 is controlled by the circuit 3 to generate a pulse with 1 word width when the destuff is in existence. A speed conversion circuit 5 restores the output with frequency system clock accuracy of the original signal 1, a differentiating circuit 6 differentiates and shapes the output to output a destuff pulse 7 of one bit width. Thus, even when the data transmission speed is fast and the circuits 3, 4 make complicated processing, the circuits are made up of low speed devices.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a data transmission device.
In particular, it relates to destuffing control circuits in high-speed asynchronous data transmission.

0002

2. Description of the Related Art A conventional destuff control circuit, as shown in the block diagram of FIG.
It has a destuff determination circuit 8 which inputs the destuff determination circuit 8, and a pulse generation circuit 9 which receives the output of the destuff determination circuit 8 as input.

Next, the operation of this destuff control circuit will be explained using a timing chart shown in FIG. FIG. 3(a) is an example of input signal 1, which includes stuff control bit C and stuff bit S at specific positions. Normally, an information bit is placed in the position of the stuff bit S, but when stuffing is present, it becomes an empty bit. The presence or absence of stuffing is determined by stuffing control bit C,
For example, it is determined by majority decision of CCC=111.

The destuff determination circuit determines whether the input signal 1 is stuffed or not, and controls the pulse generation circuit 9. The pulse generation circuit 9 operates as shown in FIG. 3(b) when there is stuffing.
) is generated, and this destuff pulse 7 prevents the empty stuff bit S from being written into the stuff memory as data.

[0005]

[Problems to be Solved by the Invention] This conventional destuffing control circuit processes input signals at the same speed, so the data transmission speed is fast and the destuffing judgment circuit and pulse generation circuit are suitable for performing complex processing. had the problem of increased power consumption.

[0006]

[Means for Solving the Problems] The destuffing control circuit of the present invention includes a serial-to-parallel conversion circuit that expands asynchronous data signals in parallel word by word, and a destuffing determination circuit that destuffs the parallel expanded data signals. a pulse generating circuit that generates a one-word width pulse under the control of the destuffing determination circuit when it is determined by the destuffing determination that destuffing is to be performed; The speed conversion circuit converts the pulse outputted from the speed conversion circuit into a destuff pulse having a 1-bit width of the data signal.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 4(a) to (e)
) is a timing chart showing the operation of the embodiment of FIG.

In FIG. 1, a serial-parallel conversion circuit 2 expands an input signal 1, which is an asynchronous data signal as shown in FIG. 4(a), in which one word consists of n bits, in n parallel words. The signal speed of input signal 1 is reduced to 1/n (see FIG. 4(b)). The stuff determination circuit 3 uses a fundamental frequency clock system in which the signal speed of the input signal 1 is reduced to 1/n, and determines whether or not the signal input from the serial-to-parallel converter circuit 2 is destuffed by majority decision of the stuff control bit C. judge. The pulse generating circuit 4 is under the control of the destuffing determination circuit 3, and when destuffing is present, it generates a pulse of one word width as shown in FIG. 4(c). The speed conversion circuit 5 returns the output of the pulse generation circuit 4 to the clock precision of the original frequency system of the input signal 1 (see FIG. 4(d)). The differentiating circuit 6 differentiates and shapes the output of the speed converting circuit 5, and outputs a 1-bit width destuff pulse 7 shown in FIG. 3(e). The destuff pulse 7 is generated by the above operations.

[0009]

As explained above, the present invention reduces the operating speed to 1/n by converting input signals into series and parallel, and performs destuffing judgment and one-word width destuffing pulse using a slow operating speed clock system. We decided to generate a 1-bit width destuff pulse by converting the speed of this signal, returning it to a clock-accurate signal that corresponds to the speed of the original input signal, and then differentiating it to generate a 1-bit width destuff pulse. When the destuff determination circuit and the pulse generation circuit perform complex processing, these circuits can be configured with low-speed devices, and power consumption can be reduced.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional example.

FIG. 3 is a timing chart illustrating the operation of a conventional example.

FIG. 4 is a timing chart illustrating the operation of the embodiment in FIG. 1;

[Explanation of symbols]

1 Input signal 2 Serial-to-parallel conversion circuit 3 Destuffing judgment circuit 4 Pulse generation circuit 5 Speed conversion circuit 6 Differential circuit 7 Destuff pulse 8 Destuffing judgment circuit 9 Pulse generation circuit

Claims (1)

[Claims] 1. A serial-to-parallel conversion circuit that parallelizes an asynchronous data signal word by word, and a destuff determination circuit that destuffs the parallel expanded data signal.
a pulse generating circuit that generates a one-word width pulse under the control of the destuffing determination circuit when it is determined that destuffing is to be performed by the destuffing determination; A destuff control circuit comprising: a speed conversion circuit that converts the pulses into clock-accurate pulses; and a differentiation circuit that converts the pulses output from the speed conversion circuit into destuff pulses with a 1-bit width of the data signal.