JP2606575B2 - Variable speed conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission speed conversion circuit for digital communication, and more particularly to a variable speed conversion circuit for changing the data speed and bit configuration using one elastic store.

[0002]

2. Description of the Related Art Elastic store (hereinafter "ESM")
FIG. 4 shows an example of a conventional speed conversion circuit using the same.

In FIG. 4, reference numeral 41 denotes a WR / WI signal generator for inputting a clock (CLK) and a frame pulse (FP) from a highway to generate a write reset signal (WR) and a write inhibit signal (WI); RR / RI which inputs a clock (CLK) and a frame pulse (FP) from the highway to generate a read reset signal (RR) and a read inhibit signal (RI)
The signal generation unit 43 receives data (DAT) from the highway.
A), an ESM unit which inputs CLK, WR signal, WI signal, RR signal, RI signal and read clock (RCLK) and outputs output data (DO).

Data DATA input from the highway
Is the WR / WI created by the WR / WI signal creation unit 41
The data is written to the ESM unit 43 according to the signal timing. The ESM unit 43 converts the written data into RR /
The data written according to the RR / RI timing created by the RI signal creation unit 42 is output as output data DO. At this time, the ESM unit 43 does not write the input data when the WI signal is active, and stops reading the data when the RI signal is active and holds the data value of the previous stage. , RI signals are data obtained by speed-converting the input data.

[0005]

However, in such a conventional transmission speed conversion circuit, the speed and bit configuration of data output after conversion with respect to the speed of input data are always constant. It is not possible to convert to the speed and bit configuration of the above, and to convert to other speeds, it is necessary to provide a separate circuit, so that the circuit scale becomes large.

Accordingly, the variable speed conversion circuit of the present invention has
It is an object of the present invention to provide a variable speed conversion circuit capable of performing a plurality of types of speed conversion using one ESM.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a variable speed conversion circuit according to the present invention uses a write / read clock signal and a write instruction for writing from a frame pulse and a clock signal of a transmission line. A timing circuit for generating a reset signal, a read reset signal for instructing reading, and a write inhibit signal for stopping writing and a read inhibit signal for stopping reading from a frame pulse and a clock signal of a transmission line; Inhibit signal generating means; and select signal generating means for generating a select signal for instructing the inhibit signal generating means on the output type of the inhibit signal in accordance with an instruction from the processor. Inhibit signal and lead inhibition Characterized in that changing the type of bets signals.

As a result, the type of the inhibit signal to be inputted changes, so that even if there is one ESM,
The output data signal speed can be made variable depending on the type of the input inhibit signal.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A variable speed conversion circuit according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIGS. 2 and 3 are time charts showing the operation thereof.

This embodiment shows a case where input data (DI) having a bit rate x is selected from eight types of output data DO1 to DO8 and converted according to an order from a processor.

In FIG. 1, reference numeral 11 denotes a select signal generating unit for generating select signals (SEL1 to SEL3) for selecting a speed and a bit configuration of output data in response to a control command from a μP bus 15 from a microprocessor (not shown). ,
12 is a write / read clock (W / RCLK) from the input clock (CLK) and frame pulse (FP),
A timing circuit for generating a write reset signal (WR) and a read reset signal (RR) and adjusting the timing for inputting the signal to the ESM unit 14;
P, an inhibit signal generation unit for generating a write inhibit signal (WI) and a read inhibit (RI) signal from the SEL1 to SEL3 signals; An ESM unit that converts and outputs output data (DO).

The inhibit signal generator 13 generates the inhibit signals INH1 to INH12 shown in FIG. A combination of the WI signal and the RI signal is selected from these INH signals and output according to the select signals SEL1 to SEL3 output from the select signal creation unit 11.

In the ESM unit 14, the writing of the input data DI and the reading of the output data DO are controlled by the WI signal and the RI signal to perform speed conversion and bit configuration conversion.

FIG. 3 shows a combination of the WI signal and the RI signal and the output data DO at that time.

DO1 to DO8 are as follows.

DO1 is IN for both the WI signal and the RI signal.
This is an output when the H1 signal is used, and is composed of only even-numbered bits, and has a bit rate of x / 2.

DO2 outputs the INH2 signal to the WI signal and R
This is an output when the INH1 signal is used as the I signal. One block is composed of 2 bits and is composed of even blocks, and the bit rate is x / 2.

DO3 outputs INH3 signal to WI signal and R
This is an output when the INH1 signal is used as the I signal. One block consists of 4 bits and is composed of even blocks, and the bit rate is x / 2.

DO4 outputs the INH4 signal as the WI signal,
This is an output when the INH1 signal is used as the I signal. One block is composed of 8 bits and is composed of even-numbered blocks. The bit rate is x / 2.

DO5 outputs the INH5 signal as the WI signal,
This is an output when the INH9 signal is used as the I signal, and is 2n
.., And the bit rate is x / 2.

DO6 outputs the INH6 signal as the WI signal,
This is an output when the INH10 signal is used as the I signal.
It is composed of n bits (0, 4, 8,...), and the bit rate is x / 4.

DO7 outputs the INH7 signal to the WI signal,
This is an output when the INH11 signal is used as the I signal, and is 8
It is composed of n bits (0, 8, 16,...), and the bit rate is x / 8.

DO8 outputs the INH8 signal as the WI signal,
This is an output when the INH12 signal is used as the I signal.
It is composed of 6n bits (0, 16, 32, ...), and the bit rate is x / 16.

[0025]

As described above, the variable speed conversion circuit according to the present invention has a conversion circuit capable of performing a plurality of speed conversions even with a simple hardware configuration having a small number of components using one ESM. Can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a time chart of an inhibit signal according to the embodiment shown in FIG. 1;

FIG. 3 is a time chart of output data of the embodiment shown in FIG. 1;

FIG. 4 is a block diagram of a conventional example.

[Explanation of symbols]

 Reference Signs List 11 select signal creation unit 12 timing circuit 13 inhibit signal creation unit 14, 43 ESM unit 15 μP bus 41 WR / WI signal creation unit 42 RR / RI signal creation unit

Claims (1)

(57) [Claims] 1. A speed conversion circuit for performing speed conversion of transmission data using an elastic store, comprising: a frame signal and a clock signal of a transmission line, a clock signal for writing / reading, a write reset signal for instructing writing, and reading. Signal generation means for generating a read reset signal for instructing a write, and a write inhibit signal for stopping writing and a read inhibit signal for stopping reading from a frame pulse and a clock signal of a transmission line. And select signal generating means for generating a select signal for instructing the inhibit signal generating means on the output type of the inhibit signal in accordance with an instruction from the processor. Variable speed conversion circuit, characterized in that changing the type of Hibitto signal.