JPH0430481U - - Google Patents
Info
- Publication number
- JPH0430481U JPH0430481U JP7066990U JP7066990U JPH0430481U JP H0430481 U JPH0430481 U JP H0430481U JP 7066990 U JP7066990 U JP 7066990U JP 7066990 U JP7066990 U JP 7066990U JP H0430481 U JPH0430481 U JP H0430481U
- Authority
- JP
- Japan
- Prior art keywords
- sample
- circuit
- storage device
- clock pulse
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001360 synchronised effect Effects 0.000 claims 2
- 230000003068 static effect Effects 0.000 claims 1
- 230000001052 transient effect Effects 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Landscapes
- Measurement Of Current Or Voltage (AREA)
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の一実施例のブロツク図、第２
図は本考案の制御タイムチヤート、第３図はサン
プリング時のタイムチヤート、第４図は従来技術
でのサンプルデータ例の波形図、第５図は従来の
制御タイムチヤートである。
１……増幅器、２……トリガ発生回路、３……
鋸歯状波発生回路、４……コンパレータ、５……
ＤＡ変換回路、６……遅延量制御用デイジタル値
出力回路、７……ＮＡＮＤ回路、８……デイレー
ライン、９……デイレーライン、１０……ＡＤ変
換器、１１……バツフアメモリ、１２……サンプ
ルホールド回路、１３……増幅器、１４……マイ
クロプロセツサ、１５……表示用メモリ、１６…
…ＤＡ変換器、１７……増幅器、１８……ＣＲＴ
、１９……クロツクパルス制御回路、２０……Ｏ
Ｒ回路、Ａ……入力信号、Ｂ……トリガレベル、
Ｃ……トリガパルス、Ｄ……鋸歯状波電圧、Ｅ…
…ＤＡ変換出力電圧、Ｆ……コンパレータ出力、
Ｇ……ＮＡＮＤ回路７出力（クロツクパルス）、
Ｈ……サンプルホールド１２の入力部（入力信号
Ａの遅延した信号）、Ｊ……マイクロプロセツサ
１４のデータパス、Ｋ……クロツクパルス制御回
路１９の出力（Ｆ信号とは別にクロツクパルスＧ
を出力させる）、Ｌ……トリガイネーブル信号、
Ｍ……ＯＲ回路２０出力。
Fig. 1 is a block diagram of an embodiment of the present invention;
3 is a time chart of the present invention, FIG. 3 is a time chart during sampling, FIG. 4 is a waveform diagram of an example of sample data in the prior art, and FIG. 5 is a conventional control time chart. 1...Amplifier, 2...Trigger generation circuit, 3...
Sawtooth wave generation circuit, 4... Comparator, 5...
DA conversion circuit, 6... Digital value output circuit for delay amount control, 7... NAND circuit, 8... Delay line, 9... Delay line, 10... AD converter, 11... Buffer memory, 12... ...Sample and hold circuit, 13...Amplifier, 14...Microprocessor, 15...Display memory, 16...
...DA converter, 17...amplifier, 18...CRT
, 19...clock pulse control circuit, 20...O
R circuit, A...input signal, B...trigger level,
C...Trigger pulse, D...Sawtooth wave voltage, E...
...DA conversion output voltage, F...comparator output,
G...NAND circuit 7 output (clock pulse),
H...Input part of sample hold 12 (delayed signal of input signal A), J...Data path of microprocessor 14, K...Output of clock pulse control circuit 19 (clock pulse G separately from F signal).
), L...Trigger enable signal,
M...OR circuit 20 outputs.
Claims (1)
ら、ある遅延時間後に同期した一定周波数のクロ
ツクパルスを発振出力する回路と該クロツクパル
スにより入力信号をサンプルホールドするサンプ
ルホールド回路と前記遅延時間を制御する手段を
持ち、前記クロツクパルスにより入力信号をサン
プリングし、記憶する記憶回路より成る波形記憶
装置において、前記サンプルホールド回路へのク
ロツクパルスを、前記の系とは別に任意に発振出
力する手段を持つことを特徴とする波形記憶装置
。 ２ 長い静止状態の後にサンプルを開始する前に
疑似的にサンプルクロツクを発生させ、サンプル
ホルダ回路を含むアナログ回路系を過渡状態から
定常状態にすることを特徴とする波形記憶装置。 ３ 所定のサンプルが終了し、メモリへの書込み
を停止させても、サンプルホルダ回路へのクロツ
クを次のサンプルの準備が整うまで、継続させて
発生させておくようにしたことを特徴とする波形
記憶装置。[Claims for Utility Model Registration] 1. A circuit that oscillates and outputs a clock pulse of a constant frequency synchronized after a certain delay time from a trigger pulse synchronized with an analog input signal, a sample hold circuit that samples and holds an input signal using the clock pulse, and the delay. In a waveform storage device comprising a storage circuit which has means for controlling time and samples and stores an input signal using the clock pulse, means for arbitrarily oscillating and outputting the clock pulse to the sample and hold circuit separately from the above system is provided. A waveform storage device characterized by having. 2. A waveform storage device characterized in that a sample clock is generated in a pseudo manner before starting a sample after a long static state, thereby bringing an analog circuit system including a sample holder circuit from a transient state to a steady state. 3. A waveform characterized in that even if a predetermined sample is completed and writing to the memory is stopped, the clock to the sample holder circuit continues to be generated until the next sample is ready. Storage device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990070669U JPH0750715Y2 (en) | 1990-07-04 | 1990-07-04 | Waveform storage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990070669U JPH0750715Y2 (en) | 1990-07-04 | 1990-07-04 | Waveform storage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0430481U true JPH0430481U (en) | 1992-03-11 |
| JPH0750715Y2 JPH0750715Y2 (en) | 1995-11-15 |
Family
ID=31607021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990070669U Expired - Lifetime JPH0750715Y2 (en) | 1990-07-04 | 1990-07-04 | Waveform storage |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0750715Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010187092A (en) * | 2009-02-10 | 2010-08-26 | Dkk Toa Corp | Peak hold circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55130232A (en) * | 1979-03-30 | 1980-10-08 | Yokogawa Hokushin Electric Corp | Ad conversion system for repetitive waveform |
| JPS60128372A (en) * | 1983-12-16 | 1985-07-09 | Hitachi Denshi Ltd | Sample holding circuit |
-
1990
- 1990-07-04 JP JP1990070669U patent/JPH0750715Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55130232A (en) * | 1979-03-30 | 1980-10-08 | Yokogawa Hokushin Electric Corp | Ad conversion system for repetitive waveform |
| JPS60128372A (en) * | 1983-12-16 | 1985-07-09 | Hitachi Denshi Ltd | Sample holding circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010187092A (en) * | 2009-02-10 | 2010-08-26 | Dkk Toa Corp | Peak hold circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0750715Y2 (en) | 1995-11-15 |
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