JPH0430229B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A clamp circuit used in a video camera or the like is generally configured as shown in FIG. 1. For example, when a luminance signal Sy as shown in FIG. Clamp pulse as shown in Figure B
When Pc is supplied, a luminance signal Sy whose black level is clamped to voltage Vc is taken out to the emitter of transistor Qa.

However, when using a clamp circuit as an IC,
Since the capacitor Ca is externally connected, the number of external pins of the IC increases. Furthermore, the output impedance of the voltage source Vc must be sufficiently low, and a capacitor or the like is required for this purpose, so the voltage source Vc must also be externally connected, increasing the number of external pins of the IC.

Furthermore, when sending the signal Sy from the previous stage to the latter stage,
It requires a large amount of current to flow, which poses a problem in terms of power consumption.

This invention attempts to eliminate these problems.

Let's explain one example below.

In FIG. 3, the emitters of transistors Q ₁ to _{Q 3} are connected to transistors Q ₂₁ to _{Q 23} for constant current sources, so that transistors Q ₁ to _{Q 3} function as emitter followers, and are connected to an input terminal T for a luminance signal Sy. ₁
is connected to the base of transistor Q ₁ , its emitter is connected to the base of transistor Q ₂ through resistor R 1, and its emitter is connected to the base of transistor Q ₂ .
Connected to the base of Q ₃ .

Further, the terminal _T1 is connected to the base of the transistor _Q11 , and its emitter is connected to the constant current source transistor _Q31 , so that the transistor _Q11
is considered to be Emitsuta Folowa. Also, the emitter of transistor Q ₁₁ is connected to the base of transistor Q ₁₂ through resistor R ₁₁ , and transistor Q ₁₂
The emitter of transistor Q ₃₂ for constant current source is connected between the collector and emitter of transistor Q ₁₅ .
_The collector and emitter of the transistor Q16 are connected between the base of the transistor _Q12 and the collector of the transistor _Q32 . Therefore, when transistor Q ₁₆ is off and transistor Q ₁₅ is on, transistor Q ₁₂ acts as an emitter follower.

Also, the emitter of transistor _Q12 is connected to the base of transistor _Q13 , and this transistor
The emitter of Q ₁₃ is a constant current source transistor Q ₂₃
The transistor _Q13 is connected to the emitter follower, and the base of the transistor _Q13 is connected to the capacitor _C1 through the terminal _T4 .

Further, the emitters of transistors Q ₄ and Q ₁₄ are connected to a constant current source transistor Q ₂₄ , and resistors R ₂ and R ₃ are connected to the collectors of transistors Q ₄ and Q ₁₄ to form a differential amplifier A _1. At the same time, the base of transistor Q ₄ is connected to the emitter of transistor Q ₃ , the base of transistor Q ₁₄ is connected to the emitter of transistor Q ₁₃ , and the collectors of transistors Q ₄ and Q ₁₄ are connected to output terminals T ₂ and T _3. is connected.

Further, a current mirror circuit A ₂ is configured by transistors Q ₂₁ -Q ₂₄ , Q ₃₁ -Q ₃₃ and transistors Q ₂₅ , Q ₂₆ , and transistors Q ₂₁ -Q ₂₄ , Q ₃₁ -
A predetermined collector current is applied to _Q33 .

Note that the corresponding elements have the same characteristics, and _Q1 to _Q4 = _Q11 to _{Q14 Q21} to _Q23 = _Q31 to _{Q33 R1} = _R11 and _R2 = _R3 .

Additionally, an inverter _A3 is configured. This inverter _A3 converts the clamp pulse Pc from TTL level to ECL level (amplitude is 0.7V),
This is for forming pulses of opposite phase.

That is, the input terminal _T11 of the clamp pulse Pc is connected to the base of the transistor _Q42 through the transistor _Q41 , and the transistors _Q42 ,
The emitter of Q ₄₃ is a constant current source transistor Q ₄₄
is connected to configure differential amplifier _A4 . Furthermore, the collector of transistor Q ₄₂ is
It is connected to the base of Q ₅₁ , and its emitter is connected to constant current source transistor Q ₅₄ through level shift transistors Q ₅₂ and Q ₅₃ , making transistor _{Q 51 an} emitter follower. Connected to the base of transistor _Q16 . In addition, the collector of transistor Q ₄₃ is connected to the base of transistor Q ₅₅ , and its emitter is connected to constant current source transistor Q ₅₈ through level shift transistors Q ₅₆ and Q ₅₇ , so that transistor Q ₅₅ functions as an emitter follower. The emitter of transistor _Q57 is connected to the base of transistor _Q15 .

Furthermore, a current mirror circuit A ₅ is formed by transistors Q ₄₄ , Q ₅₄ , Q ₅₈ and transistors Q ₄₅ , Q ₄₆ .
is configured.

According to such a configuration, when the clamp pulse Pc of the terminal _T11 is at the "0" level (the brightness signal
when Sy is not at black level), transistor Q ₄₁
is on, transistor Q ₄₂ is turned off, transistor Q ₅₁ is turned on, and transistor
Q ₅₃ 's emitsuta is at the "1" level. Furthermore, when the pulse Pc is at the "1" level (when the signal Sy is at the black level), the transistor _Q41 is turned off, so the transistor _Q42 is turned on, and the emitter of the transistor _Q53 is at the "0" level. Become. Therefore, the emitter of the transistor _Q53 receives a pulse having a phase opposite to that of the pulse Pc, as shown in FIG. 2C.

Also, transistor Q ₄₃ is transistor Q ₄₂
Since the transistor _Q55 is turned on and off in the opposite phase to the pulse, and the output drives the transistor Q55, a pulse having the opposite phase to the pulse, that is, the pulse Pc, is obtained at the emitter of the transistor _Q57 (actually, the transistor (Q ₄₁ to Q ₅₇ do not enter the saturation region.) Then, this pulse Pc,
Since the luminance signal Sy is supplied to Q ₁₅ and Q ₁₆ , when the luminance signal Sy is at the black level (Pc="1"), the transistor Q ₁₅ is turned on and the transistor Q ₁₆ is turned off. Therefore, transistor _Q12 is a transistor
Since Q ₃₂ acts as a constant current source and an emitter follower, when the luminance signal Sy is supplied to terminal T ₁ ,
This signal Sy is supplied to the capacitor C ₁ through the signal line of the terminal T ₁ → transistor Q ₁₁ → resistor R ₁₁ → transistor Q ₁₂ → capacitor C ₁ , and the capacitor C ₁ is charged to the black level of the signal Sy .

When the signal Sy is not at the black level (Pc="0"), the transistor _Q15 is turned off and the transistor _Q16 is turned on. Therefore, if the collector current (sink type constant current) of the transistor Q ₃₂ is I ₃₂ , this current I ₃₂ flows through the resistor R ₁₁ through the transistor Q ₁₆ , so the resistor
A voltage drop of the magnitude R ₁₁ ×I ₃₂ occurs across _R 11 , which turns off transistor Q ₁₂ . Therefore,
At this time, capacitor _C1 is no longer charged.

That is, the capacitor _C1 is charged to the black level only when the luminance signal Sy is at the black level.

Therefore, the black level of the signal Sy is sampled and held in the capacitor _C1 , and the terminal voltage _V1 of the capacitor _C1 indicates the black level of the signal Sy.

Then, the voltage V ₁ indicating the black level of the capacitor C ₁ is taken out by the transistor Q ₁₃ and supplied to the transistor Q ₁₄ , and the signal Sy at the terminal T ₁ is transferred from the terminal T ₁ →transistor Q ₁ →resistor R ₁
→ Transistor Q ₂ → Transistor Q ₃ → Transistor Q ₄ It is supplied to transistor Q ₄ through the signal line of 4. Therefore, since the brightness signal Sy is compared with the voltage _V1 indicating the black level in the differential amplifier _A1 , the terminals _T2 and _T3 have the following voltages:
Luminance signal with black level clamped to a constant level
Sy is taken out. Note that the black level of this extracted luminance signal Sy is Vcc-1/2×R Vcc: power supply voltage I ₂₄ : collector current R of transistor Q ₂₄ = R ₂ = R ₃ .

In this way, the luminance signal Sy whose black level is clamped to a predetermined level can be obtained at the terminals T ₂ and T _3. In this case, especially according to the present invention,
When converting into an IC, only the capacitor _C1 can be attached externally, and the only external terminal required is terminal _T4 . Therefore, the number of external terminals and external parts are also small.
It is advantageous for IC implementation and has a large effect.

Furthermore, the voltage drop V _BE between the base and emitter of the transistor varies depending on the temperature, but as is clear from Fig. 3, the signal line of the luminance signal Sy (terminal T ₁ → transistor Q ₁ → resistor R ₁ → transistor signal line of _{voltage V 1 indicating} black level ( _{terminal T 1 →} transistor Q ₁₁ → resistor R ₁₁ → transistor Q ₁₂ → transistor Q ₁₃ → transistor Q) ₁₄ signal line) have the same DC configuration, so even if the voltage V _BE changes due to temperature, the terminal
The black level of the luminance signal Sy at T ₂ and T ₃ does not change.

Furthermore, in an IC, it is extremely easy to form two signal lines in the same format with the same constants, so this is also suitable for IC implementation. In addition, it can be directly connected to the previous stage circuit, does not require a large amount of current to flow, and has low power consumption.

In the example shown in FIG. 4, the configuration is simplified, and the clamp pulse Pc from terminal _T11 is
is taken out through the emitter follower transistor Q ₆₁ , and the transistors Q ₆₃ and Q ₆₄
and _Q16 constitute a current mirror circuit.

And when Pc="1", the transistor
Since Q ₆₂ is turned on and transistor Q ₆₄ is turned off, transistor Q ₁₆ is also turned off, and
Transistor _Q32 turns on. Therefore, the transistor _Q12 acts as an emitter follower, so that the capacitor _C1 is charged to the black level of the signal Sy.

Also, when Pc="0", the transistor
Since Q ₆₂ is turned off and transistor Q ₆₄ is turned on, a collector current equal to the collector current of transistor Q ₆₃ flows through resistor R ₁₁ in transistor Q ₁₆ , and transistor Q ₁₂ is turned off. Then, transistor _Q32 is also turned off.

Therefore, the voltage _V1 indicating the black level of the signal HSy is sampled and held in the capacitor _C1 .
Since this voltage V ₁ and the signal Sy are compared by the differential amplifier A ₁ , a luminance signal Sy whose black level is clamped to a constant level is taken out from the terminal T ₂ .

[Brief explanation of drawings]

1 and 2 are diagrams for explaining this invention, and FIGS. 3 and 4 are connection diagrams of an example of this invention. T ₁ is an input terminal, and T ₂ and T ₃ are output terminals.

Claims (1)

[Claims] 1. First and second signal lines that are configured to be DC-equal to each other and to which an input signal is commonly supplied; and output ends of the first and second signal lines are one and the other. a differential amplifier connected to the input terminals of the second signal line, a hold circuit having a hold capacitor provided on the second signal line, and a hold circuit connected to the hold capacitor and controlled on/off by a clamp pulse. a charging/discharging current source; and a sampling circuit provided on the second signal line, which has a unidirectional switch that becomes conductive due to the clamp pulse and conducts when a predetermined potential difference occurs between input and output. When the clamp pulse is at one level, the unidirectional switch of the sampling circuit becomes conductive, the charging/discharging current source operates, and the input signal is sampled and held in the capacitor, and the unidirectional switch of the sampling circuit becomes conductive. When the switch is not conducting, the capacitor is charged and discharged by the charging and discharging current source, and when the clamp pulse is at the other level, the unidirectional switch becomes inoperative and the charging and discharging current source is also disabled. The clamp circuit is activated, and the hold output of the capacitor is supplied to the other input terminal of the differential amplifier, and the input signal is clamped and extracted from the differential amplifier.