JPH0511470B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vertical synchronization separation circuit for television signals, and particularly to a circuit that enables synchronization separation even in a weak electric field.

[Conventional technology]

FIG. 3 is a block diagram of this type of conventional vertical synchronization separation circuit. That is, the signal from signal input terminal 1 is passed through low pass filter 2 (hereinafter referred to as LPF).
The input of an inverter 3 was connected to the output of this LPF 2, and the output of this inverter 3 was used as a signal output terminal 5 to form a vertical synchronization separation circuit.

[Problems to be Solved by the Invention] This conventional vertical synchronization separation circuit, as shown in FIGS.
In contrast to Figure a), the output of the LPF 2 (Figure 4b) above a predetermined threshold voltage was inverted by the inverter 3 and outputted (Figure 4c). However, in a weak electric field, noise is added to the signal output (Figure 5a), so the output amplitude of LPF2 is reduced as shown in Figure 5b.
The voltage becomes so small that it no longer reaches the logic threshold voltage of the inverter 3, and the output of the inverter 3 does not invert as shown in FIG.

Also, when using a CMOS structure in a conventional circuit,
The above logic threshold voltage was set by changing the size ratio of the PcH transistor and NcH transistor of the inverter 3. However, inverter 3
The logic threshold voltage of is approximately 1V threshold voltage (hereinafter referred to as _VT ) of the NcM transistor (
(approximately 1V), and there are large manufacturing variations in the voltage value. For example, when the power supply voltage is 5V,
The drawback was that it varied by about 1V, and there was a limit to vertical synchronization separation in weak electric fields.

SUMMARY OF THE INVENTION An object of the present invention is to provide a vertical synchronization separation circuit that solves these problems and enables vertical synchronization separation even in a weak electric field.

[Means for solving problems]

The vertical synchronization separation circuit of the present invention includes a low-pass filter that receives an input signal from an input terminal, a capacitor that receives a signal output from this low-pass filter, a resistor that has one end connected to the output of this capacitor, and one end of this resistor that receives an input signal from an input terminal. a first MOS inverter, the other end of which is connected to the input end and the output end, respectively;
and a second MOS inverter whose input terminal is the output of the capacitor and whose output terminal is a signal output terminal.

The vertical synchronization separation circuit of the present invention has a conventional configuration.
In order to lower the detection level that could not be lowered below V _T of NcH, by separating the DC component of the integrating circuit and the inverting amplifier section and using a bias circuit in which the input and output of the MOS inverter were connected with a resistor, Synchronous separation in a weak electric field is achieved by biasing the inverting amplifier section and giving it a logic threshold voltage slightly higher than the bias level.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. In this embodiment, the signal output terminal 1 and the input of LPF2 are connected, the output of LPF2 is connected to one end of the coupling capacitor C1, and the input and output are connected to the other end of the coupling capacitor via the resistor R1. The input of a MOS inverter 4, which is connected to form a bias circuit, and the input of a MOS inverter 3, which forms an inverting amplifier, are connected, and the output of the MOS inverter 3 is used as a signal output terminal 5.

FIGS. 2a to 2d show respective waveform diagrams of FIG. 1. Second
Figures a and d show the input signal waveform and LPF output waveform, and are the same as Figures a and b. Figure 2c shows the output waveform of the coupling capacitor C1,
The waveform is obtained by separating the DC component from the LPF output signal (Fig. 5b) and further adding the bias circuit voltage V _T2 .

Here, the bias circuit voltage V _T2 becomes the logic threshold voltage of the MOS inverter 4, and any voltage difference between it and the logic threshold voltage V _T1 of the MOS inverter 3 is applied to these MOS inverters 3 and 4.
By setting the transistor size ratio appropriately, the bias circuit voltage can be adjusted as shown in Figure 2d.
It is set a little smaller than V _T1 , and its vertical synchronization separated output can be obtained at output terminal 5.

Here, the difference voltage between voltages V _T1 and V _T2 is determined by the ratio of transistor sizes of each PcH and NcH of MOS inverters 3 and 4, so design is easy and approximately
The differential voltage can be set from 0V, and manufacturing variations are extremely small.

〔Effect of the invention〕

According to the present invention, the integrating circuit section and the inverting amplifier section are separated in terms of direct current, the inverting amplifier section is biased near the first inverter circuit threshold voltage, and the circuit threshold voltage of the second inverter is set to the first inverter circuit threshold voltage. By setting the circuit threshold voltage slightly higher than the inverter's circuit threshold voltage, even if the voltage level of the integrated waveform decreases in a weak electric field (even in the region where vertical synchronization separation could not be achieved when the voltage was below V _T ), the two inverters in the inverting amplifier section The detection voltage level can be lowered to the difference between the circuit threshold voltages. In addition, by configuring the MOS inverter with an integrated circuit, the difference in circuit threshold voltage is determined by the size ratio of the transistors, so the difference in circuit threshold voltage can be kept almost constant, and stable vertical synchronization separation can be achieved even in a weak electric field. It becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a vertical synchronization separation circuit according to an embodiment of the present invention, FIGS. 2 a to d are vertical synchronization separation waveform diagrams in the weak electric field of FIG. 1, and FIG. 3 is a circuit diagram of a conventional vertical synchronization separation circuit. Circuit diagrams, Figures 4a-c are vertical synchronization separation waveform diagrams of various parts in the strong electric field of Figure 3, and Figures 5a-c.
c is a vertical synchronization separation waveform diagram of each part in a weak electric field in FIG. 3; In the figure, 1... signal input terminal, 2... low pass filter, 3, 4... inverter, 5... signal output terminal, C1... capacitor, R1... resistor.

Claims (1)

[Claims] 1 A low-pass filter that receives an input signal from an input terminal, a capacitor that receives a signal output from this low-pass filter, a resistor that has one end connected to the output of this capacitor, and one end and the other end of this resistor that are connected to the input terminal, respectively. the output end and the second
A vertical synchronization separation circuit including a 1MOS inverter and a 2nd MOS inverter whose input terminal is the output of the capacitor and whose output terminal is a signal output terminal.