JPH0193919A - Level shifting circuit - Google Patents

Abstract

PURPOSE:To obtain a level shifting circuit having uniform rising and falling time characteristics, a short transmission delay time, and high precision by complementarily constituting DC cut capacitors, clamp diodes, and grounded- emitter transistors TRs. CONSTITUTION:Grounded-emitter TRs Tr1 and Tr2 take two states, namely, the cut-off state and the turning-on state in a saturation area by DC cut capacitors C1 and C2 and clamp diodes D1 and D2. Two kinds of state namely, the state where the first TR Tr1 is cut off and the second TR Tr2 is turned on in the saturation area and the state where the first TR Tr1 is turned on in the saturation area and the second TR Tr2 is cut off are taken by this complementary circuit constitution to perform level shifting operation. Since all circuits are complementarily provided, the balance between the rising characteristic and the falling characteristic is improved and the transmission delay time is shortened and the precision is improved.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to the configuration of a level shift circuit.

[Summary of the invention]

In a level shift circuit, the present invention performs input coupling with a DC cut capacitor, clamps the reverse bias between the pace emitters of the transistors with a clamp diode, and provides a common emitter transistor, and the above components are complemented. establish.

The complementary first transistor is cut off, and the second transistor is turned on in the saturation region. Next, when the input changes in the opposite direction, the first transistor turns on in the saturation region and the second transistor cuts off. Due to the function of the clamp diode, the base potential is driven within a range of approximately ±0.6V with respect to the emitter potential.

Therefore, effects such as level shifting to approximately the same amplitude as the power supply voltage range, uniform rise and fall time characteristics and high speed, and drive input amplitude of 2 V or more are achieved.

[Conventional technology]

Conventional level shift circuits are described in National Semiconductor Corporation's Interface Data Book, 5-
An example is DSO026 shown on page 13. It integrates NPN (NPN) transistors, diodes, and resistors on a silicon monolithic substrate, and is characterized by high speed and high load capacity drive. The input coupling circuit selects capacitive coupling or resistive coupling depending on the input voltage level.

As an example of a second conventional level shift circuit, NEC (
For example, the μPD4053BC shown in DCMOS Digital IC Co., Ltd. (DCMOS Digital IC 1986, page 139) is a complementary MOS on a silicon monolithic substrate, and transistors are integrated to enable highly accurate level shifting. The coupling circuit of the input section is directly connected.

[While the invention is trying to solve the problem]

However, the above-mentioned conventional techniques have problems in that the first conventional example has large power consumption, rise and fall time characteristics are not uniform, and the high level and low level to be level shifted are likely to change. The second conventional example has a problem that the transmission delay time is long.

SUMMARY OF THE INVENTION An object of the present invention is to provide a level shift circuit with uniform rise and fall time characteristics, short transmission delay time, and high precision.

[Means for solving problems]

The level shift circuit of the present invention is characterized in that input coupling means using a DC cut capacitor, means for clamping reverse bias between the base and emitter of a transistor using a clamp diode, and amplification means using a common emitter transistor are provided in a complementary manner. do.

[Effect]

According to the above configuration of the present invention, the DC cut capacitor and the clamp diode cause the common emitter transistor to take two states: a cutoff state and an on state in the saturation region. By configuring the circuits in a complementary manner, the first transistor is in the cutoff state and the second transistor is in the on state in the saturation region, or the first transistor is in the on state in the saturation region and the second transistor is in the on state in the saturation region. A level shift operation is performed by taking the above two types of states, in which the transistor is in a cut-off state.

〔Example〕

FIG. 1 is a circuit diagram of a level shift circuit in an embodiment of the present invention.

The input signal VIN is connected to a common emitter transistor Tr via resistors R1 and R2 and DC cut capacitors C1 and C2.
, Tr.

Common emitter transistors T r 1 , T r ! A clamp diode D1 is connected in parallel between the base and emitter of
, D2 are connected. The collectors of the common emitter Trt and Tr are commonly connected to the output terminal Vout.
becomes. A pull-up resistor RLN and a load capacitor CL are connected to the output terminal Vout. VDDlVSS is a power supply terminal.

FIG. 2 shows an operational waveform diagram of the level shift circuit in the embodiment of the present invention. The input signal VIN, the base waveform T r 1-B of the emitter-grounded transistor Tr +, and the base waveform Try-B1 of the emitter-grounded transistor Tr are illustrated as the output signal Vout.

The following description will be made assuming a level shift circuit that drives a capacitive load, such as a clock driver circuit for a MOS memory.

In FIG. 2, a square wave having an amplitude of 2V or more is applied as the input signal VIN. In state ■, VIN is at low level and Trt-B is at VDD-0,8■, so transistor T r + is turned on in the saturation region H1T r *
-B is VSS-0.6V, so the transistor Tr is in a cut-off state, so Vout is at the VDD level.

Next, set VIN to high level. In FIG. 2, the state changes to ■. That is, the transistor Tr rapidly changes from the on state to the cutoff state due to the current flowing from the signal source VIN to the power supply terminal VDD via the resistor RI, the DC cut capacitor C1% clamp diode D, and the DC cut capacitor C1% clamp diode D. Also, from the signal source VIN, resistor Rz, DC cut capacitor C1, transistor Tr! The current flowing between the base and emitter of the transistor Tr and the power supply terminal VSS causes the transistor Tr to rapidly change from a cut-off state to an on-state. At this time, the charge stored in the load capacitor CL is discharged by the collector current of the transistor Tr. The collector current is equal to the product of the base current and the current amplification factor. The response time is approximately the value obtained by dividing the amount of charge stored in the load capacitor CL by the collector current of the transistor Tr. When the charge stored in the load capacitor CL is discharged, the collector current of the transistor Tr becomes almost 0, and the flefter potential becomes approximately Vss, which is an on state in the saturation region.

Next, set VIN to low level. In FIG. 2, the state changes from state ■ to state ■. That is, from the power supply terminal VSS to the clamp diode Dx, the DC cut capacitor CA,
The current flowing through the resistor R1 to the signal source VIN causes the transistor Tr to rapidly change from an off state to a cutoff state.

Also, from the power supply terminal VDD to the transistor Tr+ /<-
The transistor Tr+ rapidly changes from the cut-off state to the on-state due to the current flowing between the transmitter and the signal source VIN via the DC cut capacitor CIN resistor R1. At that time, charge is transferred to the load capacitor CL by the transistor T.
It is charged by the collector current of r. The collector current is equal to the product of the base current and the current amplification factor. load capacitor c
The response time is approximately the value divided by the collector current of the charge transistor Tr charged to L. Load capacitor CL
When the charge is completely charged, the collector current of the transistor Trl becomes almost 0, and the collector current becomes almost VDD, and the transistor Trl enters an on state in the saturation region.

Due to the function of the clamp diodes D, ,D, the base potential of the transistors Trl and Try operates within about ±0.6V with respect to the emitter potential, so the change from the on state to the off state or from the off state to the on state is It's very fast. Resistors R1 and R2 have the function of limiting the current flowing from the signal source VIN. DC cut capacitor C
,,C.

prevents direct current from flowing from the signal source VIN.

The product of the values of the resistors R, , R, and the DC cut capacitors C8, C8 determines the time constant for the base current of the transistors T r 1 and T r t to flow, and is therefore set in accordance with the frequency of the signal source VIN. Resistors R1 and R1 are transistors T
Since it limits the bias current of I" I and T r x, the smaller it is, the better when high-speed operation is required. It is omitted, especially when the internal resistance of the signal source VIN is high. Resistor R1
is the transistor Tr, 1Tr! Both are for preventing the bias current from flowing and the output from being open-circuited, and may be omitted or may be provided between the wi source terminal VSS and the output terminal Vout.

The response speed is the reciprocal of the resistance R,, R, and the transistor Tr+
, Try, the reciprocal of the value of the load capacitor CL, and the values of the DC cut capacitors C, , C2.

Therefore, in order to make the response speeds the same at the rise and fall times, this can be easily achieved by using complementary transistors with the same current amplification factors for the transistors T r + and T r x.

The base potential of the transistors Tr, , Try is 1.2V
Signal source VIN that is driven at approximately the amplitude and has an amplitude of 1.2V or more
The voltage amplitude acts to cause the bias current to flow.

Since one of the transistors T r + and T r 1 is always in a cutoff state, no through power supply current flows.

Since the on-state of the transistors Tr, Tr settles in the saturation region where the collector current is 0, there is little change between the high level and the low level that are level-shifted.

〔Effect of the invention〕

As described above, according to the present invention, the following effects are achieved.

Since one of the first transistor and second transistor, which are provided complementary to each other, is driven in the cutoff state and the other in the saturation region, the high level and low level to be level shifted are the same as the power supply voltage range and do not change. few. Furthermore, since no through-power supply current flows, the effect of low amping power is achieved.

Since all the circuits are provided in a complementary manner, the rise and fall characteristics are well balanced.

Since a DC cut capacitor and a clamp diode are provided, the effect of level shifting is achieved as long as the input amplitude is 2V or more.

The combination of a clamp diode and a complementary transistor produces the effect of shortening the propagation delay time.

Further, the present invention has a special effect when used as a clock drive circuit for a contact type image sensor.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a level shift circuit in an embodiment of the present invention. FIG. 2 is an operational waveform diagram of the level shift circuit in the embodiment of the present invention. C, , C, ......DC cut capacitor D, , D, ...... Clamp diode T r 1, T r t... ...Emitter grounded transistor and above Applicant Seiko Epson Co., Ltd. Agent Patent attorney Tsutomu Mogami and 1 other person τ 〉

Claims (1)

[Claims] A level shift circuit characterized by complementary configurations of a DC cut capacitor, a clamp diode, and a common emitter transistor.