JPH01261024A - Logic circuit - Google Patents

Abstract

PURPOSE:To attain power consumption without disturbing high speed operation by providing a short-circuit transistor(TR) whose collector and emitter are connected in parallel with a load means of an output emitter follower circuit of a logic circuit, whose base is capacitance-coupled with the emitter of the input TR and whose conductance is temporarily increased at low level output. CONSTITUTION:The base of a TR T2 is subject to capacitive coupling with the emitter of a TR T3 via a differentiation circuit comprising a capacitor C1 and a resistor R4 and a prescribed bias voltage is supplied thereto via a bias circuit comprising a TR T4 and the resistor R4. The TR T2 is temporarily turned on when the digital input signal Di changes from a low level VL to a high level VH, the conductance is increased temporarily and the level change in a digital output signal Do is speeded up regardless that the resistor Rl has a comparatively large resistance. Thus, the power consumption of the NTL circuit is reduced without disturbing its high speed operation.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a logic circuit, for example, an NTL (N-on-T) with an output emitter follower circuit added.
The present invention relates to a technique that is particularly effective when used in threshold logic (threshold logic) circuits.

[Conventional technology]

There is an NTL circuit that receives a small amplitude digital input signal and performs a high-speed logic operation. In addition, the NTL circuit with an output limiter follower circuit is added to the above NTL circuit.
There is a TL circuit (hereinafter, this NTL circuit with an output limiter follower is referred to as an NTL circuit).
There is a high-speed logic integrated circuit whose basic configuration is a TL circuit.

For example, as shown in FIG. 87, the NTL circuit has an input transistor T3 that receives a digital input signal Di at its base, and is provided between the collector of the transistor T3 and the circuit power supply voltage Vcc and power supply voltage VEE, respectively. The basic configuration is an input limiter follower circuit consisting of resistors R2 and R3. The collector potential of the transistor T3 is made into the digital output signal Do of the NTL circuit via an output limiter follower circuit consisting of the transistor T1 and the resistor R1.

Regarding NTL circuits, for example, Japanese Patent Application No. 61-2696
It is described in No. 99.

[Problem to be solved by the invention]

Conventional NTL circuits as described above have the following problems. That is, as described above, the NTL circuit includes an output limiter follower circuit including the transistor T1 and the resistor R1. Here, the resistor R1 is designed to have a relatively large resistance value. As a result, the operating current of the output limiter follower circuit is reduced, and the power consumption of the NTL circuit is reduced. On the other hand, a relatively large load capacitance cL floating in connection wiring etc. is coupled to the output terminal of the NTL circuit, that is, the emitter of the transistor TI. This load capacitance CL is the digital output signal D of the NTL circuit.
When O is set to high level, it is charged through transistor TI, and when digital output signal DO is set to low level, it is discharged through resistor R1. However, as described above, the resistor R1 is designed to have a relatively large resistance value. For this reason, especially when it is changed from a high level to a low level, the NTL
The level of the digital output signal DO of the circuit is equal to the load capacity it
It is changed relatively slowly according to a predetermined time constant determined by CL and resistor R1. This hinders the high-speed operation of the NTL circuit, and limits the speeding up of high-speed logic integrated circuits and the like including the NTL circuit.

An object of the present invention is to provide a logic circuit such as an NTL circuit that achieves low power consumption without interfering with its high-speed operation. Another object of the present invention is to achieve faster operation and lower power consumption of high-speed logic integrated circuits including NTL circuits and the like.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the short-circuit circuit is connected in parallel with the load means constituting the output nimmy/tau follower circuit of a logic circuit such as an NTL circuit, and its base is capacitively coupled to the emitter of the input transistor, so that its conductance is temporarily increased when outputting a low level. A transistor is provided.

[For production]

According to the above-described means, it is possible to temporarily short-circuit the load means at the beginning of low level output, thereby speeding up the level change of the output signal. As a result, the resistance value of the load means can be increased (by which the operating current of the output limiter follower circuit can be reduced), and the power consumption can be reduced without interfering with the high-speed operation of the NTL circuit or the like.

(Embodiment 1) Fig. 1 shows a circuit diagram of an embodiment of an NTL circuit to which the present invention is applied.Furthermore, Fig. 2 shows the input/output characteristics of the NTL circuit shown in Fig. 1. 3 shows a characteristic diagram illustrating the relationship between the base voltage and collector current of the transistor T2 included in the NTL circuit of FIG. 1.The NTL circuit of this embodiment has the following characteristics: Although not particularly limited, it is included in a high-speed logic integrated circuit and functions as an inverter circuit.The high-speed logic integrated circuit is equipped with a large number of various logic gate circuits having the same circuit configuration as the NTL circuit shown in FIG. Each circuit element in Figure 1 is formed on a single semiconductor substrate, such as single crystal silicon, along with other circuit elements (not shown) of a high-speed logic integrated circuit. All transistors are NPN type transistors.

In FIG. 1, although the NTL circuit is not particularly limited,
Input transistor T3 (third transistor) and power supply voltage Vc between the collector of the input transistor T3 and the circuit.
c (first power supply voltage) and a resistor R2 (second load means) provided between the emitter of the input transistor T3 and the circuit power supply voltage VEE (second power supply voltage). It is constituted by R3 (third load means).

The voltage at the collector of the input transistor T3, ie, the voltage at the node n1, is supplied to the base of the output transistor Tl (first transistor) constituting the output limiter follower circuit. A resistor R1 (first load means) is provided between the emitter of the output transistor TI and the circuit power supply voltage VEE. This resistor R1 is designed to have a relatively large resistance value in order to reduce the operating current of the output limiter follower circuit and reduce the power consumption of the LNTL circuit.

The emitter voltage of the output transistor T1 is used as the output signal of this NTL circuit, that is, the digital output signal DO.

The base of the shorting transistor T2 (second transistor), which is provided in parallel with the resistor R1 constituting the output limiter follower circuit, is connected to the emitter of the input transistor T3 via the capacitor CI (first capacitor). be combined. Moreover, the base of the transistor T2 is
Although not particularly limited, it is coupled to the circuit power supply voltage Vcc via the transistor T4 (fourth transistor) and to the circuit power supply voltage VEE via the resistor R4 (fourth load means). A predetermined constant voltage Vc is supplied to the base of the transistor T4. That is, in this embodiment, the resistor R4 together with the capacitor C1 constitutes a differentiating circuit that transmits a change in the emitter voltage of the input transistor T3 to the base of the shorting transistor T2, and together with the transistor T4, the resistor R4 is connected to the base of the transistor T2. A bias circuit that supplies a bias voltage vb is configured.

Here, the constant voltage Vc supplied to the base of the transistor T4 is as shown in FIG.
A predetermined voltage is set to apply a bias voltage Vb to the base of T2 to turn the transistor T2 into a very weak ON state. Therefore, the level of the digital output signal Do of the NTL circuit is high level vH or low level vL.
In a stable state fixed at , the transistor T2 is turned on very weakly and its conductance is reduced. At this time, a relatively small emitter current IEI such as approximately IE1-IC2'+DO/R1 is caused to flow through the output transistor T1. As a result, the operating current of the output emitter follower circuit is reduced, and the power consumption of the NTL circuit is reduced.

Note that a digital input signal Di is supplied to the base of the input transistor T3 from another circuit (not shown) of the high-speed logic integrated circuit. Here, the power supply voltage Vcc of the circuit is set to the ground potential, and the power supply voltage vEE of the circuit is set to a predetermined negative power supply voltage. Further, the digital input signal Di is assumed to have a relatively small signal amplitude, for example, its high level V is -O, aV and its low level -L is -1, 4V.

Here, the level of the digital output signal Do of the NTL circuit of this embodiment will be explained. Digital input signal D
When i is set to a predetermined low level vL, the collector current ■C3 of the input transistor T3 is
The base-emitter voltage and current amplification factor of 3 are V, respectively.
I] E3 and β3, Ic3 agony (VL VBE!l VEE) / (R3X 1
j3), which is a relatively small value. At this time, the voltage at the node n1 is set to a high level such as V)lc=-R2x Ic3. The high level vnc of the node nl is further shifted by the base-emitter voltage vBEI of the transistor T1 constituting the output limiter follower circuit, and then becomes the high level of the digital output signal DO of this NTL circuit, and the high level V , 4 is V)l=V)IcVBEI, and the high level ■H of the digital output signal DO is,
This is nothing but the high level V14 of the digital input signal Di.

On the other hand, the digital input signal Di is at a predetermined high level ■H
When the collector current 1 of the input transistor T3 is
e3' is the base-emitter voltage and current amplification factor of input transistor T3, respectively, VBE3゛ and β3°.
When lc3'- (VHVBE3' VEE) / (R3Xβ3
'').At this time, the voltage at the node n1 is set to a low level such as VLc=-R2X Ic3'.The low level LC at the node n1 is the voltage at the output transistor 1 After being shifted by the base-emitter voltage VBEI', the digital output signal Do of this NTL circuit is set to a low level.At this time, the low level VL of the digital output signal DO becomes vt, -vt, cVBEI.Digital The output signal DOO low level ■L is
This is nothing but the low level VL of the digital input signal DI.

Next, the transient operation of the NTL circuit including the differential circuit will be explained. Digital input signal Di is high level V
When changing from H to low level ■L, the base voltage Ve2 of the short-circuiting transistor T2 is temporarily lowered by the signal width of the digital input signal Di by providing a differentiator circuit consisting of a capacitor CI and a resistor R4. be done.

Therefore, the shorting transistor T2 is in a cutoff state, and the digital output signal Do is changed from the low level VL to the high level VH without being influenced by the transistor T2. At this time, the digital output signal Do
The level of is changed relatively rapidly through the transistor Tl of the output emitter follower circuit.

On the other hand, when the digital input signal D+ changes from the low level VL to the high level VH, the base voltage Ve2 of the shorting transistor T2 is temporarily increased by the signal amplitude of the digital input signal Di. Therefore, transistor T2 is turned on and its conductance is temporarily increased. Therefore, the load capacitance coupled to the output terminal of the NTL circuit is rapidly discharged via the transistor T2, even though the resistor R1 is designed to have a relatively large resistance value. As a result, the level of digital output signal Do is rapidly changed from high level VH to low level VL. In other words, in the NTL circuit of this embodiment, the resistance value of the resistor R1 constituting the output emitter follower circuit is increased, and the short-circuiting transistor T2 is provided in parallel with it, so that its high-speed operation is not hindered and the resistance is low. This reduces power consumption.

As described above, in the NTL circuit of this embodiment, the resistor R1 constituting the output emitter follower circuit is designed to have a relatively large resistance value, and the shorting transistor T2 is provided in parallel with the resistor R1. It will be done. The base of this transistor T2 is capacitively coupled to the emitter of a transistor T3 constituting an input limiter follower circuit via a differentiating circuit consisting of a capacitor C1 and a resistor R4. Further, a predetermined bias voltage vb is supplied to the base of the transistor T2 via a bias circuit including a transistor T4 and a resistor R4. The transistor T2 is temporarily turned on when the digital input signal DI is changed from the low level vL to the high level VH, that is, when the digital output signal Do is changed from the high level V to the low level vL. Conductance is temporarily increased. Therefore, the level of the digital output signal Do changes quickly even though the resistor R1 has a relatively large resistance value. As a result, the NTL circuit of this embodiment has low power consumption without hindering its high-speed operation.

[Embodiment 2] FIG. 4 shows a circuit diagram of a second embodiment of an NTL circuit to which the present invention is applied. The NTL circuit of this embodiment basically follows the NTL circuit of FIG. 1 above. Transistor Tl in FIG.

T2 and T4 and resistors R1-R4 and capacitor C1
correspond to the transistors 'rl, T2, and T4, the resistors R1 to R4, and the capacitor CI in FIG. 1, respectively. Hereinafter, explanations will be added regarding parts that are different from the embodiment shown in FIG.

In FIG. 4, three parallel transistors T5 to T7 (third transistors) are provided between the resistor R2 and the resistor R3, although not particularly limited. The bases are supplied with digital input signals Dil, and the bases of transistors T6 and T7 are supplied with corresponding digital input signals D12 and D1.
i3 is supplied respectively.

When the digital input signals DIl-Di3 are all set to the low level -L, the potentials of the commonly coupled emitters of the transistors T5-T7 are set to the low level, and a relatively small collector current flows through the resistor R2. Therefore, the node n1 is at a high level V)Ic, similar to the embodiment shown in FIG. 1, and the digital output signal Do is at a predetermined high level VH.

On the other hand, when one of the digital input signals Dll-Di3 is set to high level VH, the transistor T5
The potential of the commonly coupled emitters of ~T7 becomes high level, and a relatively large collector current flows through the resistor R2. Therefore, the digital output signal Do is set to a predetermined low level vL.

That is, in the NTL circuit of this embodiment, the digital output signal Do is Do-Di 1-Di 2 ・Di 3-otl+ot
It functions as a three-person NOR gate circuit that satisfies the logical formula 2+Dta.

As described above, in the NTL circuit of this embodiment, the input transistors provided as the transistors Tl in the embodiment of FIG. transistors T5 to T7. The digital output signal DO is the digital input signal Di
When all of l to Di3 are set to low level VL, they are selectively set to high level vH, so that the NTL circuit of this embodiment functions as a three-man NOR gate circuit. Needless to say, the NTL circuit of this embodiment, like the embodiment shown in FIG. 1, has low power consumption without hindering its high-speed operation. Furthermore, by increasing or decreasing the number of input transistors arranged in parallel, a NOR gate circuit with an arbitrary fan-in number can be realized.

[Embodiment 3] FIG. 5 shows a circuit diagram of a third embodiment of the NTL circuit to which the present invention is applied. The NTL circuit of this embodiment basically follows the embodiment of FIG. 1 above. Transistors T1-T4, resistors R1-R4, and capacitor C1 in FIG. 5 correspond to transistors T1-T4, resistors R1-R4, and capacitor CI in FIG. 1, respectively. Hereinafter, explanations will be added regarding parts that are different from the embodiment shown in FIG.

In FIG. 5, a diode D1 is provided between the base of the transistor T4 and the circuit power supply voltage Vcc. Further, although not particularly limited, a resistor R5 is provided between the base of the transistor T4 and the power supply voltage VEE of the circuit, and a resistor R5 is provided between the base of the transistor T4 and the emitter of the output transistor T1, that is, the output terminal of the NTL circuit. is provided with a capacitor C2. As a result, the resistor R5 and the transistor T4 are connected together with the diode DI.
A constant voltage generating circuit is configured to apply a predetermined constant voltage Vc to the base of the transistor T4, and together with the capacitor C2, a differentiating circuit is configured to transmit a level change of the output terminal to the base of the transistor T4. Here, the resistor R5 is designed to have a relatively large resistance value, so that it does not hinder the reduction in power consumption of this NTL circuit.

When the level of the digital output signal DO is fixed at the high level VH or the low level VL, a predetermined constant voltage Vc determined by the forward voltage VDFI of the diode Di is supplied to the base of the transistor T4. This constant voltage Vc is determined by the transistor T as in the embodiment shown in FIG.
The voltage value is set to a predetermined voltage value capable of applying a bias voltage vb to the base of the transistor T2 so that the transistor T2 is turned on very weakly. For these reasons, the transistor T2 of this embodiment exhibits the same effect as that of the embodiment shown in FIG. be converted into

By the way, as described above, a differentiating circuit consisting of a capacitor C2 and a resistor R5 is provided between the output terminal of the NTL circuit of this embodiment and the base of the transistor T4.

This differentiating circuit has the effect of promoting discharge of the capacitor C1 at the same time that the digital output signal Do becomes low level, thereby improving responsiveness to a pulsed input signal.

As described above, in the NTL circuit of this embodiment, the diode D1 is provided between the base of the transistor T4 constituting the bias circuit and the circuit power supply voltage Vcc, and the diode D1 is connected between its base and the output terminal of the NTL circuit. A capacitor C2 is provided between them. Further, between the base of the transistor T4 and the power supply voltage VEE of the circuit, a constant voltage generating circuit is formed together with the diode DI, and the capacitor C2
A resistor R5 that constitutes a differentiating circuit is also provided.

This resistor R5 is designed to have a relatively large resistance value. As a result, in the NTL circuit of this embodiment, the constant voltage generation circuit for applying a predetermined constant voltage Vc to the base of the transistor T4 is simplified, and the feedback operation performed via the transistors T4 and T2 generates pulses. This improves responsiveness to sexual input signals.

As described above, since the resistors R1 and R5 are designed to have relatively large resistance values, the reduction in power consumption of the NTL circuit is not hindered.

[Embodiment 4] FIG. 6 shows a circuit diagram of a fourth embodiment of an NTL circuit to which the present invention is applied. The NTL circuit of this embodiment basically follows the embodiment of FIG. 1 above. The transistors T1 to T3, the resistors R2 and R3, and the capacitor C1 in FIG. 6 are the transistors T1 to T3 in FIG.
3, resistors R2 and R3, and capacitor CI, respectively. Hereinafter, explanations will be added regarding parts that are different from the embodiment shown in FIG.

In FIG. 6, the load means for the transistor T1 constituting the output limiter follower circuit is replaced by two resistors R6 and R7 in series. Resistance R6 and R
Although not particularly limited, a resistor R8 is provided between the commonly-coupled node of the transistors 7 and the base of the shorting transistor T2. The base of transistor T2 is further capacitively coupled to the emitter of input transistor T3 via capacitor CI. Here, the resistors R6 and R7 are designed to have relatively large resistance values, and the resistor R8 is designed to have a predetermined resistance value that makes the input impedance of the transistor T2 sufficiently large. Thereby, the resistor R8 constitutes a bias circuit that applies a predetermined bias voltage vb to the base of the short-circuiting transistor T2 together with the resistors R6 and R7, and together with the capacitor C
1 and constitutes a differentiating circuit that transmits the level change of the digital input signal D1 to the base of the transistor T2.

When the digital input signal Di is fixed at a predetermined low level ■L and the digital output signal DO is fixed at a predetermined high level ■H, the base of the shorting transistor T2 has a predetermined voltage determined by the resistance ratio of resistors R6 and R7. A bias voltage vb is applied. This bias voltage vb is
Similar to the embodiment shown in FIG. 1 above, a predetermined voltage value is set so that the transistor T2 is turned on very weakly. As a result, the transistor T2 outputs the digital output signal [
) is turned on very weakly without affecting o.

When the digital input signal Di is changed from the low level VL to the high level V)1, the base voltage of the shorting transistor T2 is determined by the change in the level of the digital input signal Di via the differentiating circuit consisting of the capacitor C1 and resistor R8. By being transmitted - made temporally high. For this reason,
Transistor T2 is temporarily in a completely on state,
Digital output signal DO is rapidly changed from high level VH to low level VL.

By the way, when the digital input signal Di is fixed at a predetermined high level V,4 and the digital output signal DO is fixed at a predetermined low level vL, the base voltage of the transistor T2 is set to a low level, and the transistor T2 is almost in a cut-off state. It is said that In this state, when the digital input signal Di is changed from the high level ■H to the low level vL, the base voltage of the shorting transistor T2 is changed due to the level change of the digital input signal Di being transmitted via the differentiating circuit. , - temporally lowered.

Therefore, the transistor T2 is further cut off, and the digital output signal DO is rapidly changed from the low level vL to the high level Vo via the transistor TI.

As described above, in the NTL circuit of this embodiment, the base of the shorting transistor T2 is capacitively coupled to the emitter of the input transistor T3 via the capacitor C1, and forms an output limiter follower circuit via the resistor R8. is coupled to a commonly coupled node of resistors R6 and R7. The resistor R8 together with the capacitor C1 constitutes a differentiating circuit that transmits the level change of the digital input signal Di to the base of the transistor T2.
6 and R7 constitute a bias circuit that applies a predetermined bias voltage vb to the base of the transistor T2. The NTL circuit of this embodiment has the advantage that its circuit configuration is further simplified, but its responsiveness to pulsed input signals is relatively poor.

As shown in the plurality of embodiments above, this invention can be applied to NT
When applied to high-speed logic integrated circuits having an L circuit as a basic configuration, the following effects can be obtained. That is, +1) A short-circuit circuit in which the base is capacitively coupled to the emitter of the input transistor and its conductance is temporarily increased when outputting a low level, in parallel form with a load means constituting an output limiter follower circuit such as an NTL circuit. By providing the transistor, it is possible to temporarily short-circuit the load means at the beginning of low level output, thereby speeding up the level change of the output signal.

(2) According to the above item (1), the resistance value of the load means is increased, the operating current of the output limiter follower circuit is decreased, and the power consumption of the NTL circuit can be reduced.

(3) According to the above (11) and (2), it is possible to achieve the effect of reducing the power consumption of the NTL circuit, etc., without impeding the high-speed operation of the circuit.

(4) The effect of the above items (11 to (3)) is that it is possible to reduce power consumption without hindering the high-speed operation of high-speed logic integrated circuits, etc., including NTL circuits, etc., and therefore, it is possible to achieve higher integration. is obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in each of the embodiments, the load means provided between the emitters of the transistors constituting the input limiter follower circuit and the output limiter follower circuit and the power supply voltage VEE of the circuit has a relatively small current. It may also be a constant current source. The high level ■H and low level vL of the digital input signal Di and the digital output signal DO can take arbitrary levels. In addition, the circuit power supply voltage Vcc can be replaced with a positive power supply voltage by setting the circuit power supply voltage VEE to the ground potential, and the bipolar transistor can be
The polarity can also be changed by replacing it with an NP type transistor. Power supply voltage of the emitter and circuit of transistor T3 that constitutes the input limiter follower circuit ■E
A capacitor for speed amplifier may be provided in the resistor R3 provided between E and E.

The embodiments shown in FIGS. 5 and 6 can have an arbitrary fan-in number by replacing the input transistor T3 with a plurality of parallel transistors. Fifth
In the figure, the diode D1 provided between the base of the transistor T4 and the circuit power supply voltage Vcc can be replaced with a plurality of diodes or transistors depending on the level of the constant voltage Vc, and the capacitor C2 may not be provided. Good too. In FIG. 6, the base of transistor T2 may be directly coupled to the commonly coupled node of resistors R6 and R7 without going through resistor R8.
Further, the specific circuit configuration and combination of power supply voltages of each example can be variously implemented.

In the above description, the invention made by the present inventor was mainly applied to NTL circuits, which is the background field of application, but the present invention is not limited to this. The present invention is applicable to logic circuits including at least output limiter follower circuits and various semiconductor integrated circuit devices including such logic circuits. It can be widely used.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, by providing a shorting transistor whose base is capacitively coupled to the emitter of the input transistor and whose conductance is temporarily increased when outputting a low level, in parallel with the load means constituting the output limiter follower circuit of the logic circuit. By temporarily short-circuiting the load means at the beginning of low level output, it is possible to speed up the level change of the output signal. As a result, the power consumption of the logic circuit can be reduced without hindering the high-speed operation of the logic circuit.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the NTL circuit to which the present invention is applied; Fig. 2 is an input/output characteristic diagram showing an embodiment of the NTL circuit of Fig. 1; 1 is a characteristic diagram showing the relationship between the base voltage and collector current of the short-circuiting transistor included in the NTL circuit; FIG. 4 is a circuit diagram showing a second embodiment of the NTL circuit to which the present invention is applied; FIG. 6 is a circuit diagram showing a third embodiment of the NTL circuit to which the present invention is applied; FIG. 6 is a circuit diagram showing a fourth embodiment of the NTL circuit to which the invention is applied; FIG. , is a circuit diagram showing an example of a conventional NTL circuit. T1 to T7...NPN type bipolar transistor, R
1-R8...Resistance, C1, C2...Capacitor, C
L...load capacitance, Dl...diode.

Claims (1)

[Claims] 1. A first transistor whose collector is coupled to a first power supply voltage and whose base receives an internal output signal; and a first transistor provided between the emitter of the first transistor and a second power supply voltage; an output emitter follower circuit consisting of a first load means arranged in parallel with the first load means, the conductance of which temporarily increases when a low level output signal is outputted through the output emitter follower circuit; A logic circuit comprising a second transistor. 2. The logic circuit is an NTL circuit to which an emitter follower circuit is added, and a third transistor whose collector is coupled to the first power supply voltage via a second load means and whose base receives an input signal; and third load means provided between the emitter of the third transistor and a second power supply voltage, the base of the first transistor being coupled to the collector of the third transistor. 2. The logic circuit according to claim 1, wherein the base of the second transistor is capacitively coupled to the emitter of the third transistor via a first capacitor. 3. A fourth transistor receiving a predetermined voltage at its base is provided between the base of the second transistor and the first power supply voltage, and a fourth transistor is provided between the base of the second transistor and the second power supply voltage. A fourth load means is provided between the first capacitor and the fourth transistor, which together with the first capacitor constitute a differentiator circuit, and together with the fourth transistor constitute a bias circuit which applies a predetermined bias voltage to the base of the second transistor. 3. The logic circuit according to claim 1 or 2, wherein the logic circuit is