JPH04352515A - Logic circuit - Google Patents

Abstract

PURPOSE:To reduce the number of circuit elements, to enable acceleration and to reduce energy consumption by controlling a pull-down transistor respectively through a current mirror type diode and the resistor of a negative feedback circuit when an input signal is L and an output signal H or in the reverse case. CONSTITUTION:When an input signal Si is turned to the prescribed L, an input transistor(Tr) T1 is almost turned off, and the non-inverted output signal of the emitter, namely, of an inside node n1 or a current switch part is turned to the L like a power supply voltage VEE. At such a time, the inverted output signal from the collector of a T2, namely, from an inside node n2 or a switch part is turned to H, and an output signal So is turned from the H of the n2 to H lower only by the VBE component of the Tr T2. As the result, a Tr T3 has a first stable operating point. When the signal Si is turned from L to H, the T1 is turned to H and the n1 is turned to H lower than the Si only by the VBE component of the T1. The n2 is turned to L lower than a circuit ground potential only by a prescribed level VSO and the signal So is turned to L. After a large base current flows to the Tr T3, the base current is limited according to a negative feedback amount.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to logic circuits, and relates to a technique particularly effective for use in bipolar logic gates mounted on high-speed logic integrated circuit devices, for example.

0002

2. Description of the Related Art An NTL (NonThr)
There are bipolar logic gates such as eshold Logc) circuits. There are also high-speed logic integrated circuit devices equipped with such bipolar logic gates, and there are digital systems that include high-speed logic integrated circuit devices.

As shown in FIG. 4, for example, an NTL circuit has an input transistor T that receives an input signal at its base.
1 and a current switch section consisting of resistors R1 and R2 that serve as the collector load and emitter load of the input transistor T1, and an output emitter follower circuit consisting of an output transistor T2 and a resistor R7 and transmitting an inverted output signal of the current switch section. .

Regarding NTL circuits, for example, Japanese Unexamined Patent Publication No. 6
It is described in Publication No. 3-124615 and the like.

[0005]

[Problems to be Solved by the Invention] The integration and capacity of high-speed logic integrated circuit devices equipped with NTL circuits, etc. are increasing significantly, and at the same time, the demand for higher speeds for these high-speed logic integrated circuit devices is also increasing. Dedicated. These factors increase the power consumption of high-speed logic integrated circuit devices, etc., and are one of the causes of an increase in the cost of digital systems including high-speed logic integrated circuit devices. In order to deal with this, as illustrated in FIG.
Logic) circuit has been proposed. However, S
The PL circuit includes a capacitor C2 and a resistor R10 forming a differentiating circuit for transmitting the non-inverted output signal of the current switch section to the base of the pull-down transistor T5, and a bias circuit for applying a predetermined bias voltage to the pull-down transistor T5. A transistor T4, diodes D2 to D4, a resistor R9, and the like are required. As a result, the number of circuit elements in the SPL circuit increases, resulting in a problem that high integration of high-speed logic integrated circuit devices and the like is hindered.

An object of the present invention is to provide a bipolar logic gate that achieves higher speed and lower power consumption while reducing the number of circuit elements. Other objects of this invention are:
The objective is to increase the integration of high-speed logic integrated circuit devices equipped with bipolar logic gates, and to promote higher speed and lower power consumption.

[0007]

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows. That is, the emitter resistor constituting the output emitter follower circuit of the NTL circuit is replaced with a pull-down transistor, and a first resistance means is provided before the pull-down transistor, for example, between the ground potential of the circuit and the base of the pull-down transistor. A negative feedback bias consisting of a diode provided between the base of the pull-down transistor and the non-inverting output node of the current switch section, and a second resistance means provided between the base of the pull-down transistor and the output terminal of the circuit. Set up a circuit.

[0008]

[Operation] According to the above means, when the input signal of the circuit is at a low level and the output signal is at a high level, the pull-down transistor is controlled via the diode which is substantially in the form of a current mirror. When the input signal is at high level and the output signal is at low level, it can be controlled via the second resistance means that serves as a negative feedback path, so the operating margin can be expanded without adding many circuit elements. This makes it possible to realize bipolar logic gates with higher speed and lower power consumption. As a result, high-speed logic integrated circuit devices equipped with bipolar logic gates can be highly integrated, and at the same time, it is possible to promote higher speed and lower power consumption.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a circuit diagram of an embodiment of a bipolar logic gate to which the present invention is applied. Also,
FIG. 2 shows a signal waveform diagram of one embodiment of the bipolar logic gate of FIG. Based on these figures, an overview of the configuration and operation of the bipolar logic gate of this embodiment as well as its characteristics will be explained. The bipolar logic gate of this embodiment is installed in a high-speed logic integrated circuit device constituting a digital system together with a large number of similar bipolar logic gates. Each circuit element in FIG. 1 is formed on a single semiconductor substrate, such as single crystal silicon, along with other circuit elements mounted on a high-speed logic integrated circuit device. In the following circuit diagrams, all illustrated bipolar transistors are NPN type transistors.

In FIG. 1, the bipolar logic gate of this embodiment includes an input transistor T1 receiving an input signal Si at its base. The collector of this input transistor T1 is an internal node n2, and is coupled to the ground potential (first power supply voltage) of the circuit via a collector resistor R1, and also coupled to the base of the output transistor T2. Further, the emitter of the input transistor T1 is connected to the internal node n1, and is connected to the power supply voltage VE via the emitter resistor R2.
E (second power supply voltage). Thereby, input transistor T1 and resistors R1 and R2 constitute a current switch section of this bipolar logic gate. Emitter of input transistor T1, i.e. internal node n
1 is a non-inverting output node of the current switch section,
Collector of input transistor T1, ie internal node n
2 is an inverted output node of the current switch section. Note that the power supply voltage VEE is a negative power supply voltage such as -2.0V, and the input signal Si is as shown in FIG.
The signal amplitude VSi is a small amplitude digital signal of about 0.6V.

In this embodiment, the output transistor T
The collector of No. 2 is coupled to the ground potential of the circuit, and the emitter thereof is coupled to the output terminal So of the circuit and to the power supply voltage VEE via a pull-down transistor T3. The base of the transistor T3 is connected to the resistor R3 (the first
is coupled to the ground potential of the circuit via a resistor R4 (second resistor means), and is coupled to the output terminal So of the circuit via a resistor R4 (second resistor means), and is further coupled to the emitter of the input transistor T1, i.e., via a diode D1. internal node n1
is combined with Thereby, the resistors R3 and R4 and the diode D1 act as a bias circuit that applies a predetermined bias voltage to the pull-down transistor T3, thereby controlling the operation of the pull-down transistor T3.

That is, when the input signal Si is set to a predetermined low level, the input transistor T1 is almost in an OFF state, and the non-inverted output signal of its emitter, that is, the internal node n1, that is, the current switch section, becomes as shown in FIG. In this case, it is set to a low level like the power supply voltage VEE. At this time, the collector of the input transistor T1, that is, the inverted output signal of the internal node n2, that is, the current switch section, becomes a high level similar to the ground potential of the circuit, so that the output signal So becomes higher than the high level of the internal node n2 of the output transistor. It is set to a high level that is lower by the base-emitter voltage VBE of T2. For these reasons, in the bias circuit, the diode D1 is turned on, and the diode D1 and the pull-down transistor T3 form a substantial current mirror configuration. As a result, the pull-down transistor T3 allows a sufficiently small collector current to flow in accordance with the forward current flowing into the diode D1 via the resistors R3 and R4, and has a stable first operating point.

Next, when the input signal Si is changed from the low level to the high level, the input transistor T1 is turned on, and the internal node n1 becomes the base-emitter voltage VBE of the input transistor T1 due to the high level of the input signal Si. The high level is considered to be lower by that amount. At this time, the internal node n2 becomes low level by a predetermined level VSo determined by the collector current of the input transistor T1 and the resistance value of the resistor R1 from the ground potential of the circuit. The low level is lower than the low level by the base-emitter voltage VBE of the output transistor T2. For these reasons, in the bias circuit, the diode D1 is turned off, and the pull-down transistor T3 is connected to the resistors R3 and R4 until the output signal So is set to a low level.
After a relatively large base current is applied through the circuit and the output signal So of the circuit becomes low level, the base current is limited according to the amount of negative feedback through the resistor R4. Therefore, the pull-down transistor T3 operates actively and rapidly discharges the load capacitance coupled to the output terminal So of the circuit until the output signal So becomes low level. After that, the collector current is limited and the stable second
It has an operating point of . Note that the internal node n2
The level difference VSo between the high level and low level of is approximately 0.
．． It is said to be about 6V. Needless to say, this level difference VSo becomes the amplitude of the output signal So.

On the other hand, when the input signal Si is returned from a high level to a low level, the input transistor T1 is turned off again, and the internal node n1 is returned to a low level such as the power supply voltage VEE. Further, the internal node n2 is set to a high level similar to the ground potential of the circuit, and thereby the output signal So is set to a high level that is lower than the high level of the internal node n2 by the base-emitter voltage of the output transistor T2. In the bias circuit, when the internal node n1 is set to a low level, the diode D1 is turned on, but only the resistor R3 is connected to the diode D1 until the output signal So of the circuit rises to a high level. After the output signal So reaches a high level, a forward current is caused to flow through the resistors R3 and R4. However, these forward currents are
Since the resistance values of the resistors R3 and R4 are made relatively large, they are set to sufficiently small values, thereby also limiting the collector current of the pull-down transistor T3.

As described above, in the bipolar logic gate of this embodiment, the emitter resistor constituting the output emitter follower circuit of the NTL circuit is replaced with the pull-down transistor T3, and the operation of the pull-down transistor T3 is substantially The discharge of the load capacitance coupled to the output terminal So of the circuit is controlled by a negative feedback bias circuit consisting of a diode D1 and a resistor R3 which constitute a current mirror circuit, and a resistor R4 which constitutes a negative feedback path. The speed is increased, and the value of the operating current flowing through the pull-down transistor T3 is limited. Then, the pull-down transistor T3 combines the forward current of the diode D1 and the resistor R, which is in a current mirror configuration.
It has two stable operating points according to the amount of negative feedback via 4. As a result, it is possible to increase the operating margin of bipolar logic gates, increase their speed, and reduce their power consumption without adding many circuit elements, making it possible to increase the integration density of high-speed logic integrated circuit devices equipped with bipolar logic gates. At the same time, it is possible to promote higher speed and lower power consumption.

As shown in the above embodiment, by applying the present invention to a logic circuit such as a bipolar logic gate mounted on a high-speed logic integrated circuit device, the following effects can be obtained. That is, (1) replacing the emitter resistor that constitutes the output emitter follower circuit of the NTL circuit with a pull-down transistor,
In the preceding stage of this pull-down transistor, for example, a first resistance means provided between the ground potential of the circuit and the base of the pull-down transistor, and a diode provided between the base of the pull-down transistor and the non-inverting output node of the current switch section. By providing a negative feedback bias circuit consisting of a second resistance means provided between the base of the pull-down transistor and the output terminal of the circuit,
The pull-down transistor is controlled via a diode that is substantially in a current mirror configuration when the input signal of the circuit is at a low level and the output signal is at a high level;
When the input signal of the circuit is at a high level and the output signal is at a low level, the collector current can be limited by controlling it through the second resistor means which becomes a negative feedback path, and the collector current can be controlled to be stable with respect to the pull-down transistor. This provides the advantage of having two operating points. (2) Item (1) above has the effect of increasing the operating margin of bipolar logic gates, speeding up their operation, and reducing power consumption without adding many circuit elements. It will be done. (3) Items (1) and (2) above enable higher integration of high-speed logic integrated circuit devices equipped with bipolar logic gates, and at the same time, promote higher speed and lower power consumption. This effect can be obtained.

[0017] Above, the invention made by the present inventor has been specifically explained based on examples, but this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. It goes without saying that there is. For example, in FIG. 1, input transistor T1 can be replaced by a plurality of input transistors in parallel configuration. Further, as illustrated in FIG. 3, the emitter resistance of the input transistor T1 is connected to two resistors R in series.
5 and R6, the operation of the pull-down transistor T3 can be controlled more precisely, and by adding an emitter peaking capacitor C1 in parallel with these emitter resistors, the frequency characteristics of the bipolar logic gate can be controlled. Furthermore, various embodiments may be adopted, such as the specific configuration of the bipolar logic gate shown in FIGS. 1 and 3, the logic level of each signal, the polarity of the power supply voltage, and the conductivity type of the transistor.

In the above explanation, the invention made by the present inventor was mainly applied to bipolar logic gates installed in high-speed logic integrated circuit devices, which is the field of application in which the invention was made, but the invention is not limited to this. For example, the present invention can also be applied to similar bipolar logic gates mounted on general-purpose gate array integrated circuit devices and other various logic integrated circuit devices. The present invention can be widely applied to logic circuits including at least a current switch section and a pull-down transistor, and to digital integrated circuit devices equipped with such logic circuits.

[0019]

Effects of the Invention: The emitter resistor constituting the output emitter follower circuit of the NTL circuit is replaced with a pull-down transistor, and a first resistor is provided at the stage before the pull-down transistor, for example, between the ground potential of the circuit and the base of the pull-down transistor. a diode provided between the base of the pull-down transistor and the non-inverting output node of the current switch section; and a second diode provided between the base of the pull-down transistor and the output terminal of the circuit.
By providing a negative feedback bias circuit consisting of a resistor means, the pull-down transistor is connected to a diode which is essentially a current mirror when the input signal of the circuit is at a low level and the output signal is at a high level. When the input signal of the circuit is high level and the output signal is low level, it can be controlled through the second resistor means which becomes a negative feedback path, so many circuit elements are added. It is possible to realize a bipolar logic gate with an expanded operating margin, higher speed, and lower power consumption without having to do so. As a result, high-speed logic integrated circuit devices equipped with bipolar logic gates can be highly integrated, and at the same time, it is possible to promote higher speed and lower power consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of a bipolar logic gate to which the present invention is applied.

FIG. 2 is a signal waveform diagram showing one embodiment of the bipolar logic gate of FIG. 1;

FIG. 3 is a circuit diagram showing a second embodiment of a bipolar logic gate to which the present invention is applied.

FIG. 4 is a circuit diagram showing an example of a conventional NTL circuit.

FIG. 5 is a circuit diagram showing an example of a conventional SPL circuit.

[Explanation of symbols]

T1 to T5...NPN type bipolar transistor, D
1~D4...Diode, R1~R10...Resistor,
C1 to C3... Capacitors.

Claims (3)

[Claims] 1. A current switch section including an input transistor that receives an input signal at its base, and a current switch section that is provided between a first power supply voltage and an output terminal of the circuit and receives an inverted output signal of the current switch section at its base. an output transistor; a pull-down transistor provided between the output terminal of the circuit and a second power supply voltage; A logic circuit comprising: a bias circuit for supplying a voltage to a base of a transistor. 2. The bias circuit includes a first resistance means provided between a first power supply voltage and the base of the pull-down transistor, and a non-inverting output node of the current switch section and the base of the pull-down transistor. 2. The logic circuit according to claim 1, further comprising a diode provided between the pull-down transistor and the output terminal of the circuit. 3. The logic circuit according to claim 1, wherein the logic circuit is mounted on a high-speed logic integrated circuit device constituting a digital system.