JPH0534847B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a limiter circuit that limits the amplitude of a portion of an input signal that exceeds a predetermined level.

BACKGROUND TECHNOLOGY AND PROBLEMS For example, in order to remove small-level noise from a video signal, a circuit is known that reduces the noise by extracting the noise component from the video signal and adding it to the original video signal in reverse phase. It is being In this case, in order to effectively extract only that noise, signals above a certain level are suppressed by a limiter.

FIG. 1 shows an example of the conventional noise reduction circuit. In this example, a video signal SA (A in FIG. 3) is supplied to a high-pass filter 2 through an input terminal 1, and an output SB of this high-pass filter 2 (A in the same figure) is supplied to a high-pass filter 2 through an input terminal 1. B)
As a result, low-level noise mainly included in the high frequency range is obtained. In this case, the high-frequency component of the video signal is also obtained as it is as the output SB of the high-pass filter 2, but this is at a relatively high level compared to the noise component. The output signal SB of the high-pass filter 2 thus obtained is supplied via a capacitor 5 to the base of a transistor 3 providing a differential amplifier. The emitters of the transistors 3 and 4 are connected to each other through resistors 6 and 7, respectively, and the connection point between the resistors 6 and 7 is grounded through a constant current source 8 having a current value _I0 . Further, a bias voltage from a power supply 9 is supplied to the bases of the transistors 3 and 4 via resistors 10 and 11, respectively.

On the other hand, the video signal through the input terminal 1 is supplied to the base of the transistor 12. This transistor 12 has an emitter-follower configuration and serves as a so-called buffer amplifier, and its collector is connected to a power supply terminal 13. Further, the emitter of the transistor 12 is connected to the collector of the transistor 3 and the collector of the transistor 4 through resistors 14 and 15, respectively, and an output terminal 16 is led out from the connection point with the collector resistor 14 of the transistor 3.

In the above configuration, in principle, the output SB of the high-pass filter 2 is obtained in the opposite phase to the collector side of the transistor 3, while the video signal SA through the input terminal 1 appears in the same phase to the emitter side through the transistor 12. . Therefore, the output terminal 16
In this case, a composite signal of the two, that is, a signal in which noise components are subtracted and removed from the input video signal is obtained.

In this case, high-level signal components that are not noise appearing in the output of the high-pass filter 2 are limited in the following manner so that they are not included in the noise components subtracted from the video signal.

That is, as shown in FIG. 2, the current flowing through transistor 3 is I ₁ and the current flowing through transistor 4 is I _{2 .}
Then, the dynamic range of the differential amplifier is
The currents I ₁ and I ₂ are within the range in which they can change, and within this range, these transistors 3 and 4 operate; beyond this range, the differential amplifier consisting of transistors 3 and 4 operates as a so-called limiter. It turns out. Therefore, in the circuit shown in FIG. 1, the variation range of the currents I ₁ and I ₂ , and therefore the current value I ₀ of the current source 8, are appropriately selected, and a predetermined level V _L of the output SB of the high-pass filter 2 is selected. Signal components exceeding . In this way, only the noise component is added to the input video signal in reverse phase, and the output terminal 16 receives a video signal with well reduced noise.
SD (Figure 3D) is made available.

By the way, as mentioned above, this conventional noise reduction circuit uses a differential amplifier to mix the noise component obtained from the high-pass filter with the input signal passed through the transistor 12 on the collector side of the transistor 3 to cancel the noise. However, the gain of the noise component at that time can be expressed as follows.

That is, the noise gain G _N can be expressed as G _N =R/2R'+2r _e (1). Here, R is the value of resistors 14 and 15, R' is the value of resistors 6 and 7, and
r _e is the differential resistance of the transistor, which changes with current. As mentioned above, the limiter range is the dynamic range of the differential amplifier, so in order to change the limiter level, the dynamic range of this differential amplifier can be changed by changing the current value _I0 of the current source 8. However, when the current value I ₀ of this current source 8 is changed, the differential resistance of the emitter of the transistor changes as is clear from equation (1) above.
r _e changes depending on this current. For this reason, the noise gain G _N will fluctuate. In this case, the noise gain changes by changing the limiter range, making it impossible to obtain a stable and desired noise reduction effect. Furthermore, changing the current value I ₀ of the current source 8 means that the output terminal 1
This is not preferable because it changes the DC level of the signal obtained in step 6.

Purpose of the Invention In view of the above points, it is an object of the present invention to propose a limiter circuit in which the noise gain does not change even if the limiter level is changed when used in a noise reduction circuit as described above.

Summary of the Invention The present invention provides two input signals with different DC levels obtained by differentially controlling the DC level of the input signal and a reference slice level, and two slice levels, one of which is input to each input signal. The above objective is achieved by having a configuration in which a pair consisting of a signal and one slice level is received differentially, and the output is received by a differential amplifier in which a resistor is inserted between the emitters. be.

Embodiments Hereinafter, before explaining one example of the circuit of the invention with reference to the drawings, the circuit of the invention will be briefly explained.

For example, as shown in FIGS. 4 and 5, this inventive circuit has a reference voltage at each of the positive and negative inputs (the positive input is the base of transistors 22 and 31, and the negative input is the base of transistors 21 and 32). V _R and limiter level control voltage Vc are supplied, and the positive and negative outputs (the positive output is the collector of transistors 21 and 32, and the negative output is the collector of transistors 22 and 31) are connected to load resistors 24, 25, 34, The first to which one end of 35 is connected
and a second differential pair (the first differential pair is transistors 21 and 22, and the second differential pair is transistor 3)
1, 32), and the load resistor 24 connected to the positive output of the first differential pair 21, 22 and the other end of the load resistor 34 connected to the negative output of the second differential pair 31, 32. is connected, and the input signal is connected to the connection point (the input signal is terminal 8
1 is supplied. ) is supplied, and the load resistor 25 is connected to the negative output of the first differential pair 21, 22, and the other end of the load resistor 35 is connected to the positive output of the second differential pair 31, 32. are connected, the DC level of the input signal is supplied to the connection point (the DC level is supplied to the terminal 82), and the positive and negative outputs of the first differential pair 21 and 22 are supplied to the respective input sides. , the first and second buffers 41 and 42 whose output sides are commonly connected, and the positive and negative outputs of the second differential pair 31 and 32 are supplied to their respective input sides, and the third and second buffers whose output sides are commonly connected. 4 buffers 51, 52, a signal appearing at the common connection point of the first and second buffers 41, 42, and the third and fourth buffers 51,
The signals appearing at the 52 common connection points are respectively supplied to the input side, and an output signal corresponding to the above input signal sliced according to the limiter level control voltage Vc is obtained from between the respective output sides (see Fig. 5F). It has a third differential pair 61 and 62.

According to the circuit of this invention configured in this way,
The DC reference of the output signal is set based on the DC voltage of the input signal, and the DC reference level of the output signal is a constant voltage higher than the DC reference of the output signal (in the upper part of Figure 5 F).
2ΔV) and a level lower by the same voltage (in Figure 5 F,
An output signal is obtained that is vertically symmetrically limited by the lower 2ΔV). Therefore, if the present invention is used as a limiter circuit for extracting only noise in a noise reduction circuit, even if the current value _I0 is changed as in the conventional example explained with reference to FIG. does not change. Furthermore, the noise gain does not change even if the limiter range is changed.

Hereinafter, an example of the circuit of this invention will be explained with reference to FIGS. 4 and 5.

That is, FIG. 4 is a connection diagram of an example of the circuit of this invention, and FIG. 5 is a waveform diagram for explaining its operation.

In FIG. 4, transistors 21 and 22,
Transistors 31 and 62, transistors 41 and 42, transistors 51 and 52, and transistors 61 and 32 each have a differential configuration,
Reference numerals 23, 33, 43, 53, 63, and 64 are transistors constituting current sources of the transistors in the differential configuration. Transistor 2 which becomes these current sources
Constant current sources may be provided in place of 3, 33, 43, 53, 63 and 64.

The collectors of the transistors 21 and 22 are connected to load resistors 24 and 25, and the collectors of the transistors 31 and 32 are connected to a load resistor 3.
4 and 35 are connected. Outputs are taken out from the connection point between the collector of the transistor 21 and the resistor 24 and the connection point between the collector of the transistor 22 and the resistor 25, and are supplied to the bases of the transistors 41 and 42, respectively. On the other hand, outputs are derived from the connection point between the collector of the transistor 31 and the resistor 34 and the connection point between the collector of the transistor 32 and the resistor 35, and are supplied to the bases of the transistors 51 and 52, respectively. These transistors 41, 42 and transistors 51, 52
The collector and emitter of each are connected in common. The respective collector common connection points are connected to the power supply terminal 73, and outputs are derived from the respective emitter common connection points, and the respective outputs are supplied to the bases of the transistors 61 and 62 having a differential configuration. A resistor 65 is connected between the emitters of these transistors 61 and 62. Furthermore, diode-connected transistors 66 and 67 for current conversion are connected to the collector sides of these transistors 61 and 62. The collectors of these transistors 66 and 67 are connected in common, and their connection point is connected to a power supply terminal 73 via a resistor 68. Output terminals 71 and 72 are led out from connection points between the collectors of transistors 61 and 62 and the emitters of transistors 66 and 67, respectively.

For example, in the case of a noise reduction circuit as described above, 81 is an input terminal to which a noise signal component obtained through a high-pass filter is supplied, and 82 is an input terminal to which only the DC component of the noise signal component is supplied. . These input terminals 81 and 82 are connected to the bases of transistors 91 and 92.
The emitter of the transistor 91 is connected to the collector of the transistor 21 via the resistor 24, and the emitter of the transistor 91 is connected to the collector of the transistor 21 via the resistor 24.
are connected to the collector of the transistor 31 via the respective terminals. Further, the emitter of the transistor 92 is connected to the collector of the transistor 22 via the resistor 25 and to the collector of the transistor 32 via the resistor 35, respectively. Collectors of these transistors 91 and 92 are connected to power supply terminal 73.

Further, 83 is an input terminal to which a voltage Vc for controlling the limiter level is supplied. is applied to the base of On the other hand, 84 is the reference voltage value
This is an input terminal to which V _R is supplied, and the voltage V _R supplied from this input terminal is applied to the bases of the other transistor 22 and transistor 31 of the differential configuration, respectively.

In this example, the collector-emitter of the transistor 26 is connected in parallel with the collector-emitter of the transistor 22, and the collector-emitter of the transistor 36 is connected in parallel with the collector-emitter of the transistor 31. The bases of these transistors 26 and 36 are connected in common to the input terminal 83.
The voltage Vc obtained at

The operation of this circuit will be explained below.

First, consider the case where, for example, the value of the limiter level control voltage Vc is equal to the reference voltage _VR . At this time, assuming that the current values flowing through the current sources 23 and 33 are 2I ₁ , the resistors 24, 25, 34,
The value of the direct current flowing through 35 is all _I1 , which is the same. At this time, the potential on the collector side of the transistors 21, 22, 31, and 32 is set to _V1 . In this state, for example, when a sinusoidal signal as shown in FIG. 5A is supplied to the input terminal 81, the DC component of this signal is applied to the base of the transistor
transistor 21 since it is supplied through 2
As shown by the solid line in FIG. 5A, only the positive half cycle of this sine wave signal appears at the common emitter output of transistors 41 and 42 forming a differential amplifier which receive the collector outputs of transistors 41 and 22. Similarly, this positive half cycle of the signal appears at the common emitter output of transistors 51 and 52 forming a differential amplifier which similarly receives the collector outputs of transistors 31 and 32. Therefore, the two signals are canceled and do not appear at the collector outputs of the transistors 61 and 62 forming the differential amplifier receiving these emitter outputs, but are all canceled.

Next, if the limiter level control voltage supplied through terminal 83 is lowered by ΔV, then
The current flowing through the resistor 24 decreases by ΔI and becomes I ₁ −ΔI. Therefore, the potential on the collector side of this transistor 21 is V ₁ +R ₁ · when the value of the resistor 24 is R ₁ .
ΔI=V ₁ +ΔV. At this time, the potential of the collector of this transistor 21 and the differential transistor 22 becomes V ₁ -ΔV. Similarly, the potential on the collector side of the transistor 31 becomes V ₁ -ΔV, and the potential on the collector side of the transistor 32 becomes V ₁ +ΔV.

Therefore, the output on the collector side of the transistor 21 is as shown in FIG.
On the other hand, the output on the collector side of the transistor 31 has a DC potential of V ₁ -ΔV as shown in FIG _. 5D.

Then, the collector output of the transistor 22 becomes the DC voltage of the input signal itself set to V ₁ -ΔV, while the collector output of the transistor 31 becomes the DC voltage itself set to V ₁ +ΔV. The DC voltages that are the collector outputs of these transistors 22 and 32 serve as a slice level for the input signal, as will be described later.

As is clear from the above, transistors 21 and 2
The circuits 2, 31, and 32 differentially control the DC voltage of the input signal and the slice level thereof.

Therefore, in the differential transistors 41 and 42 receiving the collector outputs of the transistors 21 and 22, the input signal of the DC potential V ₁ +ΔV is sliced at the slice level V ₁ −ΔV, and the common emitter of these transistors 41 and 42 is sliced. The output includes the fifth
As shown by the solid line in Figure C, the slice level V ₁ −ΔV
DC potential V ₁ into which the lower signal components are sliced
An input signal of +ΔV can be obtained.

Further, in the differential transistors 51 and 52 receiving the collector outputs of the transistors 31 and 32, the input signal of the DC potential V ₁ −ΔV is similarly sliced at the slice level V ₁ +ΔV, and the output of the common emitter is As shown by the solid line in FIG. 5D, a signal component higher than V ₁ +ΔV is obtained.

Therefore, these outputs are connected to transistors 61 and 6.
2, in these transistors 61 and 62, as shown in FIG. _5E , the signal S ₂ as shown in FIG. It will be subtracted. and,
As is clear from FIG. 5E, the signal S ₂ corresponds to a signal component higher than the potential of the signal S ₁ that is 2ΔV higher than _the potential V ₁ +ΔV;
The result is that the AC component beyond 2ΔV is limited. As a result, an output is obtained at the output terminal 71 in which signal components at a level 2ΔV higher and 2ΔV lower than the DC potential of the input signal are limited (see Figure 5F). ). Note that a signal of the opposite phase is obtained at the output terminal 72.

In this way, according to the circuit shown in FIG. 4, by changing the control voltage Vc supplied from the input terminal 83 with respect to the reference voltage V _R , that is, by lowering the reference voltage V _R by ΔV, the voltage corresponding to that ΔV is generated. The portion of the signal exceeding 2ΔV is limited and obtained at output terminals 71 and 72.

In this case, transistors 61 and 62
What is compared is a signal with a DC potential V ₁ +ΔV as shown by the solid line in FIG. 5C, and a signal component higher than the potential V ₁ +ΔV as shown by the solid line in FIG. _5D . +ΔV is the control voltage for both signals
Even if Vc is changed, it is always kept equal, so the DC level of the outputs obtained at the output terminals 71 and 72 does not change.

In addition, in this example, the control voltage Vc
This is designed to prevent the outputs of the output terminals 71 and 72 from being inverted when the voltage becomes larger than the reference voltage. That is, the transistors 26 and 36 are the same, and the control voltage Vc is the reference voltage.
When V _R is exceeded, these transistors 26 and 36 are turned on, so that transistor 22
and 31 are turned off. Therefore, at this time, transistor 21 and transistor 26 are differentially connected, and transistor 32 and transistor 36 are differentially connected. At this time, both transistors 21 and 26
Since the base voltages of 32 and 36 are both equal to Vc, no signal component appears at the output terminals 71 and 72 as described above.

In addition, in the circuit shown in Figure 4, all transistors are NPN and have the same characteristics, so it is more stable when limiters are applied vertically symmetrically than when using a mixture of NPN and PNP transistors. It also has the effect of being limited. Furthermore, in this way, all transistors
The NPN configuration also has the advantage of being easy to integrate into an IC.

Application Example The above example was explained using a limiter circuit used to extract only the noise component of a noise reduction circuit of a video signal. It can be used not only as a circuit, but also in any general case where a limiter is applied to a signal in a vertically symmetrical manner.

Effects of the Invention As described above, according to the present invention, the DC level of an input signal and the reference slice level for this input signal are differentially controlled, and the pair of the differential input signal and slice level is controlled differentially. By adopting a configuration in which the differential output is received by a differential amplifier, the force signal is vertically symmetrical with a level that is a constant voltage higher than the DC voltage of this input signal and a level that is lower by the same voltage. A limited output signal is obtained. Moreover, even if the limiter level is changed, the potential (V ₁
+ΔV) is always equal for both signals, so the effect is that the DC level of the output signal does not vary. Therefore, if this inventive circuit is used as a limiter circuit for extracting only noise in a noise reduction circuit, the DC level of the output signal will remain unchanged even if the current value of the current source is changed as in the conventional example described in Fig. 1. does not change. Furthermore, the noise gain does not change even if the limiter range is changed.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of a conventional noise reduction circuit, Figure 2 is a diagram for explaining the dynamic range of a differential amplifier, and Figure 3 is a diagram for explaining the operation of the circuit in Figure 1. FIG. 4 is a connection diagram of an example of the circuit of the present invention, and FIG. 5 is a waveform diagram for explaining its operation. 21 and 22, 31 and 32, 41 and 42,
51 and 52, 61 and 62 are differentially connected transistors, 23, 33, 43, 53,
63, 64 are current sources, 71, 72 are output terminals, 8
1 is an input terminal for an input signal, 82 is an input terminal for only the DC voltage of the input signal, 83 is an input terminal for a limiter level control voltage, and 84 is an input terminal for a reference voltage.

Claims (1)

[Claims] 1. First and second differential pairs, each of which is supplied with a reference voltage and a limiter level control voltage to its positive and negative inputs, and whose positive and negative outputs are connected to one end of a load resistor, respectively. and the load resistor connected to the positive output of the first differential pair and the other end of the load resistor connected to the negative output of the second differential pair are connected, and a connection point thereof is formed. An input signal is supplied to the load resistor, and the load resistor connected to the negative output of the first differential pair and the other end of the load resistor connected to the positive output of the second differential pair are connected. first and second buffers, the DC level of the input signal is supplied to the connection point, the positive and negative outputs of the first differential pair are supplied to the respective input sides, and the output sides are commonly connected; The positive and negative outputs of the second differential pair are supplied to their respective input sides, and the output sides are commonly connected to third and fourth buffers, and a signal appearing at the common connection point of the first and second buffers. A signal appearing at the common connection point of the third and fourth buffers is supplied to the input side, respectively, and an output signal corresponding to the input signal sliced according to the limiter level control voltage is obtained from between the respective output sides. A limiter circuit having a third differential pair.