JPH0231894B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a comparator that shapes an alternating current signal to obtain a digital signal.

Conventional configuration and its problems A comparator can obtain a digital signal that changes state according to the difference in voltage by comparing the voltages applied to two input terminals. Widely used in waveform shaping circuits, etc. When a comparator is used in the waveform shaping circuit, small high-frequency noise contained in the alternating current signal generates whisker-like noise pulses at the rising or falling points of the output signal. Conventionally, in order to prevent malfunctions caused by such noise, the output state of the comparator is fed back to the input to provide hysteresis in the input/output characteristics.

In conventional comparators with hysteresis, the output state is positively fed back to one of the differential inputs, so the voltage (or current) on the fed back input side changes abruptly in steps, causing the AC signal input to change rapidly. The effect also appears on the AC signal itself, causing distortion or step-like changes in the AC signal itself (a voltage change occurs that is the product of the step-like change in input current and the signal source impedance). Therefore, it has been difficult to directly use the AC signal for other purposes.

In addition, when converting an AC signal for speed detection into a digital signal and using it in a device that controls a motor by obtaining a voltage corresponding to the period, it is possible to accurately detect the zero-cross point of the AC signal and convert it into a digital signal. Need to convert. It is natural that noise components contained in the AC signal are required to prevent malfunctions, but in order to increase the number of detected pulses as much as possible, it is necessary to It has been desired to obtain a digital signal that accurately corresponds to the negative-to-positive zero-cross.

When using two comparators for this purpose, it is necessary to install a buffer amplifier on each input side in order to avoid mutual interference due to distortion of the AC signal, resulting in a very complicated configuration. I was getting used to it.

Purpose of the Invention In consideration of the above points, the present invention provides a comparator that can accurately detect zero-cross points of both input AC signals and obtain a digital signal with a very simple configuration. It is intended to.

Configuration of the Invention In order to achieve the above object, the present invention has the following features:
current source means for outputting second and third constant currents; differential comparison means having a pair of differential transistors for differentially distributing the first constant current according to an input voltage; The input side is connected to the output side of one differential transistor of the dynamic comparison means, and the second
a first current mirror means whose output side is connected to the output side of the constant current of the first current mirror means; a first current amplification means whose input side is connected to the output side of the first current mirror means; a first feedback means for supplying a current to the input side of the first current amplification means or the input side of the first current mirror means according to the output current of the current amplification means; a first output means for obtaining a first digital signal that changes in conjunction with the output current; and an input side connected to the output side of the other differential transistor of the differential comparison means; a second current mirror means whose output side is connected to the output side; a second current amplification means whose output side is connected to the output side of the second current mirror means; and an output current of the second current amplification means. a second feedback means for supplying a current to the input side of the second current amplification means or the input side of the second current mirror means in response to the change in output current of the second current amplification means; and second output means for obtaining a second digital signal.

DESCRIPTION OF EMBODIMENTS The present invention will be described below based on illustrated embodiments. FIG. 1 is an electric circuit diagram showing one embodiment of the present invention, which will be explained with reference to the waveform diagram for explaining the operation of FIG. 2. The differential comparator 1 has emitter resistors 23 and 24 of a pair of differential transistors 21 and 22, is supplied with the current _I0 of the first constant current source 25 of the current source 2 as a common emitter current, and has an input The current I ₀ is distributed to the collector side according to the voltage vi (Fig. 2 a, b). The input side of the first current mirror section 3 is connected to the collector side of the differential transistor 21, and the output side of the second constant current source 26 of the current source section 2 is connected to the output side of the first current mirror section 3. has been done. The values of the resistors 31 and 32 of the first current mirror section 3 are 2r:r, and the transistors 28 and 2
The emitter area ratio of No. 9 is 1/2r:1/r=1:2, and the current gain is doubled. Therefore, when current i ₁ becomes smaller than I ₀ /2, the difference current
I ₀ −2i ₁ is the transistor 33 of the first current amplifying section 4
(Part of it becomes the base current of the transistor 39). The amplified current i ₃ of the transistor 33 becomes the input current of the first feedback section 5. The first feedback section 5 is composed of a current mirror consisting of transistors 37 and 38, and is responsive (proportional) to _i3 .
The generated current i ₄ is positively fed back to the input side of the first current amplifying section 4 (loop gain is greater than 1). As a result, at the moment i ₁ <I ₀ /2, i ₃ and i ₄ change stepwise (Fig. 2c). The resistor 34 and diodes 35 and 36 of the first current amplifying section 4 are used to control the output current.
It is provided to limit the maximum value of i ₃ . The transistor 39 of the first output section 6 operates in conjunction with the transistor 33 of the first current amplification section 4, so that the current i ₅ becomes i ₃
is proportional to. Therefore, the transistor 41 is turned on and the output _v1 becomes zero (FIG. 2d). The above state continues as long as vi is positive.

When vi becomes negative, the collector current i ₁ of the differential transistor 21 becomes i ₁ >I ₀ /2. Since the output current i ₄ of the first feedback section 5 is maintained at a predetermined value by the positive feedback operation described above, the moment 2i ₁ −I ₀ >i ₄ (point A in FIG. 2) ), the base current of the transistor 33 of the first current amplifying section 4 becomes zero, and its output current _i3 also becomes zero. When i ₃ becomes zero, the output current i ₄ of the first feedback section 5 also becomes zero (positive feedback operation).
Further, the output current i ₅ of the transistor 39 of the first output section 6 also becomes zero, the transistor 41 is turned off, and the output v ₁ becomes large. After that, the above operation is repeated as vi changes.

On the other hand, the input side of the second current mirror section 7 is connected to the collector side of the differential transistor 22 of the differential comparison section 1, and the third current source section 2 of the current source section 2 is connected to the output side of the second current mirror section 7. The output side of constant current source 27 is connected. The values of the resistors 54 and 55 of the second current mirror section 7 are 2r:r, and the emitter area ratio of the transistors 51 and 52 is 1/2r:1/r.
=1:2, and the current gain is doubled. Therefore, when the current i ₂ becomes smaller than I ₀ /2, the difference current I ₀ -2i ₂ becomes the base current of the transistor 56 of the second current amplifying section 8 (a part becomes the base current of the transistor 62). ). transistor 5
The amplified current i ₆ of 6 becomes the input current of the second feedback section 9. The second feedback section 9 is constituted by a current mirror consisting of transistors 60 and 61, and positively feeds back the current i ₇ responsive (proportional) to i ₆ to the input side of the second current amplification section 8 ( loop gain is greater than 1). As a result, i ₆ and i ₇ change stepwise at the moment i ₂ <I ₀ /2 (Fig. 2e). Second
The resistor 57 and diodes 58, 5 of the current amplifying section 8
9 is provided to limit the output current _i6 . The transistor 62 of the second output section 10 operates in conjunction with the transistor 56 of the second current amplification section 8,
Current i ₈ is proportional to i ₆ . Therefore, the transistor 64 is turned on and the output V ₂ becomes zero (second
Figure f). The above state continues as long as vi is negative.

When vi becomes positive, the collector current i ₂ of the differential transistor 22 becomes i ₂ >I ₀ /2. Since the output current i ₇ of the second feedback section 9 is maintained at _a predetermined value by _the above _- mentioned positive feedback operation, the second current amplification section 8 transistors 56
The base current of becomes zero, and i ₆ , i ₇ and i ₈ become zero (positive feedback operation). Therefore, the second output section 10
transistor 64 is turned off, and the output V ₂ increases. After that, the above operation is repeated as vi changes.

The transistor 70 of the combining section 11 is the first output
The transistor 71 is turned on and off in response to V ₁ , and the transistor 71 is turned on and off in response to the second output V ₂ . Therefore, when both V ₁ and V ₂ become zero (hysteresis section), the output V ₃ of the combining section 11 becomes large. As a result, a pulse signal with a time width corresponding to the hysteresis width can be obtained from the zero-cross point of the input signal vi. The frequency of V ₃ is twice the frequency of vi (the frequencies of V ₁ and V ₂ ), and its period is equal to the interval between zero-crossing points of vi.

The relationship between the input voltage vi and the first output V ₁ or the second output V ₂ in the embodiment shown in FIG. 1 has hysteresis characteristics with opposite polarity as shown in FIG. 3 a or b, respectively. ing. That is, when vi increases from a large negative value, V ₁ changes from a positive value (base-emitter voltage V _BE of transistor 70) to zero at vi=0, and when vi decreases from positive, When vi reaches a predetermined negative value
V ₁ changes from zero to a positive value (V _BE ) (Figure 3a). Also, when vi decreases from a large positive value, V ₂ changes from a positive value (base-emitter voltage V _BE of transistor 71) to zero at vi=0, and when vi increases from a negative value, When vi reaches a predetermined positive value (V _BE ), V ₂ changes from zero to a positive value (V _BE ) (FIG. 3b). This results in
It is no longer affected by high frequency noise mixed into the AC signal vi.

In addition, in the comparator of this embodiment, the first current amplifying section 4 and the first feedback section 5 equivalently
_The input signal _vi
and mutual influence on the signals V ₁ and V ₂ does not occur.

FIG. 4 shows an electric circuit diagram representing another embodiment of the present invention. In this embodiment, the resistors 23 and 24 of the differential comparator 1 in the embodiment of FIG. 1 are omitted, and the first
The current mirror unit 3 and the second current mirror unit 7 are simply current mirrors with a gain of 1, and the values of the second constant current source 26 and the third constant current source 27 of the current source unit 2 are set to the first constant current source 26 and the third constant current source 27 of the current source unit 2. Constant current source 25 value I ₀ 2
It is 1/1.

Furthermore, in this embodiment, the output sections 6 and 10 in the embodiment of FIG. 1 are simplified to reduce the number of elements. That is, the emitter side of the current mirror of the first feedback section 5 is connected to the base of the transistor 41, and the transistor 4 is connected by the current (i ₃ +i ₄ ).
1 is turned on and off. Further, the emitter side of the current mirror of the second feedback section 9 is connected to the base of the transistor 64, and the transistor 64 is turned on and off by the current (i ₆ +i ₇ ).

Further, a resistor 101 is connected to the emitter of the transistor 38 of the first feedback section 5 to reduce the maximum value of i ₄ . That is, the emitter resistor 101
If the value of is R ₁₀₁ , the currents i ₃ and i ₄ are (kT/q)ln(i ₃ /i ₄ )=R ₁₀₁・i ₄ ...(1) where k: Boltzmann's constant, q: electron's Amount of electric charge, T: Absolute temperature. Its characteristics have saturation characteristics as shown in Figure 5, and when i ₃ is small, i ₄ and
i ₃ is proportional or approximately proportional, and as i ₃ increases, i ₄ approaches a predetermined value or approximately a predetermined value.

In this way, if the first feedback section 5 is provided with saturation characteristics, the limit value of the output current i ₃ of the first current amplification section 4 (depending on the resistor 34 and the diodes 35 and 36)
Despite the variation in , the value of i ₄ hardly changes (Figure 5). As a result, the input signal vi was converted to
The variation in the hysteresis width of V ₁ is also reduced.
Further, a resistor 102 is also connected to the emitter side of the transistor 61 of the second feedback section 9, and by providing a saturation characteristic in the relationship between i ₆ and i ₇ , variations in the hysteresis width of V ₂ are also reduced.

The configuration of other parts and the overall operation are as follows:
This is the same as the embodiment shown in the figure, and the explanation will be omitted.

FIG. 6 shows an electric circuit diagram representing still another embodiment of the present invention. In this embodiment, the transistor 37 of the first feedback section 5 and the transistor 41 of the first output section 6 in the embodiment of FIG. 4 are replaced with one transistor 103. That is, in the first feedback section 5, current i ₃ produces i ₄ and i ₉ . The relationship is approximately (kT/q)ln(i ₃ +i ₉ /i ₄ )=R ₁₀₁・i ₄ ...(2). Also, the transistor 6 of the second feedback section 9
0 and the transistor 64 of the second output section 10 are also replaced with one transistor 104.

In each of the above-described embodiments, the current amplifying sections 4 and 8 are configured by transistors whose emitters are grounded, but the present invention is not limited to such a case, and various other configurations are possible. FIG. 7 shows an electrical circuit diagram of still another embodiment of the present invention. In this embodiment, the first current amplification section 4 is replaced by a transistor 111,
Consisting of a current mirror circuit consisting of 112,
The output current i ₃ is amplified by the transistor 115 of the first feedback section 5 to output a current i ₄ , which is positively fed back to the input side of the first current amplification section 4 . The maximum value of the output current i ₄ of the first feedback section 5 is limited by the resistor 116, the diode 113 and the transistor 114. Further, the output current i ₃ of the first current amplifying section 4 becomes the base current of the transistor 114, and changes the output V ₁ digitally. Further, the configurations of the second current amplifying section 8 and the second feedback section 9 are also similar.

FIG. 8 shows an electric circuit diagram representing still another embodiment of the present invention. In this embodiment, transistors 151 and 152 are provided in the first feedback section 5 of the embodiment shown in FIG.
Add a current mirror consisting of and its output current
i ₄ is fed back to the input side of the first current mirror section 3, and the first current amplifying section 4, the first feedback section 5, and the first
A positive feedback loop is formed by the current mirror section 3, and equivalent hysteresis is provided. Further, the second feedback section 9 also includes the transistor 153.
By adding a current mirror _consisting of A positive feedback loop is formed by the current mirror section 7, and hysteresis is equivalently provided.

The operation of the comparator in this embodiment is similar to that in the embodiment shown in FIG.
The characteristics of the output V ₁ and the second output V ₂ have hysteresis characteristics as shown in FIGS. 3a and 3b.

Note that various well-known configurations can be used for the configurations of each part of the above-described embodiments. Furthermore, the configurations of the first and second current amplification sections, the first and second feedback sections, and the first and second output sections do not necessarily have to be the same. Furthermore, it is extremely easy to integrate the comparator of the present invention on a single silicon chip.

Effects of the Invention As understood from the above explanation, the comparator of the present invention realizes a comparator that accurately detects the zero-cross points of both input AC signals and obtains a digital signal, although it has a simple configuration. It is. Therefore, if a circuit for waveform shaping an AC signal for speed detection is constructed based on the present invention,
Accurate speed information with a large number of pulses can be obtained.

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram showing an embodiment of the present invention, FIGS. 2 a to g are waveform diagrams for explaining operation, FIGS. 3 a and b are input/output characteristic diagrams showing hysteresis characteristics, and FIG. 4 is an electric circuit diagram showing another embodiment of the present invention, FIG. 5 is a diagram showing the characteristics of the first feedback section in FIG. 4, and FIGS. FIG. 6 is an electrical circuit diagram showing another embodiment. DESCRIPTION OF SYMBOLS 1...Differential comparison section, 2...Current source section, 3...First current mirror means, 4...First current amplification section, 5...First feedback section, 6...First current mirror means output section,
7...Second current mirror section, 8...Second current amplification section, 9...Second feedback section, 10...Second output section, 11...Composition section.

Claims (1)

[Claims] 1. Current source means that outputs first, second, and third constant currents, and a set of differential transistors that differentially distributes the first constant current according to input voltage. a differential comparison means having an input side connected to the output side of one of the differential transistors of the differential comparison means,
a first current mirror means whose output side is connected to the output side of the second constant current; and a first current mirror means whose input side is connected to the output side of the first current mirror means.
and a first feedback means for supplying a current to the input side of the first current amplification means or the input side of the first current mirror means according to the output current of the first current amplification means. and a first current that changes in conjunction with the output current of the first current amplification means.
a first output means for obtaining a digital signal; and a first output means whose input side is connected to the output side of the other differential transistor of the differential comparison means, and whose output side is connected to the output side of the third constant current. a second current amplifying means whose input side is connected to the output side of the second current mirror means; and a second current amplifying means having an input side connected to the output side of the second current mirror means; a second feedback means for supplying a current to the input side of the amplification means or the input side of the second current mirror means; and a second digital signal that changes in conjunction with the output current of the second current amplification means. and a second output means for obtaining. 2. Claim 1, comprising a synthesizing means for synthesizing a third digital signal of twice the frequency from the first digital signal of the first output means and the second digital signal of the second output means. Comparator listed. 3. Claims 1 and 2, characterized in that the first or second feedback means has a saturation characteristic in the relationship between the input current and the output current, and the maximum value of the output current is limited. Comparator described in section.