JPH0738208A - Semiconductor laser device - Google Patents
Semiconductor laser deviceInfo
- Publication number
- JPH0738208A JPH0738208A JP5201863A JP20186393A JPH0738208A JP H0738208 A JPH0738208 A JP H0738208A JP 5201863 A JP5201863 A JP 5201863A JP 20186393 A JP20186393 A JP 20186393A JP H0738208 A JPH0738208 A JP H0738208A
- Authority
- JP
- Japan
- Prior art keywords
- submount
- solder
- pellet
- semiconductor laser
- laser device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、光情報処理・光通信等
の用途に用いられる半導体レーザ装置に関し、特にレー
ザダイオード・ペレットの搭載されるサブマウントの構
造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor laser device used for applications such as optical information processing and optical communication, and more particularly to the structure of a submount on which a laser diode pellet is mounted.
【０００２】[0002]
【従来の技術】半導体レーザ装置は、ステム上にレーザ
ダイオード・ペレット（以下、ＬＤペレットと記す）お
よびレーザ光出力をモニタするためのホトディテクタ・
ペレットとを搭載し、キャップにて封止して構成したも
のである。この際、ステムとＬＤペレットとの熱膨張係
数の差を吸収するため、並びに、量産性向上のために、
ＬＤペレットは、通常ＬＤペレットと近い熱膨張係数を
もちかつ熱伝導率の高い材料からなるサブマウントを介
してステムにマウントされる。2. Description of the Related Art A semiconductor laser device includes a laser diode pellet (hereinafter referred to as LD pellet) on a stem and a photodetector for monitoring laser light output.
It is configured by mounting a pellet and sealing with a cap. At this time, in order to absorb the difference in coefficient of thermal expansion between the stem and the LD pellet and to improve mass productivity,
The LD pellet is usually mounted on the stem through a submount made of a material having a thermal expansion coefficient close to that of the LD pellet and a high thermal conductivity.
【０００３】図８（ａ）は、従来のＬＤペレットの搭載
構造を示す正面図である。同図に示されるように、Ｓｉ
サブマウント２上にはＴｉＰｔ電極３が形成され、その
上にはさらにＡｕＳｎソルダ４が蒸着されている。Ｓｉ
サブマウント２は、ＰｂＳｎソルダ６を介してステム・
ポール７上に固着され、ＬＤペレット１は、ジャンクシ
ョンダウンの状態でＳｉサブマウント２上にＡｕＳｎソ
ルダ４を介して搭載される。FIG. 8A is a front view showing a conventional LD pellet mounting structure. As shown in FIG.
A TiPt electrode 3 is formed on the submount 2, and an AuSn solder 4 is further vapor-deposited thereon. Si
The submount 2 is connected to the stem via the PbSn solder 6.
The LD pellet 1 is fixed on the pole 7 and mounted on the Si submount 2 via the AuSn solder 4 in a junction-down state.
【０００４】上述した従来例で問題となるのは、第１
に、サブマウントをＳｉウェハから切り出す際に、ソル
ダが電極面から剥がれやすいことであり、第２に、ＬＤ
ペレットをサブマウントに装着（融着）するために用い
られるソルダ材が、図８（ｂ）に示すように、融着時に
ペレット前方にはみ出してソルダボール４ｂを形成し、
ＬＤペレットから出射される光を妨げやすいことであ
る。ソルダ剥がれを防止しはみ出すソルダ量を少なくす
るために融着材の厚さを薄くすると、十分な接着性を確
保することができなくなり、信頼性が低下する。そこ
で、従来のサブマウントの場合、図９に示すように、Ａ
ｕＳｎソルダ４をサブマウントの縁から後退したパター
ンに蒸着することが行われてきた。The problem with the above-mentioned conventional example is that
Secondly, when the submount is cut out from the Si wafer, the solder is easily peeled off from the electrode surface. Secondly, the LD
As shown in FIG. 8 (b), the solder material used for mounting (fusing) the pellet on the submount protrudes to the front of the pellet during fusion to form a solder ball 4b,
That is, it is easy to block the light emitted from the LD pellet. If the thickness of the fusing material is reduced in order to prevent the solder from peeling and to reduce the amount of solder that protrudes, it becomes impossible to secure sufficient adhesiveness and the reliability decreases. Therefore, in the case of the conventional submount, as shown in FIG.
It has been practiced to deposit uSn solder 4 in a pattern recessed from the edge of the submount.
【０００５】ＬＤペレット側面へのソルダの盛り上がり
を防止するためのサブマウント構造として、特開昭６１
−１８１９０号公報には図１０に示すもの提案されてい
る。同図に示されるように、Ｓｉサブマウント２の表面
にはＶ字形の溝８が形成されており、その表面には、Ｃ
ｒ、Ｎｉ−Ｃｒ、Ｎｉからなる下地金属層３ａが形成さ
れ、その上にはＳｎ等からなるソルダ４ｃが蒸着されて
いる。このサブマウント構造では、ＬＤペレットの融着
時にはソルダ材は溝８に流れ込むように流動するので、
ソルダの盛り上がりやソルダボールの発生は防止され
る。As a submount structure for preventing the swelling of the solder on the side surface of the LD pellet, Japanese Patent Application Laid-Open No. Sho 61-61 is known.
Japanese Patent Laid-Open No. 18190 proposes that shown in FIG. As shown in the figure, a V-shaped groove 8 is formed on the surface of the Si submount 2, and a C-shaped groove 8 is formed on the surface.
A base metal layer 3a made of r, Ni-Cr, Ni is formed, and a solder 4c made of Sn or the like is vapor-deposited thereon. In this submount structure, since the solder material flows so as to flow into the groove 8 when the LD pellets are fused,
The rise of solder and the generation of solder balls are prevented.
【０００６】[0006]
【発明が解決しようとする課題】図９に示す従来例で
は、サブマウント製造時にサブマウントの端から融着材
までの距離Ｌを正確に制御しなければならない。この距
離が小さすぎるとソルダボールができやすくなり、大き
すぎると融着後にサブマウントの端までソルダが行きわ
たらずレーザの放熱性が悪化することになるからであ
る。そのため、この従来例では、製作するのに調整等に
余分の人手がかかり、歩留まりが低下することになりや
すい。また、図１０に示したサブマウントの場合、サブ
マウントとＬＤペレットとの接触面積が小さく、放熱性
が悪化するという問題があった。さらに、サブマウント
をウェハのダイシングによって切り出すとき、ソルダ４
が溝に沿って剥がれやすいという問題があった。In the conventional example shown in FIG. 9, the distance L from the end of the submount to the fusion material must be accurately controlled when manufacturing the submount. This is because if the distance is too small, solder balls are likely to be formed, and if it is too large, the solder does not reach the end of the submount after fusion and the heat dissipation of the laser deteriorates. Therefore, in this conventional example, extra manpower is required for adjustment and the like for manufacturing, and the yield is likely to be reduced. Further, in the case of the submount shown in FIG. 10, there is a problem that the contact area between the submount and the LD pellet is small and the heat dissipation is deteriorated. Furthermore, when cutting the submount by dicing the wafer, the solder 4
However, there was a problem that it was easily peeled off along the groove.
【０００７】したがって、この発明の目的とするところ
は、上記の問題点に鑑み、製作に当たってサブマウント
上のソルダの位置を正確に制御する必要がなく、ダイシ
ング時にソルダ剥がれが生じにくく、かつ良好な放熱性
も有するサブマウントを提供することにある。Therefore, in view of the above-mentioned problems, the object of the present invention is that it is not necessary to accurately control the position of the solder on the submount in the manufacturing process, and the solder peeling is unlikely to occur during dicing, and the soldering is excellent. It is to provide a submount that also has heat dissipation.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するた
め、本発明によれば、表面に金属層（３）が形成された
サブマウント（２）と、該サブマウント上にろう材
（４）を介して搭載されたＬＤペレット（１）と、を備
える半導体レーザ装置において、前記サブマウント
（２）の前記ＬＤペレットの搭載部の少なくとも一部は
凹凸に加工されており、その凸部（３）はその頂部が平
坦になされておりかつＬＤペレットの寸法より十分細か
いピッチでマトリックス状に配列されていることを特徴
とする半導体レーザ装置が提供される。In order to achieve the above object, according to the present invention, a submount (2) having a metal layer (3) formed on the surface thereof and a brazing material (4) on the submount. In the semiconductor laser device including the LD pellet (1) mounted via the LD pellet (1), at least a part of the LD pellet mounting portion of the submount (2) is processed to be uneven, and the convex portion (3 ) Has a flat top portion and is arranged in a matrix with a pitch sufficiently smaller than the size of the LD pellet.
【０００９】[0009]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。図１は、本発明の第１の実施例のＳｉサブ
マウントにＬＤペレットを搭載するときの状態を示す斜
視図である。同図に示されるように、Ｓｉサブマウント
２の表面には、ＴｉＰｔ電極３とＡｕＳｎソルダ４が設
けられるが、ここでＳｉ基板表面は凹凸に加工されてお
り、それに倣ってソルダ４にも突起部４ａが形成されて
いる。このように構成されたＳｉサブマウント２では、
ＬＤペレット１の融着時にソルダ４はサブマウント表面
の凹部に沿って流れるため、ソルダボールの形成は抑制
される。Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a perspective view showing a state where an LD pellet is mounted on a Si submount according to the first embodiment of the present invention. As shown in the figure, a TiPt electrode 3 and an AuSn solder 4 are provided on the surface of the Si submount 2. Here, the surface of the Si substrate is processed to have unevenness, and the solder 4 also has protrusions. The portion 4a is formed. In the Si submount 2 configured in this way,
Since the solder 4 flows along the recesses on the surface of the submount when the LD pellets 1 are fused, the formation of solder balls is suppressed.
【００１０】次に、図２（ａ）〜（ｃ）を参照して第１
の実施例のサブマウントの製造方法について説明する。
まず、フォトリソグラフィ技術およびドライエッチング
工程によりＳｉウェハ表面を加工して、図２（ａ）に示
すように、突起部２ａを形成する。ここで、突起部２ａ
の高さを４μｍ、その平面寸法を１０μｍ×１０μｍと
し、凹部の幅を１０μｍとする。Next, referring to FIGS. 2A to 2C, the first
A method of manufacturing the submount according to the embodiment will be described.
First, the surface of the Si wafer is processed by the photolithography technique and the dry etching process to form the protrusion 2a as shown in FIG. Here, the protrusion 2a
Has a height of 4 μm, a plane size of 10 μm × 10 μm, and a width of the recess of 10 μm.
【００１１】その上に、ＴｉとＰｔとをそれぞれ膜厚１
０００Åに蒸着してＴｉＰｔ電極３を形成する。さらに
その上に、Ａｕを４０００Åの厚さに、続いてＡｕＳｎ
ソルダ４を３μｍの厚さに蒸着する。このとき、ソルダ
面には突起部４ａが形成される〔図２（ｂ）〕。次に、
ウェハを切断部５に沿ってフルダイシングして、個々の
サブマウントに分離する〔図２（ｃ）〕。On top of that, Ti and Pt are each formed to a film thickness of 1
The TiPt electrode 3 is formed by vapor deposition at 000Å. On top of that, add Au to a thickness of 4000Å, then AuSn.
The solder 4 is vapor-deposited to a thickness of 3 μm. At this time, the protrusion 4a is formed on the solder surface [FIG. 2 (b)]. next,
The wafer is subjected to full dicing along the cutting portion 5 to separate it into individual submounts (FIG. 2C).
【００１２】このフルダイシング工程において、サブマ
ウントの凹部に形成されたソルダ４は、網目状に電極上
に被着しているため剥離されにくくなっている。突起部
４ａのＡｕＳｎソルダ４については、ダイシング部分に
かかった部分が剥がれることがあるが、図２（ｃ）に示
されるように、突起部の端部でソルダ膜が薄くなってい
るために、剥離はここで止まる。すなわち、突起の寸法
が１０μｍ×１０μｍであることにより、剥離は、サブ
マウントの縁からせいぜい１０μｍ中に入ったところま
でであり、実用上無視できる。In this full dicing process, the solder 4 formed in the concave portion of the submount is attached to the electrodes in a mesh shape, and therefore is not easily peeled off. With respect to the AuSn solder 4 of the protrusion 4a, the portion applied to the dicing portion may be peeled off, but as shown in FIG. 2C, the solder film is thin at the end of the protrusion, Peeling stops here. That is, since the dimension of the protrusion is 10 μm × 10 μm, the peeling is from the edge of the submount to the place where it enters at most 10 μm, which can be ignored in practice.
【００１３】半導体ＬＤペレット１のサブマウントへの
融着は、従来と同様にＮ2 雰囲気中で３００℃に加熱す
ることにより行う。融着後の状態を正面図にて図３に示
す。この融着時にＬＤペレット１下の余分のＡｕＳｎソ
ルダ４はサブマウントの凹部を埋めるように流動するの
で、ソルダによるボールは生じない。ＬＤペレットをサ
ブマウントに融着するにあたり、ＬＤペレットをサブマ
ウントの端から１５μｍ出っ張らせてマウントする場
合、ソルダボールの発生率を従来のサブマウント（図９
に示されたもの）と本発明のサブマウントで比較する
と、従来のサブマウントで、ＡｕＳｎソルダがサブマウ
ントの縁から１０μｍ後退して蒸着されている場合、ソ
ルダボールの発生率は５％であったのに対し、本実施例
のサブマウントでは０％であった。また、ＬＤペレット
とサブマウントとは面接触にて密着するため、放熱性は
良好である。The fusion of the semiconductor LD pellets 1 to the submount is performed by heating to 300 ° C. in an N 2 atmosphere as in the conventional case. The state after fusion is shown in FIG. 3 in a front view. At the time of this fusion, the extra AuSn solder 4 under the LD pellet 1 flows so as to fill the concave portion of the submount, so that balls due to the solder do not occur. When fusing the LD pellets to the submount so that the LD pellets are protruded by 15 μm from the end of the submount, the solder ball generation rate is the same as that of the conventional submount (see FIG. 9).
When the AuSn solder is deposited 10 μm back from the edge of the submount in the conventional submount, the generation rate of solder balls is 5%. On the other hand, it was 0% for the submount of this example. Further, since the LD pellet and the submount are in close contact with each other by surface contact, heat dissipation is good.
【００１４】図４は、本発明の第２の実施例において用
いられるサブマウントの平面図である。この実施例では
突起部２ｂは、円柱状に形成されている。本実施例にお
いて、円柱の高さは３．５μｍ、直径は１０μｍであ
る。また、突起部２ｂのピッチは２０μｍである。この
実施例によっても先の実施例の場合と同様の効果を享受
することができる。FIG. 4 is a plan view of a submount used in the second embodiment of the present invention. In this embodiment, the protrusion 2b is formed in a cylindrical shape. In this embodiment, the height of the cylinder is 3.5 μm and the diameter is 10 μm. The pitch of the protrusions 2b is 20 μm. Also in this embodiment, the same effect as in the previous embodiment can be obtained.
【００１５】図５は、本発明の第３の実施例を説明する
ためのＳｉサブマウントの斜視図である。このサブマウ
ント２では、突起部２ａ（４ａ）はＬＤペレットがマウ
ントされる部分のみに形成されまたＡｕＳｎソルダ４も
その近傍のみにパターン蒸着されている。これにより、
ＡｕＳｎソルダの溶融度のばらつきによるレーザ光のモ
ニター用ホト・ディテクタ側への光量のばらつきを低減
することができる。FIG. 5 is a perspective view of a Si submount for explaining a third embodiment of the present invention. In this submount 2, the protrusion 2a (4a) is formed only in the portion where the LD pellet is mounted, and the AuSn solder 4 is also pattern-deposited only in the vicinity thereof. This allows
It is possible to reduce the variation in the amount of laser light on the photo detector side for monitoring due to the variation in the melting degree of the AuSn solder.
【００１６】図６は、本発明の第４の実施例を説明する
ための、ウェハのダイシング前の状態を示す斜視図であ
る。この実施例におけるサブマウントでは、突起部４ａ
はダイシングされる切断部に沿った部分のみであり、サ
ブマウントの中央部は平坦になされている。そして、Ｌ
Ｄペレットは一部中央の平坦部にかけてマウントされ
る。これにより、ＬＤペレットと電極面との密着する面
積がより広がり、放熱性の向上を図ることができる。こ
こで、凸凹面の領域の幅を５０μｍ程度とすれば、ダイ
シング時に余分の調整等を行う必要はない。FIG. 6 is a perspective view showing a state before dicing of a wafer for explaining a fourth embodiment of the present invention. In the submount in this embodiment, the protrusion 4a
Is only along the cut portion to be diced, and the central portion of the submount is flat. And L
Part of the D pellet is mounted over the flat part in the center. Thereby, the area in which the LD pellet and the electrode surface are in close contact with each other is further expanded, and the heat dissipation can be improved. Here, if the width of the area of the uneven surface is set to about 50 μm, it is not necessary to perform extra adjustment or the like during dicing.
【００１７】図７は、本発明の第５の実施例を説明する
ための、ウェハのダイシング前の状態を示す斜視図であ
る。この実施例では、切断部５は突起部４ａの行、列に
対し斜めに交わるように設定されている。本実施例によ
れば、フルダイシング時に、ダイサーの刃がＡｕＳｎソ
ルダ４層に対して斜めに当たるため、ソルダの剥離はよ
り抑制される。FIG. 7 is a perspective view showing a state before dicing of a wafer for explaining a fifth embodiment of the present invention. In this embodiment, the cutting portions 5 are set so as to obliquely intersect the rows and columns of the protrusions 4a. According to this embodiment, since the blade of the dicer hits the AuSn solder 4 layer obliquely at the time of full dicing, peeling of the solder is further suppressed.
【００１８】以上好ましい実施例について説明したが、
本発明はこれら実施例に限定されるされるものではな
く、特許請求の範囲に記載された本願発明の要旨内にお
いて各種の変更が可能である。例えば、サブマウントの
材料をシリコンに代え、ダイヤモンド、ＢＮ、ＳｉＣ等
を用いることができ、また、電極材料、ろう材について
も実施例で示されたものに代え通常用いられている他の
材料を用いることができる。The preferred embodiment has been described above.
The present invention is not limited to these examples, and various modifications can be made within the scope of the present invention described in the claims. For example, diamond, BN, SiC, etc. can be used instead of silicon as the material of the submount, and other commonly used materials can be used instead of those shown in the examples for the electrode material and brazing material. Can be used.
【００１９】[0019]
【発明の効果】以上説明したように、本発明によるサブ
マウントは、ＬＤペレットの搭載部に頂部が平坦な突起
部をマトリックス状に配置したものであるので、本発明
によれば、マウント時にソルダはサブマウントの凹部に
沿って流動するため、ソルダボールの発生は抑制され
る。また、レーザペレットとサブマウントとを面接触を
もって密着させることができるため、レーザの放熱性を
向上させることができる。また、ウェハのダイシング工
程において、サブマウントの凹部に形成されたソルダ
は、網目状に電極上に被着しているため剥離されにくく
なっており、突起部のソルダについては剥がれることが
あっても、剥離はダイシング部の突起部のみに限定され
るため、ソルダ材の剥離を実用上問題のない程度に抑え
ることができる。さらに、サブマウントの製作上の利点
として、ウェハをダイシングするにあたり細かな位置制
御をする必要がないことが挙げられる。As described above, in the submount according to the present invention, the protrusions having flat tops are arranged in a matrix on the mounting portion of the LD pellets. Flows along the recess of the submount, so that the generation of solder balls is suppressed. Moreover, since the laser pellet and the submount can be brought into close contact with each other with surface contact, the heat dissipation of the laser can be improved. Also, in the wafer dicing process, the solder formed in the recesses of the submount is less likely to be peeled off because it is deposited on the electrodes in a mesh shape, and the solder on the protrusions may peel off. Since the peeling is limited only to the protruding portion of the dicing portion, the peeling of the solder material can be suppressed to such an extent that there is no practical problem. Further, as an advantage in manufacturing the submount, it is not necessary to perform fine position control when dicing the wafer.
【図１】本発明の第１の実施例のＬＤペレットの搭載時
の状況を示す斜視図。FIG. 1 is a perspective view showing a situation when an LD pellet according to a first embodiment of the present invention is mounted.
【図２】本発明の第１の実施例のサブマウントの製造方
法を説明するための斜視図と断面図。FIG. 2 is a perspective view and a cross-sectional view for explaining a method of manufacturing the submount according to the first embodiment of the present invention.
【図３】本発明の第１の実施例の正面図。FIG. 3 is a front view of the first embodiment of the present invention.
【図４】本発明の第２の実施例を説明するためのサブマ
ウントの平面図。FIG. 4 is a plan view of a submount for explaining a second embodiment of the present invention.
【図５】本発明の第３の実施例を説明するためのサブマ
ウントの斜視図。FIG. 5 is a perspective view of a submount for explaining a third embodiment of the present invention.
【図６】本発明の第４の実施例を説明するためのサブマ
ウント用ウェハの斜視図。FIG. 6 is a perspective view of a submount wafer for explaining a fourth embodiment of the present invention.
【図７】本発明の第５の実施例を説明するためのサブマ
ウント用ウェハの斜視図。FIG. 7 is a perspective view of a submount wafer for explaining a fifth embodiment of the present invention.
【図８】従来例の正面図と側面図。FIG. 8 is a front view and a side view of a conventional example.
【図９】従来例において用いられるサブマウントの斜視
図。FIG. 9 is a perspective view of a submount used in a conventional example.
【図１０】他の従来例において用いられるサブマウント
の斜視図。FIG. 10 is a perspective view of a submount used in another conventional example.
１ レーザダイオード・ペレット（ＬＤペレット） ２ Ｓｉサブマウント ２ａ、２ｂ、４ａ 突起部 ３ ＴｉＰｔ電極 ３ａ 下地金属層 ４ ＡｕＳｎソルダ ４ｂ ソルダボール ４ｃ ソルダ ５ 切断部 ６ ＰｂＳｎソルダ ７ ステム・ポール ８ 溝 DESCRIPTION OF SYMBOLS 1 Laser diode pellet (LD pellet) 2 Si submount 2a, 2b, 4a Projection part 3 TiPt electrode 3a Base metal layer 4 AuSn solder 4b Solder ball 4c Solder 5 Cutting part 6 PbSn solder 7 Stem pole 8 Groove
Claims (5)
ントと、該サブマウント上にろう材を介して搭載された
レーザダイオード・ペレットと、を備える半導体レーザ
装置において、前記サブマウントの前記レーザダイオー
ド・ペレットの搭載部の少なくとも一部は凹凸に加工さ
れており、その凸部はその頂部が平坦になされておりか
つレーザダイオード・ペレットの寸法より十分細かいピ
ッチでマトリックス状に配列されていることを特徴とす
る半導体レーザ装置。1. A semiconductor laser device comprising: a submount having a metal layer formed on a surface thereof; and a laser diode pellet mounted on the submount via a brazing material, wherein the laser of the submount is provided. At least a part of the mounting part of the diode pellet is processed into unevenness, and the convex part has a flat top and is arranged in a matrix at a pitch that is sufficiently smaller than the size of the laser diode pellet. A semiconductor laser device.
を特徴とする請求項１記載の半導体レーザ装置。2. The semiconductor laser device according to claim 1, wherein the convex portion has a circular cross-sectional shape.
に非平行であることを特徴とする請求項１記載の半導体
レーザ装置。3. The semiconductor laser device according to claim 1, wherein the row of the convex portions is not parallel to the side of the submount.
側部分下のサブマウントの表面は凹凸になされており、
前記レーザダイオード・ペレットの後方側部分下のサブ
マウントの表面は平坦になされていることを特徴とする
請求項１記載の半導体レーザ装置。4. The surface of the submount under the front portion of the laser diode pellet is uneven.
2. The semiconductor laser device according to claim 1, wherein the surface of the submount below the rear side portion of the laser diode pellet is flat.
縁に沿った部分にのみ形成されていることを特徴とする
請求項１記載の半導体レーザ装置。5. The semiconductor laser device according to claim 1, wherein the convex portion is formed only on a portion along four edges of the surface of the submount.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5201863A JPH0738208A (en) | 1993-07-22 | 1993-07-22 | Semiconductor laser device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5201863A JPH0738208A (en) | 1993-07-22 | 1993-07-22 | Semiconductor laser device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0738208A true JPH0738208A (en) | 1995-02-07 |
Family
ID=16448143
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5201863A Pending JPH0738208A (en) | 1993-07-22 | 1993-07-22 | Semiconductor laser device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0738208A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000063967A1 (en) * | 1999-04-20 | 2000-10-26 | Toyo Kohan Co., Ltd. | Heat sink base, heat sink, and method of manufacturing heat sink |
| JP2001127370A (en) * | 1999-10-22 | 2001-05-11 | Kyocera Corp | Submount for mounting semiconductor element |
| JP2003031895A (en) * | 2001-07-13 | 2003-01-31 | Sharp Corp | Semiconductor light emitting device and its manufacturing method |
| WO2004077630A1 (en) * | 2002-12-26 | 2004-09-10 | Sony Corporation | Semiconductor laser assembly |
| WO2005091383A1 (en) * | 2004-03-24 | 2005-09-29 | Renesas Yanai Semiconductor Inc. | Light-emitting device manufacturing method and light-emitting device |
| JP2008034874A (en) * | 2007-10-09 | 2008-02-14 | Fujifilm Corp | Semiconductor light-emitting apparatus and its manufacturing method |
| CN100449889C (en) * | 2002-12-26 | 2009-01-07 | 索尼株式会社 | Semiconductor laser assembly |
| US7891836B2 (en) | 2004-10-22 | 2011-02-22 | Koninklijke Philips Electronics N.V. | Semiconductor light-emitting device with improved heatsinking |
| US8625646B2 (en) | 2010-04-07 | 2014-01-07 | Mitsubishi Electric Corporation | Semiconductor device |
| US10004147B2 (en) | 2013-09-27 | 2018-06-19 | Siemens Aktiengesellschaft | Method for the diffusion soldering of an electronic component to a substrate |
| DE102018119522A1 (en) * | 2018-08-10 | 2020-02-13 | Infineon Technologies Ag | Semiconductor device comprising a recess and method for producing the same |
| CN111386637A (en) * | 2017-11-24 | 2020-07-07 | 京瓷株式会社 | Substrate for mounting light emitting element, array substrate, and light emitting device |
| US11322907B2 (en) | 2018-02-16 | 2022-05-03 | Kyocera Corporation | Light emitting element housing package, light emitting device, and light emitting module |
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|---|---|---|---|---|
| JPH02244689A (en) * | 1989-03-16 | 1990-09-28 | Fuji Electric Co Ltd | Manufacture of sub-mount of semiconductor laser element heat dissipating body |
| JPH0511470B2 (en) * | 1985-04-02 | 1993-02-15 | Nippon Denki Aishii Maikon Shisutemu Kk |
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1993
- 1993-07-22 JP JP5201863A patent/JPH0738208A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0511470B2 (en) * | 1985-04-02 | 1993-02-15 | Nippon Denki Aishii Maikon Shisutemu Kk | |
| JPH02244689A (en) * | 1989-03-16 | 1990-09-28 | Fuji Electric Co Ltd | Manufacture of sub-mount of semiconductor laser element heat dissipating body |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000063967A1 (en) * | 1999-04-20 | 2000-10-26 | Toyo Kohan Co., Ltd. | Heat sink base, heat sink, and method of manufacturing heat sink |
| JP2001127370A (en) * | 1999-10-22 | 2001-05-11 | Kyocera Corp | Submount for mounting semiconductor element |
| JP2003031895A (en) * | 2001-07-13 | 2003-01-31 | Sharp Corp | Semiconductor light emitting device and its manufacturing method |
| JP4626517B2 (en) * | 2002-12-26 | 2011-02-09 | ソニー株式会社 | Laser diode assembly |
| JPWO2004077630A1 (en) * | 2002-12-26 | 2006-06-08 | ソニー株式会社 | Laser diode assembly |
| CN100449889C (en) * | 2002-12-26 | 2009-01-07 | 索尼株式会社 | Semiconductor laser assembly |
| US7502397B2 (en) * | 2002-12-26 | 2009-03-10 | Sony Corporation | Semiconductor laser assembly |
| WO2004077630A1 (en) * | 2002-12-26 | 2004-09-10 | Sony Corporation | Semiconductor laser assembly |
| WO2005091383A1 (en) * | 2004-03-24 | 2005-09-29 | Renesas Yanai Semiconductor Inc. | Light-emitting device manufacturing method and light-emitting device |
| US7795053B2 (en) | 2004-03-24 | 2010-09-14 | Hitachi Cable Precision Co., Ltd | Light-emitting device manufacturing method and light-emitting device |
| US7891836B2 (en) | 2004-10-22 | 2011-02-22 | Koninklijke Philips Electronics N.V. | Semiconductor light-emitting device with improved heatsinking |
| JP2008034874A (en) * | 2007-10-09 | 2008-02-14 | Fujifilm Corp | Semiconductor light-emitting apparatus and its manufacturing method |
| US8625646B2 (en) | 2010-04-07 | 2014-01-07 | Mitsubishi Electric Corporation | Semiconductor device |
| US10004147B2 (en) | 2013-09-27 | 2018-06-19 | Siemens Aktiengesellschaft | Method for the diffusion soldering of an electronic component to a substrate |
| EP3036761B1 (en) * | 2013-09-27 | 2019-07-10 | Siemens Aktiengesellschaft | Method of diffusion soldering an electronic component with a mounting surface with recesses on a substrate |
| CN111386637A (en) * | 2017-11-24 | 2020-07-07 | 京瓷株式会社 | Substrate for mounting light emitting element, array substrate, and light emitting device |
| JPWO2019102956A1 (en) * | 2017-11-24 | 2020-11-19 | 京セラ株式会社 | Light emitting element mounting board and array board, and light emitting device |
| US11757249B2 (en) | 2017-11-24 | 2023-09-12 | Kyocera Corporation | Substrate for mounting a light-emitting element and array substrate, and light-emitting device |
| US11322907B2 (en) | 2018-02-16 | 2022-05-03 | Kyocera Corporation | Light emitting element housing package, light emitting device, and light emitting module |
| DE102018119522A1 (en) * | 2018-08-10 | 2020-02-13 | Infineon Technologies Ag | Semiconductor device comprising a recess and method for producing the same |
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