JPH0429859A - Printing head controller - Google Patents

Abstract

PURPOSE:To decrease the number of gates by a method wherein a printing data is outputted by receiving output of a timing generating means which generates printing timing of all pins for correcting an inclination of a pin line of a printing head inclined to a direction cutting a transfer direction of a carriage at right angles, and an AND of the printing timing and the printing data is taken. CONSTITUTION:For a dot pattern of a head, odd pins in 24 pins form a first line and even pins form a second line. A pin N is shifted to a pin (N+2) among 12 pins of each line by 1/120 X 1/12 inch in a printing line direction. Herein, the pin N and a pin (N+1) in the first line and the second line are driven at the same timing. A timing generating part 5 outputs a timing signal (b) of all dots of a printing head according to a printing mode establishing signal (d) from a CPU 1. The output (b) of the timing generating part 5 is taken as a clock, and output (k) of an AND circuit 9 which takes an AND of output (j) of a latch part 8 for latching output (i) of a synchronous part 7 and the timing signal (b) is taken as a drive signal. Then, the head is driven by impressing pulse voltage to a head coil 11.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a print head control device for a dot matrix printer.

Conventional technology In recent years, dot matrix printers have been mounted on carriages to avoid noise caused by each dot hitting the dots at the same time, magnetic interference when using a large capacity power supply or electromagnetic force, and high-density packaging. A distributed print head is used that performs printing by supplying a signal corresponding to each pin in a row of pins of the print head, the pins of which are arranged at an angle with respect to the direction perpendicular to the direction of movement of the carriage. A head control device is used.

A conventional print head control device will be described below.

FIG. 9(a) shows the pin row pattern of a conventional 24-pin wire dot head. Figure 9(b) shows the pin array pattern of a distributed print head in which the pins are arranged at an angle.
C) is another example of a pin array pattern for a distributed print head.

FIG. 10 is a drive timing chart of the 24-pin wire dot head, and FIG. 10(a), FIG. 10(b),
Figure 10(c) is Figure 9(a) and Figure 9(b), respectively.
, corresponds to the head with the pin row pattern shown in FIG. 9(c). In the pin row pattern shown in Figure 9(a), the first
As shown in Figure 0 (a), timing T7 determines the spacing between the dots that make up the characters, and timing T8 determines the energization time of the head coil that drives the pins of the head.
However, in the pin array pattern of FIG. 9(b), the drive timing is different for each pin as shown in FIG. 10(b), so the timing T7 is sufficient.
In addition to a timer that generates timing T8, a timer that generates timing T9 that determines the delay time for each pin according to the slope of the pin arrangement is required, and it is necessary to delay all the drive timings of 24 pins by timing T9.

In the pin arrangement of FIG. 9(C), the control circuit is simplified by delaying the drive timing for each group of six pins as shown in FIG. 10(C).

FIG. 11 is a block diagram of a conventional print head control device having the pin arrangement shown in FIG. 9(b). In Figure 11,
127 is a character font read-only memory (hereinafter referred to as character font RO) in which character font data is written.
It is abbreviated as M. ), 128 is a timing generation unit that generates timing for distributing print data, and a timer 129 generates a clock with timing of T7 and T8 as shown in FIG. 10(b), and a clock with timing of T9 is generated. timer 130 and these timers 1
It consists of an oscillator 131 that operates 29.130. Reference numeral 132 denotes a print data dispersion unit composed of a shift register that delays print data read from the character font ROM 127. 133 is a central processing unit (hereinafter abbreviated as CPU), and a character font ROM 127
, the timing generation section 128, and the print data dispersion section 132 are each connected to an input/output section (hereinafter abbreviated as I10 section) 1.
It is controlled via 34. Reference numeral 135 indicates 24 AND circuits, each of which takes the AND of the print data for 24 pins from the CPU 133 and the output of the timer 129. 136 is a head driver that applies a pulse signal to the head coil 137.

The operation of the print head control device configured as described above will be described below.

The CPU 133 is always informed by the timer 129 of the falling timing W of the timing signal of the first pin (hereinafter referred to as shift data) shown in FIG.
The PU 133 reads the print data for 24 pins from the character font ROM 127 and sends it to the AND circuit 135 according to the falling timing of the shift data, and the AND circuit 135 ANDs each of the print data for the 24 pins and the output of the timer 129. It is sent to the print data distribution section 132. Also, the timer 130 converts the character mode data
A clock (hereinafter abbreviated as shift clock) having a timing having a period of T9 in FIG. 10(b) corresponding to the print mode is sent to the print data distribution unit 132 from the U 133. The print data distribution unit 132 is A
Based on the output signal from the ND circuit 135 and the shift clock, drive signals for pins 1 to 24 in FIG. 10(b) are generated and sent to the head driver 136. The head driver 136 drives the head by applying a pulse voltage to the head coil 137 in response to a drive signal from the print data distribution unit 132 . The frequency of the shift clock t changes depending on the printing mode for various characters, but T8
In order to maintain the timing of t, T8 is the shift clock t.
Therefore, it is necessary to increase the frequency of the shift clock t, that is, to provide the print data distribution unit 132 with a shift clock obtained by subdividing the T9 period. For this reason, the print data distribution section 132 has multiple stages of shift registers.

Problems to be Solved by the Invention However, in the conventional configuration, the character font ROM
The print data read from 127 is applied to the head coil 12.
40 energization time data is added, and the data obtained by adding the energization time data to this print data is used to generate a distribution corresponding to each pin in the pin row of the distributed print head in a shift register that constitutes the print data distribution unit 132. Since data is being generated, the energization time of the head coil 124 is maintained for all printing modes, so that the WIFR of the head coil 124 is always an integer of the cycle of the shift clock that drives the shift register of the print data fraction section 132. It is necessary to increase the frequency of the shift clock so that the frequency is doubled, and the number of shift registers and gates in the print data distribution section 132 increases. If a dot pattern configuration as shown in FIG. 9(C) is used to reduce the number of gates, the effects of printing noise reduction, power supply capacity reduction, etc. will be drastically reduced.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides all pins that are mounted on a carriage and correct the inclination of the pin row of the print head that is inclined with respect to the direction perpendicular to the direction of movement of the carriage. The present invention includes a timing generation means for generating a print timing of , a print data output means for receiving an output of the timing generation means and outputting print data, and a means for calculating a logical product of the print timing and the print data.

Operation The present invention can correct the inclination of the pin array of the print head that is inclined with respect to the moving direction of the carriage without using the shift register circuit having the above-described configuration.

Embodiment FIG. 1 is a block diagram of a print head control device in an embodiment of the present invention.

In Fig. 1, 1 is a central processing unit (hereinafter abbreviated as CPU), 2 is an input/output unit (hereinafter abbreviated as I10 unit) that serves as an interface between each device, and 3 is only for reading character fonts. Memory (hereinafter referred to as character font ROM)
It is abbreviated as. ). 4 is an oscillator, and 5 is a timing generation section which operates using the output a1 of the oscillator 4 as a basic clock, and outputs timing signals for all dots of the print head in accordance with a print mode setting signal d from the CPUI. A data selector 6 selects one signal from the timing signals according to the print mode setting signal d and outputs it to the CPU 1 as an interrupt signal e. 7 is the CPU in the synchronization section
According to the print mode setting signal f from 1, the print data g1 from the CPUI is synchronized with the distributed timing b using the output e of the data selector as a clock. 8 is a latch section which uses the output of the timing generation section 5 as a clock and latches the output j of the synchronization section 7; 9 is an AND circuit which ANDs the output j of the latch section 8 and the timing No. 11; A head driver 10 drives the head by applying a pulse voltage to the head coil 11 using the output k of the AND circuit 9 as a drive signal.

FIG. 2 shows a dot pattern of a head controlled by the print head control device of the present invention. In Figure 2, the dot pattern of the head is such that out of 24 pins, the odd numbered pins are in the first row and the even numbered pins are in the second row. N and pin (N+2) are shifted by 1/120*1/12 inch in the printing line direction. Here, 1/120 inch is the dot spacing between characters. Pin N and pin (N+
1) are driven at the same timing in the following explanation. That is, the interval between the first column and the second column in the print line direction is an integral multiple of 1/120 inch. Furthermore, in order to facilitate control of the 12 pins in the same column, the lower 8 pins are designated as an L block, and the upper 4 pins are designated as a (2) block.

3(a) is a block diagram of the synchronizing section 7 of FIG. 1, and FIG. 3(b) is a block diagram of another embodiment of the synchronizing section 7 of FIG. 1. In FIG. 3(a) and FIG. 3(b), 21.
22 are data g2 . In FIG. 3(a), 23, 24, and 25 are respectively print data gl, g2... AND g3 and print mode setting signals f-1, f-2, f-3 output from CPU1.
circuit, 26 is the output ml of the AND circuit.

m2. This is an adder that adds m3. In FIG. 3(b), 27 indicates the print data gl by the print mode setting signal f.
, g2. This is a data selector that selects the print data of one of the chairs in g3 and outputs it as print data i.

FIG. 4 is a block diagram of the timing generator 5 of FIG. 1. In FIG. 4, 31 is the output a of the oscillator 4 in FIG.
The address counter 32, which operates using 1 as a clock, uses a magnitude comparator to compare the print mode setting signal d-1 from the CPU 1 and the output m of the address counter 31, and outputs an address counter load fs number p. As a result, the address counter 31 counts the set d-1 as a count value. Reference numeral 33 denotes a distributed timing read-only memory (hereinafter abbreviated as distributed timing ROM) from which distributed timing is read using the output m of the address counter 31 and the print mode setting signal d-2 as addresses. 35 is a shift register which operates using one output m-1 of the address counter as data and a2 which is obtained by inverting the clock a1 by an inverter 34, and 36 is a distributed timing RO whose clock is the output n of the shift register 35.
This is a latch section made up of a flip-flop that latches the output O of M33. The operation of the print head control device configured as described above will be described below.

FIG. 5(a) shows the output signal 24 of the timing generator 5.
It is a timing chart showing the timing for pins. T1 is the printing interval between dots, T2 is the delay time between the n pin and (n+2) pin of the head, and T4 is the energization time of the head 11. Distributed timing ROM33
Twelve types of basic cycle signals corresponding to each of these pins are written in advance, and are read out at the address generated by the address counter 31. FIG. 5(b) is an address map of the distributed timing ROM 33. The printer's character font is Draft and NLQ (Near Le
There are two types: 10.12, 15.17 cpi, and 4 types of characters per inch (10, 12, 15, and 17 cpi), and the print direction of the head is forward direction (hereinafter abbreviated as Go) and reverse direction (hereinafter abbreviated as RETURN). ) two types,
There are 16 distributed timing data corresponding to each of them.
A total of 7FFF addresses are written every 800 addresses in base numbers. These print mode selections are made using the mode data signal d.
-2. The length of T1 in FIG. 5(a) differs depending on the printing mode, but the length is
loads the address counter 31 to all zeros after T1 time has elapsed in accordance with each print mode. T1 is maximum 10
The time is set to 24 μs.

FIG. 6 is a timing chart showing the output latch timing of the distributed timing ROM 33. The switching time T5 of address m is T5 = 500 ns, and the lower 8 bits of timing data (hereinafter referred to as bL data) and the upper 4 bits of timing data (hereinafter referred to as bH (abbreviated as data) are output sequentially. T6 is the output delay time of the distributed timing ROM 33 and is about 150n3, so bL and bH
Timing T7 to latch data is T6<T7<T5
T7 is set to 250 nS so that. These latch clocks nl and n2 are generated by the shift register 35 from ml output from the address counter and the inverted basic clock a2. The latch unit 36 latches the bL data and bH data of the output 0 of the distributed timing R0M33 using the latch clocks nl and n2, and further latches these data by m
A 12-bit distributed timing signal is generated by latching at the rising edge of l. These outputs are accurate to 1 μs.

FIG. 7 is a timing chart of the control device of the present invention. The synchronization section 7 in FIG. 3 will be explained below according to this timing chart. In Figure 7(a), gl is C
The output of PU1 is 24-bit print data. bl,
2 to b23 and 24 are the outputs of the timing generator 5, and these 12 signals are repetitive signals with a cycle of T1, which is the printing interval between dots, and are bn (n
=1.3. ...23 or n=2.4. ...
For 24 pins, b (n+2) is the n pin of He/Sodo and (
There is a delay of 12 hours, which is the delay time with the n+2) pin. Now, if T1 = 960 μs, then T2 becomes T2 = T1/12 = 80 μs, and during this period of T1, the head moves in the printing direction by 1/120*, which is the deviation in the printing direction between pin N and pin (N+2).
Advance 1/120 inch, which is 12 times 1/12 inch. T3
is the data processing time of the CPU 1, and if T3=50 μs, then the CPU 1 receives the rise of b23 and 24 as an interrupt signal e, outputs print data to the synchronization unit 7, and outputs this print data g1 to bl by the latch unit 8. From b2
Latch at the rising timing of 4. The head energization time T4 is guaranteed by ANDing the latch output j and the timing signal S by the AND circuit 9.

7(b), 7(c), and 7(d) are 1/180 inch and 172 inch, respectively, during the printing interval T1 period.
This is a time chart when the 40-inch and 1/360-inch heads advance in the printing direction, and it is necessary to take measures to prevent the printed characters from being tilted for these printing modes that change the quality of the characters. .

In FIG. 4(b), the delay time T2 between the n pin and (n+2) pin of the head is T 2 = T1/12 molecule t'c * (1/12
0inf/1/180i:zf)=960/12*
(180/120) = 120 μs In Fig. 4(c), T2 is T 2 = T1712 dispersion * (1/120 in f/
1/24(lf7+)=960/12* (240/
120) = 160μs In Fig. 4(d), T2 is T2 = T1/12 dispersion* (1/120(f/1/:160iaf)=960/12* (38
0/120)=240 μs. In this way, since the time of T2 differs depending on each mode, in the latch section 8, the timing b1.
Print data g1 is latched at the rising edge of bl5 and bl16 from timing b17°18, and print data g2 obtained by delaying gl by a period of T1 is latched at the rising edge of b23 and 24 from timing b17°18.

In Fig. 4 (C), timing bl, 2 gara bll, 1
2 to latch gl, L) 13.14 to b23, 24 to latch g2.

In Fig. 4(d), from timing b1,2 to b7°8, g
l, g2 from b9,10 to bl5,16, and then bl
From 7, 18 to b23, 24, print data g3 obtained by delaying gl by T1*21* is latched. The interrupt signal e to the CPU 1 must be selected from among bl, 2 to b23, 24, depending on the character mode and print direction of the head. The data selector 6 sets the character mode setting signal d to select tS and selects the interrupt signal e from bl, 2 to b23, 24. Figure 7(e) is l/360
In the inch dot pitch mode, the head is
This is a timing chart for printing in the opposite direction to d), and the printing timing is delayed by T2 from b23.24 to bl and 2. Therefore, the interrupt signal e to CPU1 is as shown in Fig. 7 (a), (c), (d).
Then, use b23 and 24 for the forward printing direction, and bl for the reverse printing direction.
, 2 is used. In Figure 7(b), the interrupt signal is bl5, 16 in the forward printing direction, and b9°10 in the reverse printing direction.
Use. This interrupt signal e also serves as a latch clock for delaying the print data g1 in the synchronization circuit 7 by a time T1. Here, g2 in which the print data g1 in FIG. 7 is delayed by a period of T1, and g3 in which the print data g1 is delayed by a period of T1*2 are the outputs of the latch sections 21 and 22 in FIGS. 3(a) and (b). g2. g is CPU
The print data g1 is delayed by the latch 21 for a period of T1 using the interrupt signal e as a synchronization clock, and the output g2 thereof is further delayed by the latch 22 for a period of T1. In FIG. 3(a), the print data gl, g2. g3 each has 24 AND circuits 23.
Entered on 24.25. This AND circuit 23.24.
25, one input of the AND circuit fl, f2 . f3 is f
1 = ” 00000000 00 units 000
00 11111111 °.

f2="000000001111111100000
000°9f 3 = ” 111111110000
000000000000'', and the 24-bit print data is enabled for each group of 8 bits from lower to upper. Outputs ml, m2.
By adding m3, the output can be made to correspond to gl, g2, and g3 for each group of 8 pits from the lower to the upper printing timing, as shown in FIG. 4(d). Furthermore, if the print direction of the head is reversed, this can be handled by replacing fl and f3. Figure 3(a)
This circuit is the synchronous circuit 7 in FIG.
This can also be realized by software using registers in PU1.

For example, output buffer register B output buffer register A output buffer register B, register B, register A, register A, register A, input buffer, input buffer, input buffer, output buffer, AND DD OVE AND DD OVE AND DD OVE When you assemble the software, first set register B (3rd
A of print data g3 and f3 existing in latch 22) in the figure
Take ND and send the print data m3 to the output buffer (
Adder 26 in FIG. 3) - Time storage. 3 to register A (
Copy the print data g2 of latch 21) in FIG. 3 to register B. 4, print data g2 existing in register A
and f2 are ANDed, and in step 5, the print data m2 and m3 of the output buffer are added and temporarily stored. In step 6, the print data g1 of the input buffer containing the font data to be printed is copied to register A. Step 7: AND the print data g1 and fl existing in the input buffer, and step 8: AND the print data m1 and m2+m3 existing in the output buffer.
and is output to I10 section 2 at 9. This process may be performed every time the interrupt signal e is input.

FIG. 3(b) shows another embodiment, in which 24 3t01 data selectors 27 are used instead of the AND circuit.
g2. g3 is input, and the mode setting signal f selects between gl and g3.

This mode setting signal f does not indicate the printing direction of the head and also includes an f word.

FIG. 8 shows the effect of distributed printing on noise using the circuit of the present invention. 7dB at 1/4 dispersion, 10 at 1/12 dispersion
It has a noise reduction effect of dB.

Effects of the Invention As described above, the present invention provides timing for generating print timing for all pins to correct the inclination of the pin row of the print head mounted on the carriage and inclined with respect to the direction perpendicular to the moving direction of the carriage. By providing print data output means for outputting print data in response to the outputs of the generation means and timing generation means, and means for calculating the logical product of the print timing and the print data, the carriage can be moved without using a shift register circuit. It is possible to correct the inclination of the pin array of the print head that is inclined with respect to the direction perpendicular to the moving direction, and it is possible to reduce the number of gates.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a print head control device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a print head control device according to an embodiment of the present invention. 7, FIG. 3(b) is a block diagram 1 of another embodiment of the synchronizer 7 in FIG. 1, FIG. 4 is a block diagram of the distributed timing generator 5 in FIG. 1, and FIG. a) is a timing chart showing the timing for 24 pins of the output signal of the distributed timing generator 5, FIG. 5(b) is the address map of the distributed timing ROM 33, and FIG. 6 is the drive timing of the head of the distributed timing ROM 33. The chart, FIG. 11, is a block diagram of a conventional print head control device. 1... Central processing unit 2... Input/output unit 3... Character font read-only memory 4... Oscillator 5... Timing generation unit 6... Data selector 7... Synchronization unit 8...・
Latch part 9...AND circuit 10...Head driver 11...Head coil 21.22.
...Latch section 23.24.25...AND circuit 26...Adder 27...Data selector 31...Address counter 32...Magnitude comparator 33...Distributed timing read-only memory 34...・Inverter
35...Shift register 36...Name of latch section agent Patent attorney Shigetaka Awano One idiot Figure 5 (a) Pin 9.10 Pin + +, 12 Pin 13.14 Pin 15.16 Pin 17 .18 Pin +9.20 Pin 2L22 Pin 23.24 Figure (b) Figure = [Nini====] Ni (8p) O o o o o o o o OOo O○

Claims (3)

[Claims] (1) A print head control device mounted on a carriage that performs printing by supplying drive signals corresponding to each pin in a row of pins of the print head that is inclined with respect to the direction perpendicular to the direction of movement of the carriage. a timing generation means for generating a print timing for each pin; a print data output means for receiving the output of the timing generation means and outputting print data; and a means for taking an AND of the print data and the print timing. A print head control device comprising: (2) The timing generation means, depending on the print mode,
2. The print head control device according to claim 1, wherein one signal is selected from among the print timing signals and is applied to the print data output means. (3) A print head control device mounted on a carriage and configured to perform printing by supplying drive signals corresponding to each pin in a row of print head pins inclined with respect to a direction perpendicular to the direction of movement of the carriage. a timing generation means for generating print timing for all dots; a print data output means for outputting print data in response to the output of the timing generation means; a delay means for delaying the print data by a print interval cycle; A print head control device characterized by comprising: selection means for selecting the output of the delay means according to a mode; and means for taking an AND of the print timing and the output of the delay means.