JPH0444868A - Printing head controlling device - Google Patents

Abstract

PURPOSE:To decrease the number of gates by maintaining a power supply time without increasing the frequency of shift clocks, and constituting the title device so as to correct the inclination of a printing pin line in a distributed printing head. CONSTITUTION:A distributed timing generation unit 4 consists of an oscillator 5, a timer 6 for generating a clock 'c' having a timing of determining a dot space constituting characters and a timing of determining a power supply time to drive pins, and timers 7, 8 for generating shift clocks 'd', 'e' for a shift register unit 10, which delay printing data drive signals. The flip-flop of the above-mentioned register unit 10 is shifted by respective one-step flip-flops, which set the outputs 'd', 'e' from the timers 7, 8 to the shift clocks, with respect to output data g2 from an AND circuit 9, and increases the flip-flops in sequence in stepwise fashion with respect to output data g3-g24. An S-R latch unit 11 converts outputs hl-h23 from the shift register unit 10 into set signals and outputs i1-i24 into preset signals to generate total dot timing signals j2-j24 for pins 2-24. A head drive 12 drives a head 13 on the basis of these dot timing signals and the output j1 from the shift register unit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a print head control device for a dot matrix printer.

Conventional technology In recent years, in dot matrix printers, dot matrix printers have been mounted on carriages to avoid noise caused by each pin hitting the dot at the same time, magnetic interference when using a large capacity power supply or electromagnetic force, and for high-density packaging. , a distributed print head is used, which uses a print head in which the pins are arranged at an angle with respect to the direction perpendicular to the direction of carriage movement, and prints by supplying a drive signal corresponding to each pin in the pin row. A printhead control device for the printhead is used.

A conventional print head control device will be described below.

FIG. 5(a) shows the pin row pattern of a conventional 24-pin wire dot head. Figure 5(b) shows the pin row pattern of a distributed print head in which the pins are arranged at an angle.
C) is another example of a pin array pattern for a distributed print head.

FIG. 6 is a drive timing chart of the 24-pin wire dot head, and FIG. 6(a), FIG. 6(b), and FIG. 6(c) are respectively FIG. ), corresponds to the head with the pin row pattern shown in FIG. 5(C). In the pin row pattern of Fig. 5(a), Fig. 6(a)
As shown in FIG. 5(b), only a timer is required to generate timing T7, which determines the interval between dots that make up a character, and timing T8, which determines the energization time of the head coil that drives the pins of the head. In the pin array pattern shown in Figure 6(b), each pin has a different drive timing, so not only the timer that generates timing T7 and timing T8, but also the delay time for each pin according to the slope of the pin array. A timer is required to generate the timing T9 that determines the timing T9, and it is necessary to delay all the drive timings of the 24 pins by the timing T9. Figure 5 (C)
In the pin arrangement shown in FIG. 6(C), the drive timing is delayed for each group of six pins to simplify the control circuit.

FIG. 7 is a block diagram of a conventional print head control device having the pin arrangement shown in FIG. 5(b). In Figure 7, 14
15 is a character font read-only memory (hereinafter abbreviated as character font ROM) in which character font data is written, and 15 is a distributed timing generation unit that generates timing for distributing print data, as shown in FIG. 6(b). The timer 16 generates clocks having timings T7 and T8 as shown in FIG. Reference numeral 19 denotes a print data distribution unit that delays print data read from the character font ROM 14. 20 is a central processing unit (hereinafter abbreviated as CPU); character font ROM 14;
Each of the distribution timing generation section 15 and the print data distribution section 19 is connected to an input/output section (hereinafter abbreviated as I10 section) 21.
Controlled through. 22 is 24 AND circuits, each of which takes the AND of the print data for 24 pins from the CPU 20 and the output of the timer 16. 23 is the head coil 24
This is a head driver that applies pulse signals to the head.

The operation of the print head control device configured as described above will be described below.

The CPU 20 uses the timer 16 to output the timing signal of the first pin shown in FIG. 6(b) (hereinafter abbreviated as shift data).
The falling timing W of is always notified, and the CPU 20
reads the print data for 24 pins from the character font R,0M14 and sends it to the AND circuit 22 according to the falling timing of the shift data.
D is taken and sent to the print data distribution section 19. Also timer 17
Then, the character mode data Send to 19th. The print data distribution section 19 distributes the data from pin 1 to pin 2 in FIG.
Drive signals for up to 4 pins are generated and sent to the head driver 23. The head driver 23 drives the head by applying a pulse voltage to the head coil 24 in response to a drive signal from the print data distribution section 19 . shift clock t
The frequency of changes depending on the printing mode for various characters, but in order to maintain the timing of T8, T8 must be an integral multiple of the shift clock t, so it is necessary to increase the frequency of the shift clock t. That is, it becomes necessary to provide the print data dispersion section 19 with a shift clock obtained by subdividing the T9 period. For this reason, the print data distribution section 19 has multiple stages of shift registers.

Problems to be Solved by the Invention However, in the conventional configuration, the character font ROM
The data on the energization time of the head coil 24 is added to the print data read from the print data 14, and the print data distribution unit 19 uses the data obtained by adding the energization time data to the print data.
The shift register that makes up the head coil 24 generates distributed data corresponding to each pin in the pin row of the distributed print head. It is necessary to increase the frequency of the shift clock so that the energization time of the print data distribution unit 19 is always an integral multiple of the cycle of the shift clock that drives the shift register of the print data distribution unit 19.
9, the number of shift registers and the like is large and the number of gates is large. If a pin row pattern configuration as shown in FIG. 5(C) is adopted in order to reduce the number of gates, effects such as printing noise reduction and power supply capacity reduction will be drastically reduced.

Means for Solving the Problems In order to solve the above problems, the present invention corrects the inclination of the pin rows of the print head mounted on the carriage and inclined with respect to the direction perpendicular to the moving direction of the carriage. A first timer that generates a first timing signal whose period is the time difference between the drive signals for each pin and that is synchronized with the rising timing of the energization time of the print head, and a drive signal for each adjacent pin that corrects the inclination of the pin row. a second timer that generates a second timing signal synchronized with the fall timing of the energization time of the print head, with a period equal to the time difference between a register, a second shift register for shifting print data using a second timing signal as a shift clock, and driving means for driving the print head by an output of the first shift register and an output of the second shift register. Equipped with

Effect of the Invention With the above-described configuration, the present invention can maintain the energization time of the print head without increasing the frequency of the shift clock, and can correct the inclination of the pin array of the print head that is inclined with respect to the moving direction of the carriage.

Embodiment FIG. 1 is a block diagram of a print head control device in an embodiment of the present invention.

In Fig. 1, 1 is a central processing unit (hereinafter abbreviated as CPU), 2 is an input/output unit (hereinafter abbreviated as 170 unit) having an interface between each device, and 3 is only for reading character fonts. Memory (hereinafter referred to as character font ROM)
It is abbreviated as. ). 5 is an oscillator, 6.7.8 is a timer driven by the basic clock a generated by the oscillator 5, and print mode data bl, b2 . Starting counting at T7.b3, the timer 6 starts counting at T7.b3 as shown in FIG. 6(b). A shift clock d of the shift register section 10 generates a clock C having a timing of T8, and a timer 7.8 delays the print data drive signal.

Generate e. These oscillator 5 and timers 6, 7, and 8 constitute a distributed timing generating section 4 that generates timing for distributing print data. 9 is 24 A, N
Each D circuit ANDs the print data for 24 pins from the CPU 1 and the output signal of the timer 6 and outputs it to the shift register section 10 consisting of 552 flip-flops. The flip-flops of the shift register section 10 are A,
It operates using the output g of the ND circuit 9 as shift data and the outputs d and e of the timer 7 or timer 8 as a shift clock.

Note that the flip-flops of the shift register section 10 are A,
The output data g2 of the N-D circuit 9 is shifted by a one-stage flip-flop using the output d of the timer 7 as a shift clock and another one-stage flip-flop using the output e of the timer 8 as a shift clock. 2 for
The stage is shifted by a flip-flop. Below, g4
As shown in FIG. 11, for ~g24, the number of flip-flops increases one stage at a time, and for g24, there are 23 stages of flip-flops using the output d of timer 7 as a shift clock and the output e of timer 8. is shifted by a 23-stage flip-flop using the shift clock. The S-R latch section 11, which consists of 23 set/reset latches (hereinafter abbreviated as S-R latches), operates using the outputs h1 to h23 of the shift register section 10 as set signals and the outputs 11 to i23 as reset signals. Pins 2 to 24 generate timing signals j2 to j24 for all dots printed. 12
is a head driver, and the head 1 is
Drive 3.

The operation of the print head control device configured as described above will be explained below.

FIG. 2 is a pattern of pin rows of a head controlled by the print head control device of the present invention. In Figure 2, the pin row pattern of the head is such that among the 24 pins, the odd numbered pins are in the first row and the even numbered pins are in the second row. Of these, pin N and pin (N+2) are shifted by 1/120*1/24 inch in the printing line direction. Here, 1/120 inch is the dot spacing between characters. Pin N and pin (
N+1) is also not driven at the same timing in the following explanation. In other words, the distance between the first and second columns in the printing line direction is 1/120*n inches+1/120*
The width is 1/24 inch (where n is an integer).

FIG. 3(a) shows the output g of the AND circuit 9 when printing is performed by driving all 24 pins, and FIG. 3(b) shows the timing of the input signals j1 to j24 of the head driver 12 in this case. This is a timing chart. As shown in Fig. 3(b), the printing timing for each pin is timing T1, which determines the interval between dots that make up a character, timing T2, which determines the energization time of the head coil that drives the head pins, and timing T2, which determines the energization time for the head coil that drives the head pins. It consists of timing T3 that determines the delay time of . The CPU is always informed of the falling timing C of the timing signal of the first pin in FIG.
Print data for 24 pins read from OM3 to I10
The signal is sent to the AND circuit 9 via the section 2. Further, the timer 6 receives and generates character mode data b1 from cPUl at a timing with a cycle of T1 in FIG. is ANDed and sent to the shift register section 10. However, the shift data on pin 1 is transferred to the shift register section 10.
The data is sent directly to the head driver 12 without passing through.

FIG. 4 is a timing chart showing the timing of the shift register section 10 and the S-R latch section 11. below,
An example will be explained in which printing is performed by driving all 24 pins as in the timing chart of FIG. 3. The output g of the AND circuit 9 has the timing shown in FIG. 3(a). In the shift register unit 10, the print interval of the head is the cycle of T1 in FIG.
=T1/24) and (T2-T5)<T4<T2.

Timer 7 and timer 8 generate signals d and e with a period of Tl/24=T5 for the print interval T1 of the head. The shift register section 1o operates using the output g of the AND circuit 9 as shift data and the outputs d and e of the timers 7 and 8 as a shift clock) and outputs timing signals from outputs h1 to h23 and timing signals from outputs 11 to i23. is sent to the S-R latch unit 11. In the outputs of these shift register units 10, hn+1 (where n=1.2.3, . . . , 22) is a signal delayed by T5 time with respect to hn. Here, the timing signal for h1 to h23 is T4=n*T5 (where n is an integer), but since T5 changes depending on the character mode, n*T5=T2 is not always true, but T4=T2. Because it does not peel off, the timing of T2 cannot be maintained, as shown in Figure 3 (b).
It has only the rise timing of the head drive timing signal. Also, for in, l n+1 is T5
It is a time-delayed signal and has only the fall timing of the head drive timing signal shown in FIG. 3(b). The output e of the timer 8 has the same cycle as the output d of the timer 7, and is delayed from d by 16 hours. Here, T6 is the time when T8+T5 tree n=T2. The SR latch unit 11 is a group of 23 SR latches whose set timing is set at the rising timing of hn, and whose reset timing is set at the falling timing of in.

This S-R latch generates a distributed timing signal from j2 to j24 that guarantees the printing interval time T1 and head current supply time T2, and in the shift register section 10, the timing signal j1 of pin 1 which does not pass through the flip tab is combined with the timing signal j2
A timing signal for 4 pins, that is, a 24-bit signal shown in FIG. 3(b) is obtained. The head driver 13 has j1 to j24.
Drive the head according to the following.

The above explanation was for 1/120 inch dot pitch, but for example, in the case of 1/240 inch dot pitch, T
5=T1/12, so the setting signal bl from CPU1
, b2. T1, T2, T3, T5, and T6 are determined in b3.

The present invention requires only 4000 gates, whereas the conventional circuit requires about 7000 gates. In addition, in the print head device of the present invention, 1/4 dispersion is 7 dB, and 1/12 dispersion is 10 dB.
It has a noise reduction effect.

Effects of the Invention As described above, the present invention corrects the inclination of the row of pins of the print head mounted on the carriage and inclined with respect to the direction perpendicular to the moving direction of the carriage. is the period, and the period is the time difference between the first timer that generates the first timing signal synchronized with the rising timing of the energization time of the print head, and the drive signal for each adjacent pin that corrects the inclination of the pin row. The second pulse is synchronized with the fall timing of the head's energization time.
a second timer that generates a timing signal; a first shift register that uses the first timing signal as a shift clock to shift print data; and a second timer that uses the second timing signal as a shift clock to shift print data. By including a shift register and a driving means for driving the print head using the output of the first shift register and the output of the second shift register, the energization time of the print head can be reduced without increasing the frequency of the shift clock. It is possible to correct the inclination of the pin array of the print head which is maintained and inclined with respect to the moving direction of the carriage, and it is possible to reduce the number of gates.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram of a print head control device according to an embodiment of the present invention, FIG. 2 is a pattern diagram of a pin row of a head controlled by the print head control device of the present invention, and FIG. 3 is a timing chart explaining the output timing of the A, ND circuits and shift register section in the same embodiment, and the fourth
The figure shows a timing chart of the shift register section and S-R latch section of the same embodiment, and FIG.
C) is a diagram of the pin row of the inclined head; FIG. 6 is a drive timing chart of a 24-pin wire dot head; and FIG. 7 is a block diagram of a conventional print head control device. 1... Central processing unit 2... Input/output section 3...
Character phono)・Read-only memory 4... Distributed timing generation unit 5... Oscillator 6.7.8... Timer 9... AND circuit 10... Shift register unit 11... S-R latch Section 12... Head driver 13... Head coil 14... Character font read-only memory 15...
Distributed timing generation section 6.17, ... timer 9 ... print data distribution section 0 ... central processing unit 2 ... AND circuit 3 ... head driver 4 ... head coil 18 ... oscillator 1...Input/output section

Claims (2)

[Claims] (1) A print head control device mounted on a carriage that performs printing by supplying drive signals corresponding to each pin in a row of pins of the print head that is inclined with respect to the direction perpendicular to the direction of movement of the carriage. and a print data output means for outputting print data, and a first drive signal synchronized with the rising timing of the energization time of the print head, the period of which is the time difference between drive signals for each adjacent pin that corrects the inclination of the pin row. a first timer that generates a timing signal; and a second timing signal that has a period equal to the time difference between drive signals for each adjacent pin that corrects the inclination of the pin row, and is synchronized with the fall timing of the energization time of the print head. a first shift register that uses the first timing signal as a shift clock to shift the print data; and a second timer that uses the second timing signal as a shift clock to shift the print data. a shift register, and an output of the first shift register;
A print head control device comprising: drive means for driving the print head by an output of the second shift register. (2) The period of the first timer and the second timer changes in response to changes in a plurality of fonts or the number of characters per unit length. print head control device.