JPH0422651A - Printing head controller - Google Patents

Abstract

PURPOSE:To reduce a printing noise and to decrease the capacity of a power source by driving pins of a pin row via timing data of printing of all the pins to be corrected at the inclination of the row of inclined printing head according to select data. CONSTITUTION:Dot pattern of a head is so formed that odd pins of 24 pins is arranged as a first row, even pin are arranged as a second row, pin N and pin (N+2) of 12 pins of each row are deviated in l/l20*l/12 inch printing line direction so that the pins of the same row are not simultaneously driven. Here, l/120 inches are dot interval of a character. Further, the pins of the first and second rows are arranged such that a pin N and pin (N+l) are disposed at intervals of different lengths of integer number of times of l/l02*l/12 inches so as not to be simultaneously driven. That is, the pins are dispersively printed at 24 timings of 24 pins of a printing head at a distance of moving l/120 inches of the head so that the pins are not simultaneously turned ON.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a print head control device for a dot matrix printer.

Conventional technology In recent years, in dot matrix printers, the dots have been tilted to avoid noise caused by each dot hitting the dots at the same time, to avoid magnetic interference when using a large capacity power supply or electromagnetic force, and to achieve high-density packaging. A distributed print head is used in which printing is performed by supplying a driving force 7g according to the dots of the print head arranged in a row, and a print head control device for the distributed print head is used.

A conventional print head control device will be described below.

FIG. 8(a) shows the dot pattern of a conventional 24-pin wire dot head. Figure 8(b) shows a dot pattern of a distributed print head in which dots are arranged in a slanted manner.
) is another example of a distributed printhead dot pattern.

9 is a drive timing chart of the 24-pin wire dot head, and FIG. 9(a), FIG. 9(b), and FIG. 9(c) are respectively FIG. ) corresponds to the dot pattern head shown in FIG. 8(C). 8th
In the dot pattern of FIG. 9(a), as shown in FIG. 9(a), timing T1 determines the spacing between dots that make up the character, and timing T2 determines the energization time of the head coil that drives the pins of the head. However, in the dot pattern of FIG. 8(b), the drive timing is different for each pin as shown in FIG. 9(b), so the timer that generates timing T1 and timing T2 may be In addition, a timer is required to generate a timing T3 that determines the delay time for each dot according to the slope of the dot array, and it is necessary to delay all the drive timings of the 24 pins by the timing T3. In the dot arrangement of FIG. 8(C), the control circuit is simplified by delaying the drive timing for each group of six pins as shown in FIG. 9(C).

FIG. 10 is a block diagram of a conventional print head control device having the dot arrangement shown in FIG. 8(b). In FIG. 10, reference numeral 22 denotes a character font read-only memory (hereinafter referred to as character font RO) in which character font data is written.
It is abbreviated as M. ), 23 is a distributed timing generation unit that generates timing for distributing print data, and a timer 24 that generates clocks having timings of T1 and T2 as shown in FIG. 9(b), and a clock having timing of T3. Generating timer 25 and these timers 24 .
It consists of an oscillator 26 which operates 25. 27 is a shift register section that delays the print data read out from the character font ROλ (22); 28 is a central processing unit (hereinafter abbreviated as CPU) that controls the character font ROM;
22, distributed timing generation section 23, shift register section 2
7 is an input/output section (hereinafter abbreviated as T10 section).

) 29. 30 is an AD circuit of 24 @, which takes the AND of the print data for 24 pins from the character font ROM 22 and the output W of the timer 24, respectively. 31
is a head driver that applies a pulse signal to the head coil 32.

The operation of the print head control device configured as described above will be described below.

The CPU 28 uses the timer 24 to output the timing signal W (hereinafter abbreviated as shift data) of the first pin shown in FIG. 9(b).

) is always notified of the fall timing of
reads the print data for 24 pins from the character font ROλ422 and sends it to the AND circuit 30 according to the falling timing of the shift data.
D is taken and sent to the shift register section 27. Also timer 25
Then, the character mode data X is received from the CPU 28, and a clock t (hereinafter abbreviated as shift clock) having a timing having a period of T3 in FIG. 9(b) corresponding to the printing mode is sent to the shift register section. Send to 27th. The shift register section 27 exposes the output word from the AND circuit 30 to the shift clock t and transfers it from pin 1 to pin 2 in FIG. 9(b).
A drive signal for the 4 pins is generated and sent to the head driver 31. The head driver 31 drives the head by applying a pulse voltage to the head coil 32 in response to a drive signal from the shift register section 27 .

The frequency of shift clock t changes depending on the printing mode for various characters, but in order to maintain the timing of T2, T2 must be an integral multiple of shift clock t, so it is inevitable that the frequency of shift clock t will change. It becomes necessary to increase the frequency, that is, to provide the shift clock t obtained by subdividing the T3 period to the shift register section 27. For this reason, the shift register of the shift register section 27 was missing llfi stages.

Problems to be Solved by the Invention However, in the conventional configuration, the number of shift registers and the like is large in the distributed timing generation section, and the number of gates is large. If a dot pattern configuration as shown in FIG. 8(C) is used to reduce the number of gates, the effects of printing noise reduction, power supply capacity reduction, etc. will be drastically reduced.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides all pins that are mounted on a carriage and correct the inclination of the pin row of the print head that is inclined with respect to the direction perpendicular to the direction of movement of the carriage. a memory in which a pair of timing data for printing and select data indicating which position in a dot row the timing data corresponds to is written; a calling means for calling the information written in the memory; and a calling means for calling the information written in the memory; and a decoder that converts the timing data called from the input signal into a drive timing signal for each pin in the pin array according to the select data.

Function: With the above-described configuration, the present invention can correct the inclination of the dot rows arranged in the vertical direction of the print head without using a timer circuit.

Embodiment FIG. 1 is a block diagram of a print head control device in an embodiment of the present invention.

In Fig. 1, 1 is a central processing unit (hereinafter abbreviated as CPU), 2 is an input/output unit (hereinafter abbreviated as I10 unit) that serves as an interface between each device, and 3 is a memory only for reading character fonts. (hereinafter abbreviated as character font ROM).

4 is an oscillator, and 5 is an address counter which is driven by a basic clock C generated by the oscillator 4 and outputs a print data request interrupt signal d to the CPUI. 6 is a magnitude comparator that outputs print mode data f for switching character quality from the CPU 1 and output e from the address counter 5.
Compare the output signal g to the address counter 5.
Output. 7 is the output e and CP of the address counter 5
Print mode data h for switching character quality from U1
This is a distributed timing generation unit that outputs drive timing signals for all printing pins.

8, 9, and 10 are the output e1 of address counter 5, respectively.
Data m1 is obtained by delaying print data mo from the CPUI by one data period for one bit string, data m2 is data m1 is delayed by one data period, and data is data m2 is delayed by one data period. A latch section 11 is composed of a flip-flop that outputs data ml, m2 .
m3 is a data selector that selects m3 by a select signal n from the CPU 1; 12 is a latch unit that binds the output i of the data selector 11 as input data; and uses the output p of the distributed timing generator as a latch clock; 13 is the output of the distributed timing generator 7. This is an AND circuit which performs an AND operation between p and the output j of the latch section 12 and outputs a head drive fR number q.

A head driver 15 applies a pulse signal to the head coil 16 based on the output q of an AND circuit.

FIG. 2 is a block diagram of the distributed timing generation section 7.

In FIG. 2, 17 is a distributed timing read-only memory (in which the encoded distributed timing is written).
Hereinafter, it will be abbreviated as distributed timing ROM. ), the distributed timing for 24 pins is read out using the output e of the address counter 5010 bits and the print mode data h for switching character quality from the CPUI as addresses. 18
is the distributed timing R composed of flip-flops
The latch part that latches the output of OM17, 19.20 is 5
Decoders 21-1 to 21-24 are 24 flip-flops that produce 24-bit individual signals from a bit-encoded input signal.

The operation of the print head control device configured as described above will be explained below.

FIG. 3 shows a dot pattern of a head controlled by a print head control device in an embodiment of the present invention. In Figure 3, the dot pattern of the head is such that among the 24 pins, the numbered pins are placed in the first row, and the even numbered pins are placed in the second row, and among the 12 pins in each row, the pins in the same row are not driven at the same time. Pin N and pin (N+2) are 1/120 * 1/
It is shifted by 12 inches in the printing line direction. Here 1/120
An inch is the distance between r#11 dots of a character. Furthermore, to prevent pins in the first and second rows from being driven at the same time, pin N and pin (N+1) are spaced at a length different from an integral multiple of 1/120*1/12 inch. There is. That is, the 24 pins of the print head are distributed at 24 timings to perform printing during the distance that the print head moves by 1/120 inch so that each pin is not turned on at the same time.

FIG. 4 is a timing chart, and D1 to D7 are the output fj of the distributed timing ROM 17, and P1 to P
24 indicates the timing of the output signal of the distributed timing generator 7, which is the drive timing signal for all 24 pins.

Di and D2 are drive timer No. 948 P1 to P, respectively.
24 rising and falling timing, D
3 to D7 are select signals used by the decoder to select which of the timings P] to P24 the timings Di and D2 correspond to.

For example, regarding the drive timing signal P1, first, Dl
At the first pulse of , D7 to D3 are 0, O, O
, 0, 1, and this select number 15 causes the decoder 19 to send the clock signal to the flip-flop 21-
1 to set Pl to high level, and then at the third pulse of D2, D7 to D3 are set to O, O, O, 0, 1, and this select No. 15 causes the decoder 20 to clear No. 18. is applied to the flip-flop 21-1 to set Pl to low level. Other drive timing signals P2 to P2
4 is similarly generated from D1 to D7.

FIG. 5 is an address map of the distributed timing ROML7. The printer's character font is draft and NLQ (N
2 types of ear Letter Quality), number of letters per inch is 10.12.15.17 cp
4 types of i, 2 types of head print direction: forward direction (hereinafter abbreviated as Go) and reverse direction (hereinafter abbreviated as RETURN), and 400 in hexadecimal for each.
Data is stored for each address, up to a total of 3FFF addresses.

These mode selections are made using print mode data h. Although the printing interval is different for each mode, the magnitude comparator 6 loads the address counter 5 to all zeros after the time set by the CPUI according to each mode. This time is 1024 μs at maximum, and 1 μs per address.

FIG. 6 is a timing chart of the FIFO section 14.

The CPU 1 calls the character font of the character to be printed from the character font ROM 3 and sends it to the FIF as print data mo.
The output timing of this print data mo is determined by the CPU 1 giving the print interval time corresponding to the print mode of the printer as a count value f to the magnitude comparator 6: A comparator 6 compares this count value f with the output e of the address counter 5, and if they match, the count value of the address counter 50 is set to zero. For example, if the CPU 1 sets the count (a f to 800) in the magnitude comparator 6, the address counter repeats counting from O to 800 and outputs an interrupt signal d to the CPUI every 800 counts. A new print data mo is output each time . As shown, there is a printer with a printing dot spacing of 1/432 inch.By the way, the dot pattern spacing of the head is 1/12 inch.
Since it is 0 inch, the dispersion timing to divide 1/120 inch into 24 is that the printing dot interval from the CPUI is 1/43.
It spans four data pieces of 2-inch print data mo. In order to support these printing modes, first, ml, m2 . 1 each like m3
Data, 2 data, and 3 data delayed data are obtained and input to the data selector 11, so that data j selected by the select signal n from the CPU 1 is exclusively used for t. In the case of FIG. 6, the print data for pins 1 to 7, pins 8 to 14, pins 15 to 20, and pins 21 to 24 are mO, ml, m2. Compatible with m3. Here, if the print data interval is fixed at 17,120 inches, the data selector 11 and latch portions 8, 9, and 10 are not necessary.

The print data mO of each of the 24 pins input to the latch unit 12 and the output i of the data selector 11 are
It is latched by distributed timing signals P1 to P23 shown in the figure. Further, by ANDing the 24-bit latched data j of each pin and the fractional timing signal p in an AND circuit 13, a head drive signal q is obtained.

Based on this head drive signal q, the head driver 15 applies a pulse signal to the head coil 16 to drive the head.

In the present invention, by using a distributed timing ROM,
Conventional circuits require approximately 7,000 gates compared to 130 gates.
0 Kate + ROM T sumu. FIG. 8 shows the effect on noise of fraction printing using the circuit of the present invention. There is a noise reduction effect of 7 dB at 1/4 dispersion and 10 dB at 1/24 dispersion.

Effects of the Invention As described above, the present invention provides timing data for printing on all pins that corrects the inclination of the pin row of the print head mounted on the carriage and inclined with respect to the direction perpendicular to the moving direction of the carriage. A memory in which the timing data is written in pairs with select data indicating which position in the dot string it corresponds to, a calling means for calling the information written in the memory, and timing data called out from the memory by the calling means. By being equipped with a decoder that sets the drive timing of each pin in the pin row according to the select data, it is possible to correct the inclination of the dot row arranged in the vertical direction of the print head without using a timer circuit. The inclination of the dot rows arranged in the vertical direction of the print head can be corrected without using a ROM table, the number of gates can be reduced, and it is easy to support different models by changing the ROM table.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a print head control device according to an embodiment of the present invention, FIG. 2 is a block diagram of a distributed timing generator 7, and FIG. 3 is a block diagram of a print head control device according to an embodiment of the present invention. Figure 4 of the Dot Butters head is the distributed timing RON (17
The timing chart of O part 14 shows the timing of the output signals D1 to D7 and the output No. 13 P1 to P24 of the distributed timing generation part 7 which is the drive timing signal of all 24 pins. Head drive timing chart, 1st
FIG. 0 is a block diagram of a conventional print head control device. 1... Central processing unit i2... Input/output unit 3... Character font read-only memory 4... Oscillator 5... Address counter 6... Magnitude comparator 7... Distributed timing generation unit 8. 9.10... Latch section 11... Data selector 12... Latch section 13.
...AND circuit 14...FIFO section 15...
Head driver 16... Head coil 17... Dedicated memory for reading distributed timing 18... Latch section 19.20... Decoder 21-1 to 21-24... Flip-flop 22...
・Character font read-only memory 23...Distributed timing generation unit 24...Timer 25...Timer 26...
・Oscillator 27...Shift register section 28・
...Central processing bag] 29...Input/output section 30...
AND circuit 31...head driver 32...
Name of Head Coil Agent Patent Attorney Shigetaka Kno One Idiot Figure Figure P2+ Figure "-]-"-] 111 Law "Figure Frequency fl-1z) Figure\(a) (b) ( C)

Claims (1)

[Claims] This device is mounted on a carriage and controls the print head for printing by supplying drive signals corresponding to each pin of a pin row of the print head that is inclined with respect to the direction perpendicular to the direction of movement of the carriage. a memory in which a pair of timing data indicating the timing of printing of all pins for correcting the inclination of the pin array and select data indicating the position of the dot array to which the timing data corresponds is written; calling means for calling information written in the memory; a decoder for making the timing data read from the memory by the calling means into a driving timing signal for each pin of the pin array according to the select data; and an output of the decoder. and a drive means for driving the print head.