JPH04835B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a print control device for a dot matrix type serial printer.

For example, in a wire dot matrix type impact serial printer, in order to increase the printing speed, the character pattern structure is changed from the character pattern shown in FIG. 1A to the character pattern shown in FIG. 1B.
We try not to hit the same pin in succession and print in thinned out format.

A timing chart for printing the pattern of FIG. 1A is shown in FIG. 2A, and a timing chart for printing the pattern of FIG. 1B is shown in FIG. 2B. In FIGS. 2A and 2B, signal FIO is an excitation signal for the print head and serves as a gate signal for data signals D0, D1, . . . , D7, . . . for each print pin. Then, when both the data signal and the excitation signal are at a low level, the driving element of the printing pin is excited. In FIGS. 2A and 2B, the case of the data signal D7 of the seventh pin is shown, and the time during which the data signal D7 is at a low level is the excitation time width T1 of the seventh pin. Further, the period of the excitation signal FIO is T in the case of FIG. 2A, but T/2 in the case of FIG. 2B, indicating that printing can be performed at twice the printing speed.

However, as shown in FIG. 3, due to the characteristics of various print heads, if the excitation time width T1 of the drive element of the print pin exceeds 1/2 of the period T, for example, as shown in the data signals Dn and Dm. In the conventional system, it was not possible to synchronize the excitation of each printing pin with a single excitation signal because the excitation times with different timings of going low level overlap. In other words, the next print data comes before the print of the previous column is finished. For this reason, it has not been possible to perform thinning printing at a printing speed twice the normal printing speed.

This invention was made in view of the above-mentioned circumstances, and in a dot matrix type serial printer, even if the driving time for the printing element exceeds 1/2 of the cycle of the printing head, the printing speed can be maintained at the normal printing speed by thinning printing. An object of the present invention is to provide a printing control device that can print at twice the speed of the printing speed.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a schematic diagram of an embodiment of the present invention. In the figure, 1 is a microprocessor, which has the function of controlling the entire serial printer. 2 is a programmable counter to which initial count data is supplied by the microprocessor 1, and when the signal PEN indicating the printable state becomes high level, the clock signal is output.
In this embodiment, after a predetermined number of pulses on CLK have been counted, the output signal CTO is set to a high level after a time T2. 3 is also a programmable counter, and initial count data is supplied by the microprocessor 1. When the signal CT0 becomes high level, after counting a predetermined number of pulses in the clock signal CLK, in this embodiment, T3 Output signal CT1 after time
Then, a low-level pulse (hereinafter referred to as a negative pulse) is generated. 4 is also a programmable counter, and when the signal PEN indicating the printable state becomes high level, the clock signal
After counting a predetermined number of pulses on CLK,
In this embodiment, a pulse (hereinafter referred to as a negative pulse) which becomes a low level in the output signal CT2 is generated after time T3. Reference numeral 5 denotes a first latch circuit, in which print data for one vertical column of a print pattern sequentially output from the microprocessor 1 is latched by a signal SET output from the microprocessor 1. 6 is a second latch circuit, and the data output from the first latch circuit 5 is latched by a negative pulse of the signal CT1. 7 is monostable, signal CT
It has a function of keeping the excitation signal FIO at a low level for at least T3 time or more in synchronization with the pulse that becomes a low level in 2. 8 ₁ , 8 ₂ , . . . are NOR circuits, and the first bit data signals R11 and R21 in the output data of the first and second latch circuits are input to the NOR circuit 8 ₁ . The second bit data signals R12 and R22 are input to the NOR circuit ₈₂ , and the following NOR circuits are also configured in the same manner. 9 ₁ , 9 ₂ ... are gate circuits, gate circuit 9
₁ has a function of setting the output signal D10 to a low level state when both the output signal of the NOR circuit ₈₁ and the excitation signal FIO are at a low level state. Gate circuit 9 ₂ is the output signal of NOR circuit 8 ₂ and excitation signal FIO
It has a function of setting the output signal D20 to a low level state when both are at a low level state, and the following gate circuits also have a similar function. Signal D1
0, D20, . . . are signals that determine the excitation time width for the first, second, .

Next, the operation of the above embodiment will be explained using the timing chart shown in FIG. When the carriage on which the print head is mounted moves at a constant speed and becomes ready for printing, the signal PEN goes high. Further, the clock signal CLK is constantly output. Therefore, the counter 2 sets the output signal CT0 to a high level after a time T2 after the signal PEN becomes a high level. When the signal PEN becomes high level, the counter 4 starts counting operation and generates a negative pulse in the output signal CT2 after time T3. Also, the signal
In synchronization with CT0 becoming high level, counter 3 starts counting operation and generates a negative pulse in output signal CT1 after time T3. Furthermore, the microprocessor 1 outputs the signal SET every time it receives a negative pulse in the signal CT2.

This signal SET causes the first latch circuit 5 to latch the output print data of the microprocessor 1 (for example, data 1 in the timing chart of FIG. 4). Furthermore, the data latched in the first latch circuit 5 is latched in the second latch circuit 6 by a negative pulse in the signal CT1 delayed by approximately T2 time from the signal SET. Then, an operation similar to this operation is repeated. That is, if print data 1, 2, 3, etc. are latched in the first latch circuit 5, the data 1, 2,..., latched in the first latch circuit 5 are latched in the second latch circuit 6 with a delay of approximately T2. It will be latched.

Therefore, for example, when the data for the first pin of data 1 is "1", the first bit data signal R11 of the first latch circuit 5 becomes high level for time T3, and the second latch circuit 6 becomes high level. The first bit data signal R21 becomes high level with a time lag of T2. Therefore, the output signal of the NOR circuit ₈₁ is at a low level for the time T2+T3. On the other hand, the excitation signal FIO is brought to a low level state by the negative pulse of the signal CT2. Therefore, when the print data for the first pin is "1", the output signal of gate ₉₁ is T2+ in synchronization with the negative pulse of signal CT2.
Low level for T3 hours. Therefore, it is possible to excite the drive element for the printing pin beyond 1/2 of the synchronization T.

Further, when the print data for the second pin is "1", in the same manner as above, the output signal D20 is synchronized with the next negative pulse of the negative pulse for data 1.
is kept at low level for T2+T3 time. For this reason,
Between signals D10 and D20, data 1 and data 2
There is an overlapping time when the T2 time is low level, but there is no interruption in the data and it is exactly the first time.
It is possible to print a pattern as shown in Figure B.

That is, in this embodiment, the first and second two
The latch circuits 5 and 6 are used to hold print data for a period longer than the timing at which the next print data is output, and during the holding period, a print element drive signal is generated. Since the latch timings of the first and second latch circuits 5 and 6 are different from each other, the same print data is latched for a long period corresponding to the time difference. For this reason,
For example, if the print data is print designation data of "1", even if the latch output of the first latch circuit 5 changes from "1" to "0", the latch output will remain unchanged for the period of latch timing deviation from that point. After a delay of (T2), the latch output of the second latch circuit 6 is changed from "1" to "0". Therefore, the drive signal for printing the print data of "1" is generated for a period longer than the print data generation time interval (T3) without being affected by the next input print data. . In this way, the drive signal to each printing element is generated according to the value of the corresponding bit data in the print data, and the drive signal for printing data "1" is generated at the print data generation time interval ( T3) occurs over a longer period of time. Therefore, even if the driving time for the printing element exceeds 1/2 of the cycle of the print head, continuous print data of "1" can be printed in the pattern shown in FIG. 2B, that is, "1", " By thinning out the print data of "0", "1", and "0", the print data of the thinning pattern can be printed at twice the normal printing speed.

In the above embodiment, a dot matrix type impact serial printer has been described, but the present application can also be applied to a dot matrix type non-impact serial printer. That is, the present invention can be applied by applying the output signals D10, D20, . . . as drive signals to other printing elements other than the excitation type printing pins. Further, by setting the T2 time in the above embodiment to "0", the pattern shown in FIG. 1A can also be printed.

As described above, according to the present invention, in a dot matrix type serial printer, the driving time for the printing element is 1/2 of the period of the printing head.
It is possible to provide a printing control system that can perform printing at twice the normal printing speed by thinning printing even when the printing speed exceeds the normal printing speed.

[Brief explanation of drawings]

Figure 1A is a diagram showing a normal printing pattern.
Figure B is a diagram showing the printing pattern of thinning printing, the second
Figure A is a timing chart when printing the pattern shown in Figure 1A using the conventional method, Figure 2B is a timing chart when printing the pattern shown in Figure 1B using the conventional method, and Figure 3 is a timing chart when printing the pattern shown in Figure 1B using the conventional method. FIG. 4 is a schematic diagram of an embodiment of the present invention, and FIG. 5 is a timing chart for thinning printing in the same embodiment. 1... Microprocessor, 2, 3, 4... Programmable counter, 5... First latch circuit,
6... Second latch circuit, 7... Monostable,
8 ₁ , 8 ₂ ... NOR circuit, 9 ₁ , 9 ₂ ... gate.

Claims (1)

[Claims] 1. In a dot matrix type serial printer, print data sequentially generated at predetermined time intervals is input, and a first latch circuit that latches and outputs the print data at a timing synchronized with the generation timing; a second latch circuit that latches and outputs the output data from the first latch circuit at a timing delayed by a predetermined period from the latch timing of the first latch circuit; It is characterized by comprising a plurality of output circuits each receiving corresponding bit data and generating a drive signal to each corresponding printing element when at least one of the input bit data is data designated for printing. Printing control device.