JPH0596791A - Print head control system - Google Patents

Abstract

PURPOSE:To reduce a scale of a circuit in a printer in which the width of a printing pin drive pulse varies in accordance with a printing condition. CONSTITUTION:Upon reception of an on-time signal I, the output of a print head driver rises, and upon reception of an on-time signal II, the output falls. An A-side counter is started in synchronism with an odd-numbered delay clock. A B-side counter is started in synchronism with an even-numbered delay clock. When the value of the A-side counter reaches Ni (i=1, 2,..., 4), a condition pulse is outputted from the i-th A-side output terminal. On the B side, a similar operation is conducted. With a select signal 1, a condition pulse group on the A side is selected. With a select signal O, a condition pulse group on the B side is selected. A condition pulse conforming to a printing condition is selected out of the selected condition pulse group to be outputted as an on-time signal II.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention requires the width of a pulse applied to a print head to be different depending on whether it is single-shot printing, the beginning of continuous printing, the middle of continuous printing, or the end of continuous printing. The present invention relates to a printer device, for example, a printer device having a piezoelectric head.

[0002]

2. Description of the Related Art FIG. 7 is a diagram showing a control block of the entire printer. In the figure, 1 is a processor, 2 is a program ROM, 3 is a work RAM, 3a is print data,
Line buffer, 4 interface control unit, 5 mechanical state monitoring unit, 6 mechanical control unit, 7 print head control unit, 8 mechanical driver, 9 print head driver,
10 is a paper feed motor, 11 is a carrier motor, 12
Indicates other motors, and 13 indicates a print head.

The processor 1 executes a program stored in the program ROM 2. Program ROM
There are various programs in 2. Work RAM
In 3, the temporary data is stored. The print data line buffer 3a also exists in the work RAM 3. The interface control unit 4 is connected to a main body device (not shown) via an interface cable, receives data from the main body device, and transmits data to the main body device.

The mechanical state monitoring section 5 monitors the signals from the paper sensor, the signals from the mechanical sensor, and the signal from the encoder, and notifies the processor 1 when the signal state changes. Further, the mechanical state monitoring unit 5 generates the print trigger CK (clock) based on the position information from the encoder. The print trigger CK is sent to the print head controller 7. The mechanical control unit 6 outputs drive signals to the paper feed motor 10, the carrier motor 11, the other motors 12, etc. based on the command from the processor 1. The drive signal output from the mechanical control unit 6 is sent to the paper feed motor 10, the carrier motor 11, the other motors 12 and the like via the mechanical driver 8.

The print head controller 7 generates an on-time signal I and an on-time signal II for driving the print head based on the received print data, and sends these signals to the print head driver 9. The print head driver 9 switches the output from the low level to the high level when receiving the on-time signal I, and switches the output from the high level to the low level when receiving the on-time signal II. The output of the print head driver 9 is sent to the print head 13. The print head 13 is, for example, a piezoelectric head having 24 pins arranged in a four-row zigzag pattern.

The operation of the printer device shown in FIG. 7 will be described. When receiving the print command from the interface, the processor 1 edits the print data for one line in the print data line buffer 3a of the work RAM 3. After that, the carrier motor 11 and the paper feed motor 10 are controlled to transfer the print data from the print data line buffer 3a to the print head controller 7 in order when printing becomes possible. The print trigger CK generated based on the position information from the encoder or the delayed print trigger CK is sent to the processor 1 as a print data request. When the processor 1 receives the print data request, it sends the next print data to the print head controller 7.

FIG. 8 is a diagram for explaining various signals in the piezoelectric printer. The print trigger clock is a basic timing signal for driving the print head, and has a certain periodicity suitable for the performance of the print head. As mentioned above,
The print trigger clock is generated based on the position information from the encoder. The delay timer signal is a signal delayed by a certain time from the print trigger clock.

The on-time signal is a logic level signal (timing signal) for driving the print head, and gives the drive on / off timing to the print head driver. There are two types of on-time signals, an on-time signal I and an on-time signal II. The on-time signal I is generated based on the print trigger clock,
The on-time signal II is generated based on the delay timer signal. Delay timer signal and on-time signal II
The time difference of is different depending on whether it is a continuous first dot, a continuous midway dot, a continuous final dot, or a single-shot dot. The continuous means that the print pin is continuously driven at every print trigger clock, and the single shot means that the print pin is not driven in the preceding and following print trigger clock cycles. As shown in the drawing, the interval between the delay timer signal and the on-time signal II is smaller than the cycle t of the print trigger clock in the case of continuous first, continuous midway, and continuous final. The interval of the on-time signal II is larger than t and smaller than 2t.

FIG. 9 is a diagram for explaining the piezoelectric head. Piezoelectric elements convert electrical vibrations into mechanical vibrations. As shown in (a) of the figure, the mechanical vibration of the piezoelectric element is amplified by the vibration amplification mechanism, and the amplified mechanical vibration is transmitted to the print pin. FIG. 6B shows the output of the driver of the piezoelectric head. When the print pulse I (charge pulse) is generated, the output of the driver rises and the print pulse II (discharge pulse) is generated. , The output of the driver falls.

FIG. 10 is a diagram showing a conventional circuit configuration example.
In the figure, 14 is a delay circuit, 15 to 18 are registers, 19 is a print data buffer, and 20 is a flip-flop.
Flops, 21 to 24 are gates, 26 to 29 are comparators, 31 to 34 are AND gates, 35 is an OR gate, 36 is a NAND gate, 37 is a JK flip-flop, 38 is a counter, 39 is a print per pin. Each shows a pulse II generation circuit. The apparatus shown in FIG. 10 exists in the print head controller 7 shown in FIG.

The delay circuit 14 corresponds to the delay timer shown in FIG. The register 15 is set with the interval value between the delay timer signal and the on-time signal II in the case of a single shot, and the register 16 is set with the interval value between the delay timer signal and the on-time signal II in the case of the continuous first. The register 17 is set with the interval value between the delay timer signal and the on-time signal II in the case of continuous continuation, and the register 18 is set with the delay timer signal and the on-time signal II in the case of continuous final.
The interval value of is set.

The print data buffer 19 is a shift register. Assuming that the illustrated print pulse II generation circuit 39 corresponds to the i-th print pin, print data for the i-th print pin is sequentially input to the print data buffer 19. Print data buffer 19
Output signal S1 indicates whether there is previous data, output signal S2 indicates whether there is current data, and output signal S1
3 indicates whether or not there is next data. Signals S1, S2, S
3 is held in the flip-flop 20. The NAND gate 36 outputs a pulse when the delay circuit 14 outputs a pulse while the output signal S2 is on. When this pulse is output, the flip-flop 20
The output signals S1, S2, S3 are taken in.

The gate 21 outputs "1" when the condition 1 is satisfied, the gate 22 outputs "1" when the condition 2 is satisfied, and the gate 23 outputs the condition 3 is satisfied. When the condition 4 is satisfied, the gate 24 outputs "1" when the condition is satisfied, and the gate 24 outputs "1" when the condition 4 is satisfied. Condition 1 is that the current dot is a single-shot dot, Condition 2 is that the current dot is the first of the continuous dots, Condition 3 is that the current dot is in the middle of the continuous dots, and Condition 4 is that the current dot is in the middle. The dot is the last of the continuous dots.

When the NAND gate 36 outputs a negative-going pulse, the flip-flop 37 is set and the counter 38 starts counting time. The comparator 26 compares the content of the register 15 with the count value of the counter 38, and outputs "1" if they match. Comparators 27, 28,
29 also performs the same operation. When the comparator 26 outputs "1", the counter 38 returns to the initial value and is stopped.

The AND gate 31 outputs "1" when both the comparator 26 and the gate 21 output "1". The AND gates 32, 33 and 34 perform the same operation. The outputs of the AND circuits 31 to 34 are OR circuits 35.
Entered in. The output of the OR gate 35 is the print pulse II.
(Synonymous with on-time signal II).

[0016]

As described above, the time difference between the delay timer signal and the on-time signal II differs depending on whether it is the beginning of continuous printing, the middle of continuous printing, the end of continuous printing, or single-shot printing. In some cases, the difference is greater than the print cycle. In the conventional method, it is necessary to have a timer for counting the time difference as described above for each print pin, and therefore the circuit scale is enormous. The present invention has been made in view of this point, and an object thereof is to reduce the circuit scale of the circuit for generating the on-time signal II of the serial printer.

[0017]

FIG. 1 illustrates the principle of the present invention. The print head control method of the present invention includes a print head having a plurality of print pins, a print head control unit that outputs an on-time signal I and an on-time signal II when the print pins are driven, and an on-time signal I. Is a print head control method in a printer device having a print head driver that raises the print pin drive signal when the output is output, and turns off the print pin drive signal when the on-time signal II is output. The print head controller has a pulse generator and a print pulse output unit for each print pin. The pulse generator includes a delay circuit for delaying the print trigger clock, two counters, and a delay circuit. Each time the delay clock is output, the logical value of the timer select signal is switched, the counter on the A side is activated in synchronization with the odd-numbered delay clock, and the even-numbered delay clock is activated. It has a switching circuit that activates the counter on the B side in synchronization with the extended clock, four output terminals on the A side, and four output terminals on the B side, and the value of the counter on the A side is N _i ( i = 1, ..., and outputs the condition pulse to the i-th output terminal of the a side when it is 4), the i-th output terminal of the B-side when the value of the B-side counter becomes N _i And a condition pulse generation circuit for outputting a condition pulse to the print pulse output unit for each print pin, when the delay clock is generated under the condition of dot printing,
When the select signal storage means for fetching the timer select signal and the select signal output from the select signal storage means have one logical value, the condition pulse group on the A side is selected, and when the select signal has the other logical value, B is selected. Group selecting means for selecting the condition pulse group on the side, and one condition pulse is selected from the selected condition pulse groups based on the printing conditions, and the selected condition pulse is used as the on-time signal II. It has a condition pulse selecting means for outputting.

[0018]

The counter on the A side is cleared before the odd-numbered delayed clock is generated, and starts counting time when the odd-numbered delayed clock is generated. The counter on the B side is cleared before the even-numbered delay clock is generated, and starts counting the time when the even-numbered delay clock is generated. Each of the A-side counter and the B-side counter can count up to 2t. However, t is the cycle of the print trigger clock.

When the value of the counter on the A side reaches N ₁ , condition pulse 1 is output from the first output terminal on the A side, and A
When the value of the counter on the side becomes N ₂ , the condition pulse 2 is output from the second output terminal on the side of A, and when the value of the counter on the side of A becomes N ₃ , it is output from the third output terminal on the side of A. When the condition pulse 3 is output and the value of the counter on the A side reaches N ₄ , the condition pulse 4 is output from the fourth output terminal on the A side. N ₁ is larger than t and smaller than 2t. The same operation is performed on the B side. Condition pulse 1 corresponds to single-shot printing, condition pulse 2 corresponds to the beginning of continuous printing,
Condition pulse 3 corresponds to the middle of continuous printing, and condition pulse 4
Corresponds to the end of continuous printing.

The group selecting means selects the condition pulse group on the A side when the select signal is "1", and selects the condition pulse group on the B side when the select signal is "0". The condition pulse selecting means selects the condition pulse 1 in the case of single-shot printing, the condition pulse 2 in the beginning of the continuous printing, and the condition pulse 3 in the middle of the continuous printing. When it is the last, the condition pulse 4 is selected. The selected condition pulse is sent to the printhead driver as an on-time signal II.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a block diagram showing a configuration example of a pulse generator of the present invention. In the figure, 40 is a delay circuit, 4
1 is a counter, 42 to 44 are registers, 45 to 47 are comparators, 48 to 50 are JK flip-flops, 51 is a D flip-flop, 52 and 53 are gates, 54 is an AND gate, and 55 is a switching circuit. Shows.

The circuit of FIG. 2 is a portion for generating the print pulse I. The print trigger signal is input to the delay circuit 40, and the output of the delay circuit 40 is the JK flip-flops 48 and 4.
It is input to the J input terminals of 9,50. The non-inverted output of the JK flip-flop 48 is input to the D flip-flop 51, and the output of the D flip-flop 51 is input to the upper input terminal of the AND gate 54. Further, the normal output of the JK flip-flop 48 is input to the clear terminal of the counter 41. The inverted output of the JK flip-flop 48 is input to the lower input terminal of the AND gate 54.
The output of the AND gate 54 becomes the delay CK, and the delay CK is input to the switching circuit 55. The comparator 45 compares the value of the counter 41 with the value of the register 42, and when they match, applies "1" to the K input terminal of the JK flip-flop 48.

The normal output of the JK flip-flop 49 is input to the lower input terminal of the gate 52. The normal output of the JK flip-flop 48 is input to the upper input terminal of the gate 52. The output of the gate 52 is the print pulse I
(Single shot). The comparator 46 compares the value of the counter 41 with the value of the register 43, and when they match, sets "1" to J.
It is applied to the K input terminal of the K flip-flop 49.

The normal output of the JK flip-flop 50 is input to the lower input terminal of the gate 53. The normal output of the JK flip-flop 48 is input to the upper input terminal of the gate 53. The output of the gate 53 is the print pulse I
(Continuous). The comparator 47 compares the value of the counter 41 with the value of the register 44, and when they match each other, "1" is set to J.
It is applied to the K input terminal of the K flip-flop 50.

The delay CK is input to the switching circuit 55. The timer select signal output from the switching circuit 55A inverts its value every time the delay CK is input. The counter A trigger signal is generated each time an odd-numbered delay CK is input, and the counter B trigger signal is generated each time an even-numbered delay CK is input.

FIG. 3 is a diagram showing a configuration example of the pulse generator (continuation) of the present invention. In the figure, 61 to 64 are registers, 66A to 69A are comparators, 66B to 69B are also comparators, 71 to 74 are registers, 76A to 79A are comparators, 76B to 79B are also comparators, 8
1A to 84A are JK flip-flops, 81B to 84B are JK flip-flops, 85A and 85B
Also indicates JK flip-flops, and 86A and 86B indicate counters, respectively.

FIG. 3 shows a portion for generating the print pulse II. The register 61 and the register 71 define the rise time and fall time of the print pulse II in the case of single-shot printing, and the register 62 and the register 72 indicate the rise time and fall time of the print pulse II in the first case of continuous printing. The register 63 and the register 73 define the rise time and the fall time of the print pulse II during the continuous printing, and the register 64 and the register 74 specify the print pulse during the continuous printing. It defines the rise time and fall time of II.

Since the circuit portion on the A side and the circuit portion on the B side in FIG. 3 have the same configuration and operation, only the circuit portion on the A side will be described. When the counter A trigger signal is generated, the JK flip-flop 85A is set and the counter 86A starts counting. When the value of the counter 86A becomes equal to the value of the register 61, the comparator 66A outputs "1", the JK flip-flop 81A is set, and the condition 1 pulse A rises. Counter 86
When the value of A and the value of the register 71 become equal, the comparator 76
A outputs "1", the JK flip-flop 81A is reset, and the pulse A for condition 1 falls. When the comparator 76A outputs "1", the JK flip-flop 85A is reset and the counter 86A is cleared. The register 71 has the largest value among the registers 61 to 64 and 71 to 74.

When the count value of the counter 86A and the value of the register 62 become equal, the comparator 67A outputs "1", and J
The K flip-flop 82A is set, and the pulse A for condition 2 rises. Value of counter 86A and register 7
When the values of 2 become equal, the comparator 77A outputs "1", the JK flip-flop 82A is reset, and the pulse A for condition 2 falls. The pulse A for condition 3 and the pulse A for condition 4 are generated in the same manner.

FIG. 4 is a diagram showing the signal timing of the pulse generator of the present invention. The delay CK is generated with a delay from the print trigger pulse by an amount determined by the delay amount of the delay circuit 40 and the value of the register 42. The timer select signal rises in synchronization with the odd-numbered delay CK (first is the first) and falls in synchronization with the even-numbered delay CK. The counter A trigger is generated in synchronization with the odd-numbered delay CK, and the counter B trigger is generated in synchronization with the even-numbered delay CK.

The pulse A for condition 1 rises after a time determined by the value of the register 61 after the counter A trigger is generated, and falls after a time determined by the value of the register 71.
The pulse A for condition 2 rises after a time determined by the value of the register 62 after the counter A trigger is generated, and falls after a time determined by the value of the register 72. The pulse A for condition 3 is registered in the register 63 after the counter A trigger is generated.
Rises after a time determined by the value of, and falls after a time determined by the value of the register 73. The pulse A for condition 4 rises after a time determined by the value of the register 64 and after a time determined by the value of the register 74 after the counter A trigger is generated.

The pulse B for condition 1 rises after a time determined by the value of the register 61 after the counter B trigger is generated, and falls after a time determined by the value of the register 71.
The pulse B for condition 2 rises after a time determined by the value of the register 62 and after a time determined by the value of the register 72 after the counter B trigger is generated. The pulse B for condition 3 is registered in the register 63 after the counter B trigger is generated.
Rises after a time determined by the value of, and falls after a time determined by the value of the register 73. The pulse B for condition 4 rises after a time determined by the value of the register 64 and after a time determined by the value of the register 74 after the counter B trigger is generated.

The print pulse I (single shot) rises after a time determined by the delay amount of the delay circuit 40 and the register 43 from the print trigger, and falls in synchronization with the delay CK. The print pulse I (continuous) rises after a time determined by the delay amount of the delay circuit 40 and the register 44 from the print trigger,
It falls in synchronization with the delay CK.

FIG. 5 is a diagram showing an example of the configuration of the print pulse output section for each pin of the present invention. In the figure, 89 is a print data buffer, 90 is a flip-flop, 91 to 94 are gates, 96 to 99 are selectors, 101 to 104 are AND gates, 105 is an OR gate, 10
6 is a NAND gate, 107 is a JK flip-flop, 108 and 109 are gates, 110 is an OR gate, 1
Reference numeral 11 denotes a print pulse output unit for each pin.

The print data buffer 89 is a shift register. Assuming that the illustrated print pulse output unit corresponds to the i-th print pin, the print data for the i-th print pin is sequentially input to the print data buffer 89. The output signal S1 from the print data buffer 89 indicates whether or not there is previous data, and the output signal S1
2 indicates whether there is present data, and the output signal S3 indicates whether there is next data. The signals S1, S2 and S3 are held in the flip-flop 90. NAND gate 10
6 outputs a pulse when the delay CK is input while the output signal S2 is on. When this pulse is output, the flip-flop 90 outputs the output signals S1 and S.
Take in 2, S3.

The gate 91 outputs "1" when the condition 1 is satisfied, the gate 92 outputs "1" when the condition 2 is satisfied, and the gate 93 outputs the condition 3 is satisfied. When the condition 4 is satisfied, the gate 94 outputs "1" when it is present, and outputs "1" when the condition 4 is satisfied. Condition 1 is that the current dot is a single-shot dot, Condition 2 is that the current dot is the first of the continuous dots, Condition 3 is that the current dot is in the middle of the continuous dots, and Condition 4 is that the current dot is in the middle. The dot is the last of the continuous dots.

The flip-flop 107 takes in the pulse select signal (synonymous with the timer select signal) when the state latch CK is generated. The output of the flip-flop 107 becomes the select signal. Selector 96
Is a pulse A for condition 1 when the select signal is "1"
When the select signal is "0", the condition 1 pulse B is selected. Other selectors 97 to 98
Performs the same operation as selector 96.

The AND gate 101 outputs "1" when both the selector 96 and the gate 91 are outputting "1". The AND gates 102, 103, 104 also perform the same operation. The outputs of the AND circuits 101 to 104 are input to the OR circuit 105. The output of the OR circuit 105 becomes the print pulse II (synonymous with the on-time signal II).

The gate 108 outputs a print pulse I (single shot) on condition that there is no previous data and there is current data. The gate 109 outputs a print pulse I (continuous) on condition that there is previous data and current data. The outputs of the gates 108 and 109 are input to the OR gate 110,
The output of the OR gate 110 becomes the print pulse I.

FIG. 6 is a diagram showing the signal timing of the print pulse output section of the present invention. In the uppermost row in the figure, x indicates data without dot printing, and o indicates data with dot printing. The numbers above the circles indicate the serial numbers of the data with dot printing. The delay CK is delayed from the print trigger by a time determined by the delay circuit 40 and the register 42. When a dot row as shown in the uppermost row is input to the print data buffer 89, the signals S1, S2, S3 (previous data,
The current data and the next data respectively) change as shown.

When the NAND of the signal S2 and the delay CK is taken, the result becomes the CK for status latch. When the state latch CK is generated, the timer select signal is fetched by the flip-flop 107. The output of the flip-flop 107 becomes the select signal. Condition 1 is H level (logic 1) on condition that there is no next data, there is current data, and there is no previous data. Condition 2 is H level on condition that there is next data, there is current data, and there is no previous data.
Condition 3 is H level on condition that there is next data, current data, and previous data. Condition 4 is H level on condition that there is no next data, there is current data, and there is previous data.

The first print pulse I (print pulse I with the numeral 1 added) is generated based on the second print trigger (the leftmost print trigger is the first). The first print pulse II is generated when the time based on the second delay CK becomes equal to the value of the register 61. The second print pulse I (print pulse I with the numeral 2 added) is generated based on the fourth print trigger. The second print pulse II is the fourth delay C
Generated when the time referenced to K equals the value of register 62.

The third print pulse I (print pulse I with the numeral 3 added) is generated based on the fifth print trigger. The third print pulse II is generated when the time based on the fifth delay CK becomes equal to the value of the register 63. The fourth print pulse I (print pulse I with the numeral 4 added) is generated based on the sixth print trigger. The fourth print pulse II is
The time based on the sixth delay CK is set in the register 6
It is generated when it becomes equal to the value of 4.

The fifth print pulse I (print pulse I with the numeral 5 added) is generated based on the eighth print trigger. The fifth print pulse II is generated when the time based on the eighth delay CK becomes equal to the value of the register 61.

[0045]

As is apparent from the above description, according to the present invention, since the two timers can each count up to twice the print cycle, the timing may differ by more than the print cycle due to the difference in the print conditions. Is also available. Therefore, for example, in the case of a 24-pin 4-row zigzag head, it is possible to reduce the 24 timers to 4 (2 × 2),
Since the circuit scale can be reduced, it is possible to reduce the cost by reducing the size of the gate array by several ranks.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing a configuration example of a pulse generator of the present invention.

FIG. 3 is a diagram showing a configuration example (continuation) of a pulse generation unit of the present invention.

FIG. 4 is a diagram showing signal timing of a pulse generator of the present invention.

FIG. 5 is a diagram showing a configuration example of a print pulse output unit of each pin of the present invention.

FIG. 6 is a diagram showing signal timing of a print pulse output unit of the present invention.

FIG. 7 is a diagram showing control blocks of the entire printer.

FIG. 8 is a diagram showing various signals in the piezoelectric printer.

FIG. 9 is a diagram illustrating a piezoelectric head.

FIG. 10 is a diagram showing an example of a conventional circuit configuration.

[Explanation of symbols]

61 to 64 register 66A to 69A comparator 66B to 69B comparator 71 to 74 register 76A to 79A comparator 76B to 79B comparator 81A to 84A JK flip flop 81B to 84B JK flip flop 85A and 85B JK flip flop 86A And 86B counter 91 to 94 gate 96 to 99 selector 101 to 104 AND gate 106 gate 107 flip flop 108 to 110 gate 111 print pulse output unit per pin

Claims (1)

[Claims] 1. A print head having a plurality of print pins, a print head control unit which outputs an on-time signal I and an on-time signal II when the print pins are driven, and an on-time signal I. Sometimes, when the print pin drive signal is raised, and the on-time signal II is output,
A print head control system in a printer device comprising a print head driver for lowering a print pin drive signal, wherein the print head control unit has a pulse generation unit and a print pulse output unit for each print pin. , The pulse generator switches the logic value of the timer select signal every time a delay clock is output from the delay circuit, two counters and the delay circuit that delays the print trigger clock, A switching circuit that activates the counter on the A side in synchronization and activates the counter on the B side in synchronization with the even-numbered delayed clock, four output terminals on the A side, and four output terminals on the B side. When the counter value on the A side reaches N _i (i = 1, ..., 4), a condition pulse is output to the i-th output terminal on the A side, and the counter value on the B side changes to N i. B when _i becomes A condition pulse generation circuit for outputting a condition pulse to the i-th output terminal on the side, and the print pulse output section for each print pin, when the delay clock is generated under the condition of dot printing, The select signal storage means for fetching the timer select signal and the condition pulse group on the A side are selected when the select signal output from the select signal storage means has one logical value, and B when the select signal has the other logical value. Group selecting means for selecting the condition pulse group on the side, and one condition pulse is selected from the condition pulse groups selected based on the printing conditions, and the selected condition pulse is used as the on-time signal II. A print head control method comprising: a condition pulse selecting means for outputting.