JPH0429255B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a dynamic logic circuit using complementary MOS (CMOS) transistors used, for example, to generate control signals for a CPU.

[Technical background of the invention]

Conventionally, a dynamic logic circuit used to generate control signals for a CPU is configured as shown in FIG. That is, a P channel (second conductivity type) type MOS transistor _T1 for precharging is arranged between the power supply Vcc and the logic setting section 11, and an N channel for discharging is arranged between the logic setting section 11 and the ground point. Channel type (first conductivity type) MOS
A transistor T ₂ is provided, and conduction of each transistor T ₁ and T ₂ is controlled by a common synchronizing signal. The connection point A between the transistor T ₁ and the logic setting section 11 is connected to the transistors T ₃ ,
_The transistor T ₄ is connected to the input terminal of a CMOS inverter circuit that detects whether the logic of the logic setting section 11 is established or not.
It is configured to obtain output OUT from connection point B of _T4 .

The operation in the above configuration will be explained. When the synchronization signal is at “0” level, transistor T ₁
is in the on state, the transistor _T2 is in the off state, and the connection point A is precharged to the "1" level. Therefore, the output OUT of the inverter circuit is “0”
level. During this precharge, the logic of the logic setting section 11 is determined. Then, when the synchronization signal changes from the "0" level to the "1" level, the transistor _T1 turns off and the transistor _T2 turns on. Therefore, if the logic of the logic setting section 11 is established, the connection is The charge stored at point A is discharged and its potential becomes "0", so the output signal
OUT becomes the “1” level. Also, if the logic is not established here, the connection point A maintains the precharged state, so the output signal OUT
is at the "0" level. In this way, whether or not the logic of the logic setting section 11 is established can be detected by the output signal OUT of the inverter circuit.

[Problems with background technology]

Incidentally, in such a circuit, the operating speed is determined by the discharge time of the connection point A. However, since the charge at the connection point A is discharged through the logic setting section 11 and the transistor _T2 , a relatively long discharge time is required, and therefore it is desired to speed up this circuit.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to provide a highly reliable logic circuit that is capable of high-speed operation and stable operation.

[Existing necessity of the invention]

That is, in this invention, in addition to the first configuration, a discharge assisting device is provided between connection points A and C.
By connecting a MOS transistor and controlling the discharge by feeding back the output signal OUT of the inverter circuit (logic detection means), when the logic of the logic setting section 11 is established, the logic setting section 11 and the discharging transistor _T2 are connected. In addition to the above-mentioned discharge auxiliary route,
MOS transistor and above discharge transistor _T2
The structure is such that the electric charge is discharged through a path via the .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Figure 2 shows its configuration.
In addition to the configuration shown in Figure 1 above, an N-channel type discharge auxiliary MOS transistor is connected between connection points A and C.
_T5 is provided, and the conduction is controlled by the potential of the connection point B (the output signal OUT of the inverter circuit, which acts as a logic detection means for detecting whether the logic of the logic setting section 11 is established or not).
In the figure, the same components as those in FIG. 1 are given the same reference numerals, and the explanation thereof will be omitted.

The operation in the above configuration will be explained. When the synchronization signal is at “0” level, transistor T ₁
is on, transistor _T2 is off,
Connection point A is precharged to the "1" level.
Therefore, the output signal OUT of the inverter circuit (the level at the connection point B) is at the "0" level, and the transistor _T5 is in the off state. Next, when the synchronization signal reaches the "1" level, the transistor T ₁ becomes off and the transistor T ₂ becomes on, and if the logic of the logic setting section 11 is established, the level of the connection point A decreases. It becomes “0” level. Therefore, the output signal OUT of the inverter circuit becomes "1" level, and the transistor _T5 is turned on. Then, when the synchronization signal reaches the "1" level, transistor _T1 is turned off and transistor _T2 is turned on, so that the charge at the connection point A is transferred to the transistor _T5.
and quickly discharged through T ₂ .

FIG. 3 shows another embodiment of the present invention, in which transistors T ₈ , T ₉ ,
It is equipped with a dynamic type inverter circuit consisting of _T10 . Even in such a configuration, the same effects as in the above embodiment can be obtained.

Fig. 4 shows a so-called domino circuit in which the circuit shown in Fig. 2 above is configured in multiple stages, and the output signal of the first stage is
OUT is used as an input signal to the second stage logic setting section 12. In such a circuit, the speed can be significantly increased compared to the conventional circuit.

〔Effect of the invention〕

As explained above, according to the present invention, by simply adding one MOS transistor for assisting discharge,
A highly reliable dynamic logic circuit capable of high-speed operation and stable operation can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional logic circuit, FIG. 2 is a diagram showing a logic circuit according to an embodiment of the present invention, and FIG.
4 and 4 are circuit diagrams showing other embodiments of the present invention, respectively. 11...Logic setting section, _T1 ...Precharge MOS
Transistor, T ₂ ...Discharge MOS transistor,
T ₃ ~ T ₅ , T ₈ ~ T ₁₀ ...MOS transistor, φ
...Synchronization signal.

Claims (1)

[Scope of Claims] 1. A logic setting section composed of a first conductivity type MOS transistor, a second conductivity type precharge MOS transistor that supplies a power supply voltage to the logic setting section, and this precharge MOS transistor. a first conductivity type discharge MOS transistor whose conduction is controlled by a common control signal and whose logic setting section is grounded;
Logic detection means that is supplied with a potential at the connection point between the precharge MOS transistor and the logic setting section and detects whether the logic of the logic setting section is established or not, and the connection point between the precharge MOS transistor and the logic setting section and the logic Setting section and discharge MOS
A first transistor connected between a connection point with the transistor and controlled to conduct by feeding back the output signal of the logic detection means, thereby discharging the potential at the connection point between the precharge MOS transistor and the logic setting section. If the logic of the logic setting section is established, the potential of the connection point between the precharge MOS transistor and the logic setting section is set to the logic setting section. and a first path via the discharge MOS transistor, and a discharge assisting path of the first conductivity type.
A logic circuit characterized by discharging through a second path via a MOS transistor and the discharging MOS transistor. 2 The above logic detection means is of static type.
2. The logic circuit according to claim 1, comprising a CMOS inverter circuit. 3. The logic circuit according to claim 1, wherein the logic detection means comprises a synchronous or dynamic inverter circuit.