JPH04291460A - Method and device for logical simulation - Google Patents

Abstract

PURPOSE:To improve the high speed logical simulation efficiency by omitting the processing operations which are so far carried out for each test at an initialization part and a result deciding part and at the same time to attain an optimum logical simulation environment in accordance with a test case. CONSTITUTION:A logical simulation device confirms the operation of a tested logic circuit model with use of a test program and consists of a logic circuit model to be tested, an instruction interpreter 12 serving as an actual data processor, a contact module 13 which secures a contact of information between the model 11 and the interpreter 12, and a memory 16 which stores a test program 14 and an initial/expected value table 15. Then the initial value that can offer an environment equal to the state of an initialization part carried out by the interpreter 12 whose normalcy is confirmed is recorded into the table 15 together with the expected value that can offer an environment equal to the executed state of a test part.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a logic simulation device and a logic simulation method, and particularly to a logic simulation device and method that enable high-speed and efficient logic simulation in logic simulation of a data processing device using a test program. Concerning applied and effective techniques.

0002

[Prior Art] Conventionally, as a logic simulation method using a test program, for example, Japanese Patent Laid-Open No. 59-14
As described in Publication No. 8971, there is a logic circuit model that has a slow execution speed but is the logic under test that processes the test part of the test program and calculates the operation check in detail, and a logic circuit model that has a fast execution speed and has initial settings. One example is a method of performing a logic simulation using a logic circuit model that can be operated by a machine language instruction for processing a result judgment section and a result judgment section.

For example, the environment for logic simulation performed at the device level is as shown in FIG. a communication module 3 that communicates information such as conversion;
It is composed of a memory 5 in which a test program 4 is stored.

[0004] Logic simulation is then executed in the following steps. In this case, the description will be made assuming that the initial setting section of the test program 4 holds or automatically generates the initial value and the expected value.

First, the communication module 3 executes the state setting of the instruction interpreter 2 (step 601), and transfers the operation to the instruction interpreter 2. Then, the instruction interpreter 2 reads the test program 4 from the memory 5 and executes the instructions until the instruction A indicating the end of the initial setting section is executed (steps 602 to 604). Here, command A
When executed, the communication module 3 moves the operation to determine whether the simulation should continue or end (step 605).

At this time, if the simulation is to be continued, the state setting of the logic circuit model 1 is executed (step 606).
), the operation is transferred to logic circuit model 1. Then, the logic circuit model 1 reads the test program 4 from the memory 5 and executes the instructions of the test section until instruction B indicating the end of the test section is executed (steps 607 to 609). Further, when the instruction B is executed, the operation is transferred to the communication module 3.

[0007] Subsequently, the communication module 3 executes the state setting of the command interpreter 2 (step 601), and transfers the operation to the command interpreter 2. Then, the instruction interpreter 2 executes reading of the instruction (step 602), and executes an instruction for processing the result determination section such as result determination and error analysis (step 604).

As described above, when the test program 4 consists of a plurality of tests, this series of operations is repeated for all the tests, and finally the operation is transferred to the communication module 3 to terminate the simulation when continuing the simulation. (step 605).

Next, the flow of the test program 4 will be explained with reference to FIG. In FIG. 7, the vertical direction shows time, and the horizontal direction shows the mutual processing transitions of the instruction interpreter 2, the communication module 3, and the logic circuit model 1. However, in this case, it is assumed that the test consists of test A, test B, and test C.

First, the initial setting part A71 of the test A is executed by the instruction interpreter 2, and then the test part A72 is executed by the logic circuit model 1 through the communication module 3. Thereafter, it passes through the communication module 3 and the result determination section A73 is executed by the instruction interpreter 2. In this way, the initial setting section B74, the test section B75, and the result determination section B7 of the test B
6, and initial setting section C77 of test C, test section C78,
The result determination unit C79 is similarly executed.

As described above, conventionally, the test program 4
For each test, a logic simulation method is adopted in which the initial setting section and the result judgment section are executed by the instruction interpreter 2.

0012

[Problem to be Solved by the Invention] However, in the prior art as described above, when a test program consists of a plurality of tests, the initial setting part and the result judgment part are executed by an instruction interpreter for each test unit. have to,
This poses a problem in that the execution time increases. In particular, in logic simulations in which the same test program is executed many times, the tendency for the execution time to increase is noticeable.

Therefore, the conventional logic simulation method cannot provide high-speed and efficient logic simulation using a test program.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to eliminate the need for processing of the initial setting section and result judgment section of a test program for each test unit during logic simulation, and to perform processing of the initial setting section and result judgment section of a logic circuit model. A logic simulation device that independently executes the processing of the test section of the logic circuit model under test, and achieves high speed and efficiency by reducing the execution time of the logic circuit model initialization section and result judgment section. and to provide methods.

Another object of the present invention is to provide versatility in the execution of the initial setting section and result determination section of a test program, so that processing can be performed on either a high-speed real machine or an instruction interpreter that can be operated using machine language instructions. An object of the present invention is to provide a logic simulation device and method that can realize the construction of an optimal logic simulation environment tailored to a test case.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0017]

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions will be as follows.
It is as follows.

That is, the logic simulation apparatus of the present invention includes an initial value setting section for setting an initial value and an expected value of the logic circuit model under test, and a group of instructions for testing the logic circuit model under test. A logic simulation device that confirms operation using a test program, which consists of a test section and a result judgment section that compares and analyzes expected values with the execution results of the test section. an execution means that performs the execution in advance on the logic circuit model that has been prepared; a storage means that records and holds the execution results of the initial setting section and the test section; It is provided with a setting/comparison means for comparing the result set in the circuit model and executed by the test section in logic simulation with the recorded execution result of the test section.

Further, in the logic simulation method of the present invention, a test program is executed in advance on a logic circuit model whose normality has been confirmed, and the execution result of the initial setting section is set as an initial value in the logic circuit model under test. , Furthermore, the results of executing the test section in the logic simulation and the execution results of the test section in execution are compared, and if the comparison results match, execute the next test, and if they do not match, perform the normality check. The result judgment section is executed using the confirmed logic circuit model, and the initial setting section, test section, and result judgment section are all executed repeatedly for each test.

[0020] Another logic simulation method is
If the comparison results match, only the test section is executed, and if they do not match, only the test section and result determination section are executed.

In this case, the initial setting section and the testing section of the test program can be executed by either an instruction interpreter capable of pseudo-operating the logic circuit model under test whose normality has been confirmed or by an actual data processing device. This is how it was done.

[0022] Furthermore, if the result of executing the test part in the logic simulation and the execution result of the recorded test part do not match, error analysis is performed in the communication module that communicates information about the logic circuit model and the logic circuit model under test. The test part of the test program is executed only by the logic circuit model under test and the communication module.

[0023]

[Operation] According to the above-described logic simulation device and method, by providing the execution means, the holding means, and the setting/comparing means, if the result of the setting/comparing means is a match, the next test is executed, and when the result of the setting/comparing means is a match, In this case, execute the result judgment part with the logic circuit model whose normality has been confirmed, and then repeat the process for each test to execute all the initial setting part, test part, and result judgment part, or start the test if the results match. If there is a discrepancy, only the test part and the result judgment part can be executed. Thereby, in the logic simulation, the processing of the initial setting section and the result determination section of the logic circuit model and the processing of the testing section of the logic circuit model under test can be executed separately.

In this case, by making the initial setting section and the testing section of the test program executable by an instruction interpreter or an actual data processing device, the test program can be executed with versatility. This makes it possible to construct an optimal logic simulation environment tailored to the test case.

Furthermore, by having the communication module execute only error analysis when the comparison results do not match, the process of the result judgment unit is not necessary for the logic circuit model whose normality has been confirmed, and the logic circuit model under test and the communication module are The test part of the test program can be executed using just the module. This reduces the execution time of the logic circuit model initial setting section and result determination section, and processes only the test section using the logic circuit model, thereby achieving higher speed and efficiency.

[0026]

[Example] Fig. 1 is an explanatory diagram showing the configuration and execution procedure of a logic simulation device which is an embodiment of the present invention, and Fig. 2
is an explanatory diagram showing the flow of a test program in the logic simulation device of this embodiment, FIG. 3 is an explanatory diagram showing the configuration and flow of creating an initial value/expected value table in this embodiment, and FIG. 4 is an explanatory diagram showing the flow of a test program in the logic simulation device of this embodiment. - An explanatory diagram showing the transmission information of the expected value table and the instruction interpreter. FIG. 5 is an explanatory diagram showing the relationship between the instruction interpreter, the initial value/expected value table, and the logic circuit model in this embodiment.

First, the configuration of the logic simulation apparatus of this embodiment will be explained with reference to FIG.

The logic simulation device of this embodiment is as follows:
For example, it is a logic simulation device that checks the operation of a logic circuit model under test using a test program, and includes a logic circuit model 11 that is the logic under test, an instruction interpreter (execution means) 12 that is an actual data processing device, and a logic circuit A communication module (setting/comparison means) 13 that communicates information such as status setting and format conversion of the model 11 and instruction interpreter 12, and a test program 14.
and a memory 16 in which an initial value/expected value table (holding means) 15, which is a feature of the present invention, is stored.

In other words, the initial value/expected value table 15 contains initial values that can provide the same environment as when the instruction interpreter 12 whose normality has been confirmed has finished executing the initial setting section, and This method is different from the conventional technology shown in FIG. 1 in that the expected value that can provide the same environment as the current state is recorded.

Next, the operation of this embodiment will be explained.

First, referring to FIG. 1, the execution of a logic simulation will be described assuming that the initial setting section of the test program 14 holds or automatically generates initial values and expected values.

First, the communication module 13 reads initial values from the initial value/expected value table 15 (step 101), and further sets the state of the logic circuit model 11 (step 102). At this point, the same result as the processing up to the logic circuit model state setting (step 606) described in the prior art is obtained.

Further, when the operation moves to the logic circuit model 11, the instructions of the test program 14 are read out from the memory 16 (step 103). Then, the instructions of the test section are executed until instruction B is executed (step 1
04, 105), when instruction B is executed, the operation is transferred to the communication module 13, and the expected value is read from the initial value/expected value table 15 in the memory 16 (step 1
06).

Next, the read expected value is compared with the execution result of the test section to perform a compare check (step 107). Then, if there is no error, it is determined to continue the simulation (step 108), and the logic circuit model 1
1, and the above operations are repeated from instruction reading (step 103).

On the other hand, if there is an error, the operation is transferred to the instruction interpreter 12 and the instruction is read (
Step 109). Then, when the test program 14 is read from the memory 16 and an error analysis instruction is executed, the instruction is completed (steps 110 and 111).
, the operation is transferred to the communication module 13 to execute the next test.

In this case, if you only want to check whether there is an error or not in the comparison check with the expected value (step 107), that is, if you do not need the error analysis performed in the instruction execution (step 111), directly continue the simulation. (
Step 108) can be performed.

If the test program 14 consists of a plurality of tests, this series of operations is repeated for all the tests, and finally the operation is transferred to the communication module 13 to continue the simulation and end the simulation (step 108). ).

Next, the flow of the test program 14 will be explained with reference to FIG. In Figure 2, time is taken in the vertical direction,
The mutual processing transitions of the instruction interpreter 12, the communication module 13, and the logic circuit model 11 are shown in the horizontal direction, and the test program 14 can have one or more test items, but test A is shown here. , test B and test C.

First, in test A21, the state setting of the initial value/expected value table 15 and the logic circuit model 11 (step 1) is performed.
02) enables direct execution on the logic circuit model 11. After execution, the operation is transferred to the communication module 13, and a comparison check is performed between test A22 and the expected value (step 107).
), and if there is no error, the operation is transferred to the logic circuit model 11 and tests B23 and B24 are performed in the same manner.

Subsequently, tests C25 and C26 are executed in the same manner. For example, if an error is found in the comparison check with the expected value, the operation is transferred to the instruction interpreter 12, and test C2 is executed.
Execution of instructions for error analysis regarding 7 (step 1)
11). In this case, as described above, execution of this instruction can be omitted.

Next, a method for creating the initial value/expected value table 15 will be explained based on FIG. In this case, the initial value
It is most desirable to create the expected value table 15 when the test program 14 is debugged using the instruction interpreter 12, and this case will be described here. However, in various logical simulations,
It is possible to create the configuration using the instruction interpreter 12 and the memory 16 shown in FIG.

First, the instruction interpreter 12 can process the test program 14 at extremely high speed, and the memory 16 is composed of the test program 14 and an initial value/expected value table 15 in which initial values/expected values are stored.

First, when an instruction is read (step 301), the test program 14 is read from the memory 16 and the instruction is executed (step 302). When the processing of the initial setting section is completed, instruction A is executed, and based on the judgment of instruction A (step 303), the state of the instruction interpreter 12 at that time, that is, the initial value, is stored in the initial value/expected value table 15 in the memory 16. Record (step 304).

Further, instructions are executed for the test section (step 305), and when the processing of the expected value setting section is completed, instruction B is executed and the result is determined by the judgment of instruction B (step 306).
), the state of the instruction interpreter 12 at that time, that is, the expected value, is recorded in the initial value/expected value table 15 in the memory 16 (step 307).

[0045] Then, in determining the next test (step 308), if the test continues, the process returns to instruction reading (step 301) and repeats the series of steps for all tests, while if the test is finished, the simulation ends. .

Furthermore, for the test program 14 in which the initial setting section holds initial values and expected values in advance or automatically creates them, the initial values and expected values are stored in the memory 16 using command A (step 304). . At this time, the process of storing the data in the memory using instruction B (step 307) becomes unnecessary.

As a result, the program creator does not need to be aware of creating the initial value/expected value table 15 at all, and can debug the test program in the same way as normal test program debugging.

The initial value/expected value table 15 can be recorded on, for example, a disk device or a magnetic tape device, and then loaded into the memory 16 in the same way as the test program 14.

Next, the configurations of the instruction interpreter 12 and the initial value/expected value table 15 will be explained with reference to FIG.

The instruction interpreter 12 stores control information 41 of the instruction interpreter 12 during execution of instruction A (step 302), general-purpose registers 42 and 43, and buffer memory 4.
4 and the main memory 45 are stored in the memory 16 (step 304), and stored in the initial value/expected value table 15 provided in the memory 16 and having the same contents as the instruction interpreter 12. Also, when executing instruction B (step 3
05) is also possible.

Next, according to FIG. 5, the instruction interpreter 12,
A logic simulation method using the initial value/expected value table 15 and the logic circuit model 11 will be explained.

First, the test program 14 executed by the instruction interpreter 12 executes the instruction A when the initial setting section 51 is finished, and sets the result (initial state of the test section), that is, the state that becomes the initial value, as the initial value/expected state. It is stored in the value table 15. After that, when the processing of the test section 52 is completed, the command B
is executed, and the state that becomes the expected value is stored in the initial value/expected value table 15. Then, when the result determination section 53 is processed, one test is completed, and this is repeated for all tests.

Next, in logic circuit model 11, the initial value
The initial value is read from the expected value table 15 and execution is performed from the initial value state. The logic circuit model 11 processes only the test section 54 of the test program 14. lastly,
The instruction interpreter 12 displays the execution results and initial values of the test section.
A comparison check is performed with the expected value read from the expected value table 15, and this is repeated for all tests. This eliminates the need for the initial setting section and result determination section that are processed for each test in the logic circuit model 11.

Therefore, according to the logic simulation device of the present embodiment, there are initial values and values in the memory 16 that can provide the same environment as the state in which the initial setting part has been executed by the instruction interpreter 12 whose normality has been confirmed. By providing an initial value/expected value table 15 in which the expected value that can provide the same environment as the state when the test part has been executed is recorded, normality can be confirmed only once when it is composed of multiple tests. This instruction interpreter eliminates the need for processing in the initial setting section and result determination section, so logic simulation can be performed efficiently and at high speed.

[0055] Above, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say.

For example, in this embodiment, a case has been described in which the instruction interpreter 12 capable of pseudo-operating a logic circuit model under test whose normality has been confirmed is used, but the present invention is limited to the above-mentioned embodiment. Rather, it can be widely applied to actual machines such as actual data processing equipment, for example. In this case, since the test program can be executed with versatility, an optimal logic simulation environment can be realized.

[0057]

[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by the typical inventions are briefly explained as follows.
It is as follows.

(1). Execution means for pre-executing a test program on a logical circuit model whose normality has been confirmed; holding means for recording and holding the execution results of the initial setting section and the test section; and the holding means for recording and holding the execution results of the initial setting section. is set as an initial value in the logic circuit model under test, and the setting/comparison means is provided to compare the result of executing the test section in logic simulation with the execution result of the recorded test section. If the results match, execute the next test, and if they do not match, execute the result judgment section using the logic circuit model whose normality has been confirmed, and repeat for each test to perform the initial setting section, test section, and result judgment. In logic simulation, it is possible to execute the initial part of the logic circuit model, or only the test part if the results match, and only the test part and result judgment part if the results do not match. It becomes possible to separately execute the processing of the setting section and the result determination section and the processing of the testing section of the logic circuit model under test.

(2). By making the initial setting section and the testing section of the test program executable by either an instruction interpreter capable of simulating operation of a logic circuit model under test whose normality has been confirmed, or an actual data processing device,
Since the test program can be executed with versatility, it is possible to construct an optimal logic simulation environment tailored to the test case.

(3). To cause a communication module that communicates information about the logic circuit model and the logic circuit model under test to only perform error analysis when the results of executing the test section in logic simulation and the execution results of the recorded test section do not match. As a result, the test part of the test program can be executed using only the logic circuit model under test and the communication module, eliminating the need for the initial setting part and result judgment part that were performed for each test. By reducing the execution time of the test section and the result judgment section and processing only the test section using a logic circuit model, it is possible to achieve high speed and improved efficiency.

(4). According to (1) to (3) above,
By simply providing a holding means whose normality has been confirmed only once, conventional technology can be maximized and changes in the logical simulation environment can be minimized, which is particularly effective when executing a test program multiple times. Logic simulation can be provided.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the configuration and execution procedure of a logic simulation device that is an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing the flow of a test program in the logic simulation device of this embodiment.

FIG. 3 is an explanatory diagram showing the configuration and flow of creating an initial value/expected value table in this embodiment.

FIG. 4 is an explanatory diagram showing an initial value/expected value table and transmission information of an instruction interpreter in this embodiment.

[Figure 5] Instruction interpreter in this embodiment, initial value/
FIG. 3 is an explanatory diagram showing the relationship between an expected value table and a logic circuit model.

FIG. 6 is an explanatory diagram showing the configuration and execution procedure of a logic simulation device that is an example of the conventional technology.

FIG. 7 is an explanatory diagram showing the flow of a test program in a logic simulation device that is an example of the conventional technology.

[Explanation of symbols]

1 Logic circuit model 2 Instruction interpreter 3 Communication module 4 Test program 5 Memory 11 Logic circuit model 12 Instruction interpreter (execution means) 13 Communication module (setting/comparison means) 14 Test program 15 Initial value/expected value table (holding means) 16
Memory 21 Test A 22 Test A 23 Test B 24 Test B 25 Test C 26 Test C 27 Test C 41 Control information 42 Register 43 Register 44 Buffer memory 45 Main memory 51 Initial setting section 52 Test section 53 Result determination section 54 Test section 71 Initial setting part A of test A 72 Test part A of test A 73 Result judgment part A of test A 74 Initial setting part B of test B 75 Test part B of test B 76 Result judgment part B of test B 77 Initial stage of test C Setting section C 78 Test section C of test C 79 Result judgment section C of test C

Claims (5)

[Claims] 1. A logic circuit model under test, an initial value setting section for setting an initial value and an expected value of the logic circuit model under test, a test section for a group of instructions for testing the logic circuit model under test; A logic simulation device that checks the operation using a test program that includes a result judgment unit that compares and analyzes an expected value with the execution result of the test unit, the logic simulation device that uses the test program to check the operation of the logic whose normality has been confirmed. Execution means for executing the circuit model in advance; holding means for recording and holding the execution results of the initial setting section and the test section; and a logical circuit model under test using the recorded execution results of the initial setting section as an initial value. 1. A logic simulation device comprising: a setting/comparison means for comparing the result of executing a test section in a logic simulation with the recorded execution result of the test section. 2. A logic simulation method for verifying the operation of a logic circuit model under test using a test program comprising an initial setting section, a test section, and a result determination section, the method comprising: verifying the normality of the test program; The execution result of the initial setting part from this execution is set in the logic circuit model under test as an initial value, and the result of executing the test part by logic simulation and the execution of the test part by the above execution. If the compared results match, execute the next test, and if they do not match, execute the result judgment section using the logic circuit model whose normality has been confirmed, and repeat for each test. Initial setting section,
A logic simulation method characterized by executing both a test section and a result judgment section. 3. A logic simulation method for confirming the operation of a logic circuit model under test using a test program comprising an initial setting section, a test section, and a result judgment section, the method comprising: verifying the normality of the test program; The execution result of the initial setting part from this execution is set in the logic circuit model under test as an initial value, and the result of executing the test part by logic simulation and the execution of the test part by the above execution. A logic simulation method characterized in that the results are compared, and if the compared results match, only the test part is executed, and if they do not match, only the test part and the result judgment part are executed. 4. The initial setting section and the test section of the test program can be executed by either an instruction interpreter or an actual data processing device capable of performing a simulated operation of a logic circuit model under test whose normality has been confirmed. The logic simulation method according to claim 1 or 2, characterized in that: 5. Communication for communicating information about the logic circuit model and the logic circuit model under test when the result of executing the test section in the logic simulation and the execution result of the recorded test section do not match. 3. The logic simulation method according to claim 1, further comprising causing a module to perform only error analysis, and executing a test portion of a test program using only the logic circuit model under test and the communication module.