CN115718685A - CPU test method, device, electronic equipment and storage medium - Google Patents
CPU test method, device, electronic equipment and storage medium Download PDFInfo
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Abstract
The embodiment of the invention provides a CPU testing method and device, electronic equipment and a storage medium, and relates to the technical field of testing. The method comprises the following steps: constructing a basic test case according to a verification scene; configuring an external source random excitation for the basic test case to obtain a random test case; controlling the CPU to execute the random test case to generate a test result; reading the state value of the state register, and judging whether the operation test is finished according to the state value; if the running test is finished, judging whether the random test case is successfully executed according to the test result, and finishing the running test when the random test case is successfully executed. Test scenes are enriched by accessing exogenous random excitation; the simulation environment is only carried out by C language, and the complexity is not high; meanwhile, the real CPU is adopted to ensure the completeness of a test scene and the reliability of a test result.
Description
Technical Field
The invention relates to the technical field of testing, in particular to a CPU testing method and device, electronic equipment and a storage medium.
Background
With the development of the semiconductor industry, the functions of the SOC (System On Chip) become more and more complex, and improving the verification efficiency and reliability of the CPU (Central Processing Unit) subsystem has an important meaning for SOC development.
The existing CPU subsystem is generally tested by a simulation environment, and a real CPU can be replaced by a virtual component, but this test mode is not highly reliable. If simulation verification is carried out under a real CPU, a driver and excitation are generated by adopting simpler C language/C + +, but the CPU does not have an effective mechanism for generating random excitation, so that the test scene under the simulation environment is single.
Therefore, a CPU testing method with high reliability and more test scenarios is needed.
Disclosure of Invention
In order to solve the above technical problem, embodiments of the present application provide a CPU testing method and apparatus, an electronic device, and a storage medium.
In a first aspect, an embodiment of the present application provides a CPU testing method, where the method includes:
constructing a basic test case according to the verification scene;
configuring an external source random excitation for the basic test case to obtain a random test case;
controlling the CPU to execute the random test case to generate a test result;
reading a state value of a state register, and judging whether the operation test is finished according to the state value;
and if the running test is finished, judging whether the random test case is successfully executed according to the test result, and finishing the running test when the random test case is successfully executed.
In an embodiment, the configuring an exogenous random stimulus for the basic test case to obtain a random test case includes:
configuring a preset seed number for the basic test case to obtain a verification test case;
verifying the verification test case;
and if the verification is passed, generating a random seed number by using an external local (time) function, and configuring the random seed number for the basic test case to obtain the random test case.
In one embodiment, the generating a random seed number using an external local (time) function includes:
acquiring first system time corresponding to the current moment;
converting the first system time to the random seed number using the local (time) function.
In an embodiment, the method further comprises:
updating the random seed number;
and generating a new test case, and executing the running test by using the new test case.
In one embodiment, said updating said random seed number comprises:
acquiring a second system time corresponding to the current moment;
converting the second system time to an update seed number using the local (time) function;
replacing the random seed number with the updated seed number.
In one embodiment, the controlling CPU executes the random test case, which includes:
and acquiring an operation code from a static memory outside the CPU so that the CPU executes the random test case according to the operation code.
In one embodiment, the step before the controlling CPU executes the random test case further includes:
compiling the random test case to obtain a compiling result and generate a compiling log;
storing the compilation result into the static memory;
and if the random test case fails to be executed, performing error troubleshooting according to the compiling log and the test result.
In a second aspect, an embodiment of the present application provides a CPU testing apparatus, including:
the construction module is used for constructing a basic test case according to the verification scene;
the configuration module is used for configuring an external source random excitation for the basic test case to obtain a random test case;
the execution module is used for controlling the CPU to execute the random test case and generating a test result;
the judging module is used for reading the state value of the state register and judging whether the operation test is finished according to the state value;
and the determining module is used for judging whether the random test case is successfully executed according to the test result if the running test is finished, and finishing the running test when the random test case is successfully executed.
In a third aspect, an embodiment of the present application provides an electronic device, which includes a memory and a processor, where the memory is used to store a computer program, and the computer program executes the CPU testing method provided in the first aspect when the processor runs.
In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program, where the computer program, when executed on a processor, executes the CPU testing method provided in the first aspect.
According to the CPU testing method provided by the application, a basic test case is constructed according to a verification scene; configuring an external source random excitation for the basic test case to obtain a random test case; controlling the CPU to execute the random test case to generate a test result; reading the state value of the state register, and judging whether the operation test is finished according to the state value; if the running test is finished, judging whether the random test case is successfully executed according to the test result, and finishing the running test when the random test case is successfully executed. Test scenes are enriched by accessing exogenous random excitation; the simulation environment is only carried out by C language, and the complexity is not high; meanwhile, the real CPU is adopted to ensure the completeness of a test scene and the reliability of a test result.
Drawings
In order to more clearly explain the technical solutions of the present application, the drawings needed to be used in the embodiments are briefly introduced below, and it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope of protection of the present application. Like components are numbered similarly in the various figures.
FIG. 1 is a flow chart of a CPU testing method provided by the embodiment of the present application;
FIG. 2 is a schematic diagram illustrating a simulation environment provided by an embodiment of the present application;
fig. 3 shows a schematic structural diagram of a CPU testing apparatus provided in an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments.
The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present application, are intended to indicate only specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another, and are not to be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application belong. The terms (such as terms defined in a commonly used dictionary) will be construed to have the same meaning as the contextual meaning in the related art and will not be construed to have an idealized or overly formal meaning unless expressly so defined in various embodiments of the present application.
Example 1
With the development of the semiconductor industry, the functions of the SOC (System On Chip) become more and more complex, and improving the verification efficiency and reliability of the CPU subsystem has an important meaning for SOC development. Based on this, the embodiment of the present disclosure provides a CPU testing method.
Specifically, referring to fig. 1, the cpu test method includes:
the CPU testing method provided by the embodiment of the application is mainly applied to a simulation environment of CPU testing and is mainly used for testing subsystems of the CPU. As shown in fig. 2, the simulation environment includes 5 components: the DUT, driver store SRAM, driver and monitoring information.
The DUT (Design under Test, design to be tested) is a part to be tested in the embodiment of the present application, and includes a CPU, an IP core, and an RTL (Register Transfer Level ) circuit of the peripheral. One of the SRAMs (Static Random Access memories ) in the peripheral device may be divided into a fixed area to be used as a Read-Only Memory (ROM) of the CPU.
SRAM is used to cache testcase. After the driver is written into the SRAM, the driver in the SRAM is read out by the simulation environment and is put into a starting ROM of a CPU, and the CPU analyzes the driver and completes execution of a command corresponding to the peripheral.
The driver includes a boot program and testcase of the CPU. Wherein the CPU boot program is implemented in assembly language. testcase is an executable C file that implements test scenarios to be simulated by invoking an external random program to generate random stimuli. Meanwhile, the function of checker (judgment) is also realized in the testcase.
The role of the checker is to monitor whether the simulation is expected. In the testcase execution process, the checker judges whether the testcase execution has errors or exceptions by reading the status register; after the command is executed, the checker performs data comparison to determine whether the testcase is executed successfully. And finally, outputting the judgment result as the simulated monitoring information.
The monitoring information of the simulation environment is divided into two parts. The first part is a CPU boot program and an assembly log file of testcase, which is used for recording the assembly information of testcase. In the Debug process, the corresponding instruction information can be obtained through the PC address of the CPU. The second part is log information generated by testcase simulation, which contains information of random excitation and the result of checker.
Based on the above components and their functions, the simulation is started. Step S110, constructing a basic test case according to a verification scene; wherein, the basic test case is an executable file.
Step S120, configuring an external source random excitation for the basic test case to obtain a random test case; the exogenous random excitation is used for improving the coverage rate of the scene and can be generated by calling an external task _ rand program. At this time, a region may be divided from the CPU peripheral SRAM to be used as a boot ROM of the CPU.
The CPU instruction set based on RISCV architecture has no random function, so this embodiment reproduces the rand random function of C language, as shown in algorithm one:
the first algorithm is as follows:
the rand random function of the C language converts the system time into a seed number through a srand function, as shown in algorithm two:
and (3) algorithm II:
void srand(unsigned int seed){
next＝seed；
}
however, the embedded CPU does not have an effective random seed generation mechanism, so the embodiment of the present application uses an external program to generate random excitation, please refer to algorithm three:
and (3) algorithm three:
it should be noted that, first, preliminary simulation verification needs to be performed on each basic test case, it is confirmed that each testcase realizes a corresponding verification scene (feature), and after each testcase flow is confirmed to be correct and a simulation result meets expectations, the next verification can be performed.
Based on this, in one embodiment, a preset seed number is configured for the basic test case to obtain a verification test case; verifying the verification test case; wherein, the preset seed number may be 0.
And if the verification is passed, generating a random seed number by using an external local (time) function, and configuring the random seed number for the basic test case to obtain the random test case.
The process of generating random seed numbers is called regression verification, and in each regression verification process, different seed numbers are adopted as basic test cases to configure random excitation so as to ensure the improvement of verification coverage rate.
In one running test, in one embodiment, a first system time corresponding to the current time is obtained; converting the first system time to the random seed number using the local (time) function.
When entering the next running test, in one embodiment, updating the random seed number; and generating a new test case, and executing the running test by using the new test case.
In one embodiment, the simulation environment performs regression verification on all test cases using perl scripts, which sequentially execute each line of commands in the file. When all testcase flows are tested to be correct, one row of commands in each line in the perl script are each testcase simulation command, and the regression frequency is 1. And after the process is confirmed to be correct and the simulation passes, performing multiple regression verifications. At this point, a command to modify the seed number (command 1) is added before each testcase simulation command to ensure that each regression produces a different random stimulus.
Command 1: perl-pi-e's |0x00000000 gaming (time) | g' testcase path
Between emulation executions, the default seed number 0x00000000 in testcase is replaced by the command with the system time as the seed number. Wherein, local (time) is a perl built-in function and can convert the system time into second output; wherein the testcase path' is a path of the testcase to be verified.
The seed number in each testcase in the simulation environment is set to 0x00000000, and other zero values in the testcase are represented by 0x0, so as to ensure that the modification of the seed number does not affect the functions of other functions in the testcase.
And then executing a testcase simulation command, wherein in different simulation time, the same testcase obtains different seed numbers so as to generate different excitations, and the scene can be completely covered after multiple regression.
After the testcase is executed, the perl command (command 2) is used for modifying the random seed number to be the default value of 0x00000000 so that the same testcase can obtain other random seed numbers next time, and therefore multiplexing of the peripheral random function is achieved.
Command 2: pal-pi-e's | randspeed = (. -) | randspeed =0x00000000 ventilated wind
Step S130, controlling the CPU to execute the random test case and generating a test result;
in an embodiment, an operation code is obtained from a static memory outside the CPU, so that the CPU executes the random test case according to the operation code.
When the simulation starts, the simulation environment acquires an operation code (opcode) from the SRAM and puts the operation code into a boot ROM of the CPU. The CPU reads the command from the boot ROM, decodes the operation code and executes the random test case.
Step S140, reading the state value of the state register, and judging whether the operation test is finished according to the state value;
in the process of executing the random case by the CPU, the checker works synchronously, and outputs necessary address and data information to a log file for the reproduction of the test scene until the simulation is finished. And meanwhile, monitoring the state value of the state register to judge whether the simulation is successful or abnormal, and storing the simulation result into log information. If the abnormity occurs, the simulation is ended in advance.
In one embodiment, compiling the random test case to obtain a compiling result and generate a compiling log; storing the compilation result into the static memory;
the makefile script can be used to compile the random test case, and the compilation result is converted into hexadecimal and stored in the SRAM. While a compilation log is generated for use by a subsequent error troubleshooting (Debug) phase.
And if the random test case fails to be executed, performing error troubleshooting according to the compiling log and the test result.
And S150, if the running test is finished, judging whether the random test case is successfully executed according to the test result, and finishing the running test when the random test case is successfully executed. And after the simulation is finished, judging whether the testcase is executed successfully according to the log information. If the simulation is successful, executing the next testcase to be verified; and if the compiling fails, performing debug according to the compiling log and the log information.
Compared with the prior art, firstly, the System Verilog and UVM components are adopted to replace the real CPU, and although the standard verification language is adopted, the reliability of the CPU simulated by the components is not high. Aiming at the defect, the simulation environment of the embodiment of the application adopts a real CPU, and the reliability of the verification result is ensured.
Secondly, a driver is generated by adopting C language/C + +, system Verilog generates random excitation, and simulation verification is performed under a real CPU, but the method increases the complexity of a simulation environment. Aiming at the problem, the driver and the random function of the verification environment are realized by C language.
Thirdly, the driver and the stimulus are generated by adopting C language/C + +, but the embedded CPU has no effective seed mechanism and cannot obtain random stimulus. To solve the problem, the verification environment automatically generates different random excitation in each simulation process through an external random function.
In summary, the CPU test method provided in this embodiment enriches the test scenarios by accessing an external source for random excitation; the simulation environment is only carried out by C language, and the complexity is not high; meanwhile, the completeness of a test scene and the reliability of a test result are ensured by adopting a real CPU.
Example 2
In addition, the embodiment of the disclosure provides a CPU testing device.
Specifically, as shown in fig. 3, the CPU testing apparatus 300 includes:
a building module 310, configured to build a basic test case according to the verification scenario;
a configuration module 320, configured to configure an external source random excitation for the basic test case to obtain a random test case;
the execution module 330 is configured to control the CPU to execute the random test case and generate a test result;
the judging module 340 is configured to read a state value of the state register, and judge whether the operation test is completed according to the state value;
and a determining module 350, configured to determine whether the random test case is successfully executed according to the test result if the running test is completed, and terminate the running test when it is determined that the random test case is successfully executed.
The CPU testing apparatus 300 provided in this embodiment can implement the CPU testing method provided in embodiment 1, and is not described herein again to avoid repetition.
The CPU testing device provided by the embodiment enriches testing scenes by accessing external source random excitation; the simulation environment is only carried out by using C language, and the complexity is not high; meanwhile, the real CPU is adopted to ensure the completeness of a test scene and the reliability of a test result.
Example 3
Furthermore, an embodiment of the present disclosure provides an electronic device, including a memory and a processor, where the memory stores a computer program, and the computer program executes the CPU testing method provided in embodiment 1 when running on the processor.
The electronic device provided in the embodiment of the present invention can implement the CPU testing method provided in embodiment 1, and is not described herein again to avoid repetition.
The electronic equipment provided by the embodiment enriches test scenes by accessing an external source for random excitation; the simulation environment is only carried out by C language, and the complexity is not high; meanwhile, the real CPU is adopted to ensure the completeness of a test scene and the reliability of a test result.
Example 4
The present application also provides a computer-readable storage medium, on which a computer program is stored, and when executed by a processor, the computer program implements the CPU testing method provided in embodiment 1.
In this embodiment, the computer-readable storage medium may be a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk.
The computer-readable storage medium provided in this embodiment may implement the CPU testing method provided in embodiment 1, and is not described herein again to avoid repetition.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of additional like elements in the process, method, article, or terminal that comprises the element.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present application.
While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the present embodiments are not limited to those precise embodiments, which are intended to be illustrative rather than restrictive, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope of the appended claims.
Claims (10)
1. A CPU testing method, the method comprising:
constructing a basic test case according to the verification scene;
configuring an external source random excitation for the basic test case to obtain a random test case;
controlling a CPU to execute the random test case to generate a test result;
reading a state value of a state register, and judging whether the operation test is finished according to the state value;
and if the running test is finished, judging whether the random test case is successfully executed according to the test result, and finishing the running test when the random test case is successfully executed.
2. The CPU testing method according to claim 1, wherein said configuring an external source random stimulus for the basic test case to obtain a random test case comprises:
configuring a preset seed number for the basic test case to obtain a verification test case;
verifying the verification test case;
and if the verification is passed, generating a random seed number by using an external local (time) function, and configuring the random seed number for the basic test case to obtain the random test case.
3. The CPU testing method of claim 2, wherein the generating a random seed number using an external local (time) function comprises:
acquiring first system time corresponding to the current moment;
converting the first system time to the random seed number using the local (time) function.
4. The CPU testing method according to claim 3, further comprising:
updating the random seed number;
and generating a new test case, and executing the running test by using the new test case.
5. The CPU testing method of claim 4, wherein said updating said random seed number comprises:
acquiring a second system time corresponding to the current moment;
converting the second system time to an update seed number using the local (time) function;
replacing the random seed number with the updated seed number.
6. The CPU testing method according to claim 1, wherein said controlling the CPU to execute the random test case comprises:
and acquiring an operation code from a static memory outside the CPU so that the CPU executes the random test case according to the operation code.
7. The CPU testing method according to claim 6, wherein the step before the control CPU executes the random test case further comprises:
compiling the random test case to obtain a compiling result and generate a compiling log;
storing the compilation result into the static memory;
and if the random test case fails to be executed, performing error troubleshooting according to the compiling log and the test result.
8. An apparatus for testing a CPU, the apparatus comprising:
the construction module is used for constructing a basic test case according to the verification scene;
the configuration module is used for configuring an external source random excitation for the basic test case to obtain a random test case;
the execution module is used for controlling the CPU to execute the random test case and generating a test result;
the judging module is used for reading the state value of the state register and judging whether the running test is finished according to the state value;
and the determining module is used for judging whether the random test case is successfully executed according to the test result if the running test is finished, and finishing the running test when the random test case is successfully executed.
9. An electronic device comprising a memory and a processor, the memory storing a computer program that, when executed by the processor, performs the CPU testing method of any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that it stores a computer program which, when run on a processor, performs the CPU testing method of any one of claims 1 to 7.
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