JP2843071B2 - Logic circuit test apparatus and test method thereof - Google Patents

Description

[Description of the Invention] Overview Industrial application field Conventional technology (Figs. 5 and 6) Problems to be solved by the invention Means for solving the problem (Fig. 1) Action Embodiment (Fig. 2) To FIG. 4) Effects of the Invention [Overview] A logic circuit test apparatus, particularly an apparatus for performing a function test (operation function test) of a logic circuit on an LSI-mounted printed board, includes common pattern data of test data of the logic circuit. The purpose of the test pattern data is to devise the configuration of the test pattern data so that the data can be read into the test device quickly, and the logic circuit can be tested efficiently in a short time. Data input means for outputting a test pattern, first storage means for storing the common pattern data, second storage means for storing the test pattern data,
Selecting means for selecting one of the first and second storage means; and data input / output for inputting / outputting test data reconstructed based on the common pattern data, test pattern data, and data under test from the device under test. Output means;
The input means, the first and second storage means, the selection means, and a control means for controlling input / output of the data input / output means.

[Industrial applications]

The present invention relates to a test apparatus for a logic circuit,
More specifically, the present invention relates to an apparatus for performing a function test (operational function test) of a logic circuit on a printed circuit board mounted with an LSI.

2. Description of the Related Art In recent years, a large number of super LSIs and microcomputers tend to be incorporated in a logic circuit printed board that performs a general logical operation based on a function request according to a usage mode of a user.

However, function test pattern data required for a comprehensive operation test or the like of a logic circuit printed board on which these semiconductor elements are mounted is very complicated and large in volume. This requires a large-capacity test apparatus.

Therefore, an apparatus and a method for efficiently inputting test data and testing a logic circuit in a short time are desired.

[Conventional technology]

 FIGS. 5 and 6 are explanatory views according to a conventional example.

FIG. 5 shows a configuration diagram of a logic circuit test apparatus according to a conventional example.

In the figure, the test apparatus comprises a test control computer 1, an execution test pattern buffer 3, an input / output pattern control circuit 4, a pin electronics 5, and a test execution control circuit 6.

The test apparatus and the device under test 7 are connected via the pin electronics 5, and test data D 6 is applied to the device under test 7. The data D6 includes common pattern data D2 for initializing and resetting each circuit of the device under test 7 and test pattern data D3 for performing a function test of the circuit. After being stored in the storage device 2, it is input to the tester control computer 1.

FIG. 6 is a flowchart of a conventional method for testing a logic circuit.

In the figure, first, in step P1, the tester control computer 1
Execute test data D6 by test pattern buffer 3
Then, the test data D6 is applied to the device under test 7 by the input / output pattern control circuit 4 in step P2.

Next, in step P3, the test execution control circuit 6 captures the data under test D5, compares it with the expected value data,
At step P4, completion of all patterns is confirmed.

Thus, a function test (operational function test) of the logic circuit can be performed.

[Problems to be solved by the invention]

By the way, according to the conventional example, the test data D6 applied to the device under test 7 is input from the main storage device 2 to the device under test in the order of accessing the device under test 7.

The test data D6 has the common pattern data D2 as shown in FIG.
It is configured to repeat many times during D3.

For this reason, test data required for comprehensive operation tests of logic circuits incorporating many VLSIs and microcomputers
D6 becomes very complicated and the data volume becomes huge.

As a result, there is a problem that the data storage capacity of the main storage device 2 must be expanded, or the test time becomes longer due to a delay in reading the test data D6.

The present invention has been made in view of the problems of the conventional example, and devises a configuration of common pattern data and test pattern data of test data of a logic circuit to speed up reading of the data to a test apparatus, It is an object of the present invention to provide a test apparatus for a logic circuit and a test method thereof, which enable the circuit to be efficiently tested in a short time.

[Means for solving the problem]

FIG. 1 shows a principle diagram of a test apparatus for a logic circuit according to the present invention.

The apparatus receives test data D1 for a logic circuit test configured by common pattern data D2 and a plurality of test pattern data D3 having identification bits MB indicating whether to add the common pattern data D2, A data input unit 11 for separating and outputting the common pattern data D2 and the test pattern data D3, and the data input unit 11
A first storage unit 12 for storing the common pattern data D2 output from the first storage unit, and a second storage unit 13 for inputting and sequentially outputting the plurality of test pattern data D3 output from the data input unit 11. , The identification bits of the test pattern data D3 output from the second storage means 13.
Control means 16 for outputting a switching signal S2 according to MB; and the common pattern data D2 and the test pattern data D3 from the first storage means 12 and the second storage means 13; The selecting means 14 for outputting either the test pattern data D3 alone or the test pattern data D3 to which the common pattern data D2 is added, and sequentially transmitting the output of the selecting means 14 to the device under test 17 And data input / output means 15 for inputting the data under test D5 output from the device under test 17, the method comprising: adding the common pattern data D2 and the common pattern data D2 Logic circuit test data D1 composed of a plurality of test pattern data D3 having an identification bit MB indicating whether the common pattern data D2 and the A data input means 11 outputs by separating the pattern data D3, the data input unit 11
A first storage unit 12 for storing the common pattern data D2 output from the first unit, and a plurality of test pattern data D3 output from the data input unit 11 and sequentially outputting the test pattern data D3. A first processing step of writing the common pattern data D2 into the first storage means 12, and a method of testing a logic circuit of a test apparatus having two storage means 13;
Writing one of D3 into the second storage means 13
When the identification bit MB of the test pattern data D3 written in the second storage means 13 is not activated, only the test pattern data D3 is output to the device under test 17, When the identification bit MB of the test pattern data D3 written in the second storage means 13 is activated, the common pattern data D2 is read from the first storage means 12 and output to the test piece 17. After that, the test pattern data D3 is
And a third processing step of outputting to the second and third
Is repeated for all test pattern data D3 to achieve the above object.

(Operation)

In the present invention, test data is input to the data input means 11.
When D1 is input, the data input means 11
The common pattern data D2 and the test pattern data D3 constituting D1 are separated and output. The common pattern data D2 output from the data input means 11 is stored in the first storage means 12
And the test pattern data D3 is stored in the second storage means.
Stored in 13.

Test pattern data stored in the second storage means 13
D3 is sequentially output, but the control means 16 stores the second storage means 13
Bit MB of test pattern data D3 output from
And outputs a switching signal S2 in response to.

In response to the switching signal S2, the selection means 14 switches its input. For example, when the identification bit MB is activated (in the case of “1”), the selection unit 14 outputs the common pattern data D2 input from the first storage unit 12 in response to the switching signal S2, and then performs the second storage. The test pattern data D3 input from the means 13 is output. When the identification bit MB is not activated (in the case of “0”), the selection means 14 outputs the switching signal
In response to S2, only the test pattern data D3 input from the second storage means 13 is output.

As described above, in the present invention, the test data is given to the device under test 17 while reconstructing the test data D1.
It is sufficient that the test data D1 includes only one common pattern data D2.

For this reason, the state where the common pattern data D2 is repeated many times during the test pattern data D3 as in the conventional example is eliminated. As a result, even if the test data D4 of the logic circuit incorporating a large number of VLSIs and microcomputers becomes extremely complicated and the amount of test data increases, the test data D4 can be input from the main storage device to the test device. It is possible to reduce the test data D1 to be transmitted.

As a result, it is possible to reduce the expansion of the data storage capacity of the main storage device and the like, and to shorten the test time of the device under test 17 because the test data D1 can be read quickly.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

2 to 4 are diagrams for explaining a test apparatus and a test method for a logic circuit according to an embodiment of the present invention.
1 shows a configuration diagram of a logic circuit test apparatus according to an embodiment of the present invention.

In the figure, reference numeral 21 denotes a tester control computer as one embodiment of data input means. The computer 21 receives one of the common pattern data D2 that can be shared by each circuit and the compressed test data D1 composed of a plurality of test pattern data D3 unique to each circuit, and stores the common pattern data D2 in a common pattern memory 22. And outputs the test pattern data D3 to the execution test pattern buffer 23.

Reference numeral 22 denotes a common pattern memory which is an embodiment of the first storage means 12, and stores the common pattern data D2. The reading of the data D2 is performed by the test execution control circuit 26.
This is performed by the start signal S1 from the CPU.

Reference numeral 23 denotes an execution test pattern buffer which is an embodiment of the second storage means 13, and stores test pattern data D3. The reading of the data D3 is similarly performed by the control circuit.
This is performed by a start signal S1 from 26.

Reference numeral 24 denotes a memory selection circuit as an embodiment of the selection means, which selects one of the common pattern memory 22 and the execution test pattern buffer 23 and outputs the common pattern data D2.
Alternatively, it outputs test pattern data D3. The selection circuit 24 is controlled by a switching signal S2 from the test execution circuit 26.

Reference numerals 25a and 25b denote input / output pattern control circuits and pin electronics constituting the data input / output means 15. The input / output pattern control circuit 25a receives the common pattern data D2 and the test pattern data D3 and reconfigures the test data D4
Is output. Pin electronics 25b
The device under test 27 is connected to the test apparatus.

Reference numeral 26 denotes a test execution control circuit as an embodiment of the control means 16, which outputs a start signal S1 to the memory 22 and the buffer 23, and outputs a control signal S3 to the control circuit 25a. As a result, the reconstructed test data D4 is applied to the device under test 27, and the data under test D5 is taken into the pin electronics 25b from the device under test 27.

Note that the taken data under test D5 is compared with expected value data and the like to determine the quality of the logic circuit. Also,
Reference numeral 28 denotes a main storage device for temporarily storing the compressed test data D1 transferred from the data generation system.

FIGS. 3A and 3B are explanatory diagrams of the compressed test data D1 according to the embodiment of the present invention.

FIG. 7A shows common pattern data D2 stored in the common pattern memory 22. The data D2 is data for initializing and resetting each circuit of the device under test 27.

FIG. 2B shows the compressed test data D1 input to the tester control computer 21.

The compressed test data D1 is a combination of one of the common pattern data D2 that can be shared by each circuit and a plurality of test pattern data D3 unique to a test (function test) of each circuit of the device under test 27.

The data D3 includes a control data part and a test data part, and the control data part has a common pattern execution identification bit.
MB is provided. By identifying this identification bit MB by the test execution control circuit 26, the test pattern data
The common pattern data D2 can be inserted before or after execution of D3.

FIG. 9C shows the reconstructed test data D4 applied to the device under test 27.

For example, when the identification bit MB is activated in the patterns 1, 3, and 8 of the compressed test data D1 in FIG. 4B, the common pattern data D2 is added before the pattern 1, and the patterns 2 and 3 are added. And the data D2 is inserted between the patterns 7 and 8.

Thus, according to the test apparatus of the embodiment of the present invention, the common pattern memory 22 for storing the common pattern data D2 and the memory 22 or the execution test pattern buffer 23
A memory selection means 24 for selecting any one of them is provided.

Therefore, the test execution control circuit 26 recognizes and discriminates the identification bit MB provided in the control data portion of the test pattern data D3.
D2 is read, and test pattern data D3 is read from execution test pattern buffer 23.

As a result, it is possible to supply the test object 17 with the test data D4 composed of the common pattern data D2 and the test pattern data D3 reconstructed based on the compressed test data D1.

The control data portion of the test pattern data D3 stored in the execution test pattern buffer 23 is sent to the test execution control circuit 26, and the test pattern data D3 output from the execution tester pattern buffer 23 includes the control data portion. Not.

FIG. 4 is a flowchart of a method for testing a logic circuit according to an embodiment of the present invention.

In the figure, first, the pin electronics 25 of FIG.
When performing a function test (operational function test) of the logic circuit of the device under test 27 connected to b, one common pattern data D2 and a plurality of test pattern data D3 necessary for reconstructing the test data D4 are determined in advance. The compressed test data D1 to be configured is created. And step P1
To write the common pattern data D2 into the common pattern memory 22.

At this time, the common pattern data D2 is read out in a hardware manner by reading data written in a ROM (read only memory). Alternatively, before the compressed test data D1 is transferred from the data generation system, the compressed test data D1 may be input by the tester control computer 21 and written into the RAM (write / read memory as needed).

Next, the test pattern data D3 is written to the execution test pattern buffer 23 in Step P2. At this time, the test data D1 compressed by the tester control computer 21 is read from the main storage device 28, and the data D3 is written to the buffer 23.

Next, in step P3, it is determined whether or not there is an identification bit for executing the common pattern. When the identification bit is recognized (YES)
Moves to Step P4. If it cannot be recognized (NO), the program shifts to Step P5.

In Step P4, the common pattern data D2 is read and applied to the device under test 27. In Step P5, the test pattern data D3 is read and applied to the device under test 27. As a result, the test data D4 as shown in FIG. 5 is reproduced.

Thereafter, in the same manner as in the conventional example, in step P5, the data under test D5 is taken into the test apparatus and compared and compared. In step P7, the end of all the patterns is determined, and the test is terminated.

Thus, a function test (operational function test) of the logic circuit can be performed.

Thus, according to the test method of the embodiment of the present invention, the compressed test data D1 composed of the common pattern data D2 and the test pattern data D3 necessary for reconstructing the test data D4 is created in advance. Keep it.

For this reason, the state where the common pattern data D2 is repeated many times during the test pattern data D3 as in the conventional example is eliminated. As a result, even when the test data D4 of a logic circuit incorporating a large number of VLSIs and microcomputers becomes extremely complicated and the amount of test data increases, the test data D4 can be input from the main storage device 28 to the test device. It is possible to reduce the number of compressed test data D1 to be transmitted.

This makes it possible to reduce the expansion of the data storage capacity of the main storage device and the like, and to shorten the test time of the device under test 27 because the test data D1 can be read quickly.

In the embodiment of the present invention, the case where the common pattern data is inserted before the test pattern data has been described, but the same effect can be obtained by inserting it after the test pattern data. Also, the case where the common pattern data is one has been described. However, when there is a plurality of such data, the identification bit is given a selectivity, it is given an execution test pattern buffer property, and the identification bit is given by the execution test pattern buffer. The identification allows the test data to be efficiently reconstructed.

〔The invention's effect〕

As described above, according to the present invention, since the common pattern memory and the memory selection circuit are provided, the test data can be reconfigured based on the common pattern data and the test pattern data to which the identification bits are added.

For this reason, the test object can be tested using the compressed test data, and the data storage capacity of the main storage device or the like has a margin. Further, since the test data can be read at high speed, the test time can be reduced.

This makes it possible to efficiently perform a comprehensive operation test and the like of the logic circuit printed board.

[Brief description of the drawings]

FIG. 1 is a principle diagram of a logic circuit test device according to the present invention, FIG. 2 is a configuration diagram of a logic circuit test device according to an embodiment of the present invention, and FIG. 3 is a compression diagram according to the embodiment of the present invention. FIG. 4 is a flowchart of a method for testing a logic circuit according to an embodiment of the present invention, FIG. 5 is a configuration diagram of a conventional logic circuit test apparatus, and FIG. 6 is a flowchart of a method for testing a logic circuit according to a conventional example. (Explanation of reference numerals) 11 ... data input means, 12 ... first storage means, 13 ... second storage means, 14 ... selection means, 15 ... data input / output means, 16 ... control means, D1 ... Compressed test data D2 ... Common pattern data D3 ... Test pattern data D4 ... Reconstructed test data D5 ... Test data

Claims (2)

(57) [Claims] 1. A logic circuit comprising common pattern data (D2) and a plurality of test pattern data (D3) having an identification bit (MB) indicating whether to add the common pattern data (D2). Data input means (11) to which test test data (D1) is input and which separates and outputs the common pattern data (D2) and the test pattern data (D3); and outputs from the data input means (11). A first storage unit (12) for storing the common pattern data (D2) obtained, and a plurality of test pattern data (D3) output from the data input unit (11) and sequentially output. 2
Storage means (13), and control means (16) for outputting a switching signal (S2) according to the identification bit (MB) of the test pattern data (D3) output from the second storage means (13). The first storage means (12) and the second storage means (1
3) The common pattern data (D2) and the test pattern data (D3) are input from and the test pattern data (D3) alone or the common pattern data (D2) is changed according to the switching signal (S2). Selection means (14) for outputting any of the added test pattern data (D3)
A data input / output unit (15) for sequentially transmitting the output of the selecting unit (14) to the device under test (17) and inputting the data under test (D5) output from the device under test (17) A test apparatus for a logic circuit, comprising: 2. A logic circuit comprising common pattern data (D2) and a plurality of test pattern data (D3) having identification bits (MB) indicating whether to add the common pattern data (D2). Data input means (11) to which test test data (D1) is input and which separates and outputs the common pattern data (D2) and the test pattern data (D3); and outputs from the data input means (11). A first storage unit (12) for storing the common pattern data (D2) thus obtained, and the plurality of test pattern data (D3) output from the data input unit (11); A second storage means (13) for sequentially outputting (D3) a test circuit for a logic circuit of a test apparatus, the method comprising writing the common pattern data (D2) in the first storage means (12). One place A second processing step of writing one of the plurality of test pattern data (D3) to the second storage means (13); and a second processing step of writing one of the plurality of test pattern data (D3) to the second storage means (13). When the identification bit (MB) of the test pattern data (D3) is not activated, only the test pattern data (D3) is output to the device under test (17), and the second storage means (13)
When the identification bit (MB) of the test pattern data (D3) written to the device is activated, the common pattern data (D2) is read from the first storage means (12) and And a third processing step of outputting the test pattern data (D3) to the device under test (17) after outputting the test pattern data to the test object (17). A test method for a logic circuit, characterized by repeating (D3).