JP2003196257A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To execute a self-test by using a signal path which is the same as that in its normal use, and to make it unnecessary to overlap an address space for a self-test ROM, and to reduce a self-test ROM capacity. <P>SOLUTION: An address output 3, data output 4, and control output 5 from a CPU 1 and a download address 16, download data 17, and down load bus control signal 18 from a test control circuit 12 are inputted to program RAM input selectors 15a, 15b, and 15c, and the outputs are selected according to a bus selection signal 8, and inputted to the program RAM 2. The test control circuit 12 transfers a self-test ROM address 22, self-test ROM control signal 23, and self-test ROM data output 10 or the like with a self-test ROM 6, and transmits a CPU reset signal 24 to the CPU 1 for reset control. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, more specifically, a CPU and a program RA inside.
The present invention relates to a semiconductor integrated circuit having M and a self-test ROM.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit (hereinafter, also referred to as an LSI) in which a CPU, a program RAM as a program memory of the CPU, a self-test ROM and the like are incorporated is used.

In this type of semiconductor integrated circuit, the above-mentioned CPU executes the test program of the self-test ROM, and the manufacturing verification is performed by determining whether the operation result of the circuit is valid or not by the program. Such a manufacturing verification method is also called a self-test, and when the self-test is performed, the output of the test program is switched to the output of a normal program memory by a self-test selection signal.

FIG. 5 is a diagram for explaining a configuration example of a conventional semiconductor integrated circuit. As shown in FIG. 5, the semiconductor integrated circuit includes a CPU 31, a program RAM 32, a self-test ROM 36, and the like, and each unit is connected by a bus that exchanges various signals.

For example, the address output 3 from the CPU 31
3 and control output 35 are programmed RA via the bus.
Input to M32 and self-test ROM 36 respectively,
The data output 34 from the CPU 31 is input to the program RAM 32 via the bus.

The data output 40 from the self-test ROM 36 and the data output 39 from the program RAM 32 are input to the CPU data input bus selector 38, and any one of the data is selected and output. The data selection operation by the CPU data input bus selector 38 is controlled by the bus selection signal 41 generated by the test control circuit 42, and the selected data is input to the CPU 31 as the data input 37.

The test control circuit 42 normally outputs a bus selection signal 41 for selecting the data output 39 of the program RAM 32, and decodes the address output 33 when the self-test is instructed by the self-test selection signal 43. , The address area of the self-test ROM 36 is C
When the PU 31 makes an access, the self-test ROM 36
A value for selecting the data output 40 is output.

When performing the above-described self test (manufacturing verification), the reset of the CPU 31 is released by the self test start signal 44, and the CPU 31 causes the self test ROM 3 to operate.
This was done by executing the self-test program in 6.

An example of this type of publication is, for example, "1-chip microcomputer" described in Japanese Patent Laid-Open No. 59-20069, in which a test ROM area having the same address space as the ROM area is separately provided and switched. I was testing by connecting.

[0010]

However, in such a conventional semiconductor integrated circuit, since the program in the self-test ROM 36 is executed during the self-test, the program execution in the program RAM 32 during normal use is Since a different signal path is used, there is a problem that it is not possible to perform a test according to the operation during normal use.

FIG. 6 is a diagram showing the memory layout of the CPU in FIG. 5, showing the normal use and the self-test execution. It is assumed that the CPU 31 of FIG. 5 executes from the instruction at address 0x0000 after reset release. Here, the program R for normal use
A self-test ROM area is arranged at an address that overlaps with the AM area, and a self-test RO area is set when the self-test is performed.
The bus control signal 41 is output from the test control circuit 42 so that the M side is selected. However, in the memory arrangement as shown in FIG. 6, there is a problem in that it is not possible to access the area where the address overlaps during the self test.

Further, FIG. 7 is a diagram showing another example of the memory arrangement of the CPU in FIG. 5, showing the normal use and the self-test execution. Here, the self test RO is performed in an area that does not overlap with the program RAM area.
The M area is arranged and the content of the address executed first after the reset is released is used as a branch instruction to the head of the self-test ROM. In this case, it is possible to execute the test on the entire program RAM area. However, FIG.
In such a memory arrangement, there is a problem that the self test ROM area cannot be taken if the CPU address area has no margin.

The present invention has been made in view of the above,
The self-test can be performed using the same signal path as in normal use, and it is not necessary to duplicate the dedicated address space or address space for the self-test ROM, and to reduce the capacity of the self-test ROM. The object is to obtain a semiconductor integrated circuit capable of

[0014]

To achieve the above object, a semiconductor integrated circuit according to the present invention has a CPU inside.
In a semiconductor integrated circuit having a program RAM and a self-test ROM, a self-test program is downloaded from the self-test ROM to the program RAM by a self-test selection signal and a self-test start signal input from the outside, and The CPU
It is characterized by comprising a test control circuit for releasing the reset.

According to the present invention, by the self-test selection signal and the self-test start signal input from the outside,
Since the test control circuit that downloads the self-test program from the self-test ROM to the program RAM and releases the reset of the CPU is provided, the area of the program RAM where the test program is downloaded is accessed and actually used. A self test using the signal path can be performed.

In the semiconductor integrated circuit according to the next invention, the test control circuit further includes a decompression circuit for decompressing compressed data, and when the test program is downloaded, the compressed program code in the self-test ROM is decompressed. The circuit is expanded and converted into a test program that can be recognized by the CPU.

According to the present invention, the test control circuit further comprises a decompression circuit for decompressing the compressed data, and when the test program is downloaded, the decompression circuit decompresses the compressed program code in the self-test ROM to obtain a CP.
Since the test program is converted into a test program that can be recognized by U, the capacity of the self-test ROM can be reduced.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of a semiconductor integrated circuit chip according to the present invention will be described in detail below with reference to the accompanying drawings.

Embodiment 1. 1 is a block diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

As shown in FIG. 1, the semiconductor integrated circuit according to the first embodiment includes a CPU 1, a program RAM 2, a self-test ROM 6, a test control circuit 12 and the like, and various signals are sent between the respective parts. Connected by a bus that interacts.

Then, the address output 3 from the CPU 1,
The data output 4 and the control output 5 are input to the program RAM input selectors 15a, 15b, 15c via the bus, respectively. Further, data input 7 is made from the program RAM 2 to the CPU 1.

Further, the download address 16 and the download data 1 output from the test control circuit 12
7 and the download bus control signal 18 are also input to the program RAM input selectors 15a, 15b and 15c.

This program RAM input selector 15
a, 15b, 15c are address output 3, data output 4, control output 5 from the CPU 1 side, and the test control circuit 12 in response to the bus selection signal 8 from the test control circuit 12.
The download address 16, the download data 17, and the download bus control signal 18 from the side are selected and input to the program RAM 2 as the program RAM address 19, the program RAM data input 20, and the program RAM control input 21.

The bus selection signal 8 from the test control circuit 12 usually takes a value for selecting the output from the CPU 1.

Further, the test control circuit 12 has a self-test ROM address 22, a self-test ROM control signal 23, a self-test ROM data output 10 and the like with the self-test ROM 6 in addition to the interface to the program RAM 2 described above. It has a bus interface for communication.

The CPU 1 is reset by the CPU reset signal 24 from the test control circuit 12.

The semiconductor integrated circuit according to the first embodiment is
It is configured as described above, and its self-test operation will be described below.

First, as shown in FIG. 1, the test control circuit 12 is set to the self-test mode when the self-test selection signal 13 is input from the outside. At the same time,
The test control circuit 12 resets the CPU 1 by the CPU reset signal 24, and at the same time, the test control circuit 12
The bus selection signal 8 for selecting the download address 16, the download data 17, and the download bus control signal 18 from is output.

Subsequently, as shown in FIG. 1, when the self-test start signal 14 is input to the test control circuit 12, the test control circuit 12 causes the test program in the self-test ROM 6 to pass through the bus interface for the self-test ROM 6. Is read out and further written in the program RAM 2 by the program RAM address 19, the program RAM data input 20, the program RAM control input 21 and the like via the bus interface for download from the test control circuit 12.

After all the test programs have been transferred to the program RAM 2 in this way, the test control circuit 12 switches the program RAM input selectors 15a, 15b, 15c to the CPU 1 side by the bus selection signal 8. At the same time, the test control circuit 12 releases the reset of the CPU 1 and the CPU 1 executes the test program transferred to the program RAM 2 to determine the result of the self-test.

FIG. 2 is a timing chart when control is performed using the test control circuit of FIG. As shown in FIG. 2, during the reset period of the CPU 1 by the CPU reset signal, the self-test program is transferred from the self-test ROM 6 to the program RAM 2 under the control of the test control circuit 12 (downward arrow in FIG. 2), and the program is transferred. After the end, the test control circuit 12 releases the CPU reset signal 24, so that the program RAM 2
The self-test program transferred to the inside is executed, and the self-test (manufacturing verification) is performed.

As described above, according to the first embodiment, since the test program is in the program RAM 2, the access test of the area in which the program is arranged is performed by using the same signal path as in normal use. It becomes possible to confirm by the execution itself of, and an effective self-test can be performed.

Further, according to the first embodiment, since the self-test ROM 6 is accessed only by the test control circuit 12, a dedicated address space for the self-test ROM 6 and an address space with the program RAM 2 and the like. Duplication is unnecessary, and inaccessible areas can be eliminated.

Embodiment 2. 3 is a configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

As shown in FIG. 3, the basic structure of the semiconductor integrated circuit according to the second embodiment is substantially the same as that of the semiconductor integrated circuit according to the first embodiment (see FIG. 1).
The same parts are designated by the same reference numerals and the description of the configuration will be omitted.

In the characteristic configuration of the semiconductor integrated circuit according to the second embodiment, in the case of the above-described first embodiment, the value read from the self-test ROM 6 is used as the test control circuit 12.
Was written in the program RAM 2 as is, whereas the expansion circuit 25 was incorporated in the test control circuit 12, and the test control circuit 1 was previously stored in the self-test ROM 6.
The compressed self-test program corresponding to the decompression circuit 25 of No. 2 is stored.

When the compressed self-test program of the self-test ROM 6 is transferred to the program RAM 2, the expansion circuit 25 in the test control circuit 12 is used.
The program code is decompressed by the above, converted into a test program recognizable by the CPU 1, and then transferred.

In this way, the self-test program is
Since it can be stored in the self-test ROM 6 in a compressed state, it is possible to reduce the memory capacity of the self-test ROM 6 itself.

FIG. 4 is a timing chart when control is performed using the test control circuit of FIG. As shown in FIG. 4, during the reset period of the CPU 1 by the CPU reset signal, the self-test program is transferred from the self-test ROM 6 to the program RAM 2 under the control of the test control circuit 12, but the self-test program in the self-test ROM 6 is Since it is compressed, the CPU 1 cannot recognize it even if it is transferred as it is. Therefore, the compressed self-test program is expanded by the expansion circuit 25 inside the test control circuit 12, and the expanded self-test program is transferred to the program RAM 2.

When the transfer of the self-test program is completed, the test control circuit 12 releases the CPU reset signal 24 and the CPU 1 executes the self-test program transferred into the program RAM 2 to execute a self-test (manufacturing verification). Is carried out.

As described above, according to the second embodiment, the compressed self-test program is stored in the self-test ROM 6 in advance, and the self-test program is expanded in the test control circuit 12 when the self-test program is downloaded. The self-test ROM 6 is expanded by the circuit 25 and converted into a self-test program that can be recognized by the CPU 1.
It is possible to reduce the memory capacity of itself and improve the integration degree of the semiconductor integrated circuit.

In the second embodiment, the example of the compression / expansion circuit has been described, but the present invention is not limited to this, and an encoding / decoder may be used as another configuration. Of course good.

[0043]

As described above, according to the present invention, the self-test program is downloaded from the self-test ROM to the program RAM by the self-test selection signal and the self-test start signal inputted from the outside, and the CPU is downloaded. Since the test control circuit for releasing the reset is provided, the area of the program RAM where the test program is downloaded is accessed, and the self-test using the signal path actually used can be performed.

According to the next invention, the test control circuit further comprises an expansion circuit for expanding the compressed data, and at the time of downloading the test program, the compressed program code in the self-test ROM is expanded by the expansion circuit, and C
Since the PU is converted into a recognizable test program, the capacity of the self-test ROM can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart when control is performed using the test control circuit of FIG.

FIG. 3 is a configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a timing chart when control is performed using the test control circuit of FIG.

FIG. 5 is a diagram illustrating a configuration example of a conventional semiconductor integrated circuit.

6 is a diagram showing a memory arrangement of the CPU in FIG.

FIG. 7 is a diagram showing another example showing a memory arrangement of the CPU in FIG.

[Explanation of symbols]

1 CPU, 2 program RAM, 3 address output, 4 data output, 5 control output, 6 self test R
OM, 7 data input, 8 selection signal, 10 self test ROM data output, 12 test control circuit, 15a,
15b, 15c Program RAM input selector, 16
Download address, 17 download data,
18 Download bus control signal, 19 Program R
AM address, 20 program RAM data input, 2
1 Program RAM control input, 22 Self test R
OM address, 23 self-test ROM control signal, 2
4 CPU reset signal.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G06F 11/22 340 G06F 11/22 360A 360 12/16 330A 12/16 330 G11C 29/00 675M G11C 29 / 00 675 G01R 31/28 VP B F term (reference) 2G132 AA01 AA03 AA08 AA09 AB01 AC04 AE22 AE23 AG01 AG02 AG11 AK13 AK29 AL00 AL29 AL40 5B018 GA03 HA35 JA21 JA24 MA23 MA34 NA01 PA03 QA13 5B048 A02 AA12 A01 GG05 HH08 JJ05 5L106 AA16 DD11 DD21 EE02 GG07

Claims (2)

[Claims] 1. A semiconductor integrated circuit having a CPU, a program RAM, and a self-test ROM inside, and a self-test from the self-test ROM to the program RAM in response to a self-test selection signal and a self-test start signal input from the outside. A semiconductor integrated circuit comprising a test control circuit for downloading a test program and releasing the reset of the CPU. 2. The test control circuit further comprises a decompression circuit for decompressing compressed data, and when the test program is downloaded, the compressed program code in the self-test ROM is decompressed by the decompression circuit to obtain the CPU. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is converted into a recognizable test program.