JPH11250115A - Logical verification method using emulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logical verification method using an emulator capable of quickly executing the logical verification and debugging of a computer to be developed. SOLUTION: The emulator is initialized, a test program is loaded into a simulator on the emulator which is prepared for simulating a computer and the simulator is allowed to execute the test program. When an error occurs in the simulator, the emulator is initialized, the test program is loaded again into the simulator on the emulator to allow the simulator to execute the test program again, the simulator is stopped by several cycles before the detection of the error, and all FF/RAM values in the simulator are dumped. The dumped FF/RAM values are loaded to a simulator on a software simulator to start the simulator on the software simulator.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a logic verification method using an emulator and a software simulator.

[0002]

2. Description of the Related Art Reproduction of a specific state inside a computer is possible by setting all FF / RAM values. There is a simulator on the emulator that performs the same operation as the computer under development, but if an error is detected while the simulator on the emulator is executing the test program, another software simulator Let us consider a case where the error is to be reproduced by the above method.

FIG. 3 is a diagram for explaining a conventional example of logic verification using an emulator. First, the simulator of the emulator is initialized and a test program is loaded into the simulator. If an error is detected during the process of causing the simulation device to execute the test program, the clock number (clock input to the simulation device) at which the error occurred is recorded. Note that “Clock = ****” in the figure indicates the number of clocks when an error occurs.

Next, the software simulator is initialized and the same test program is loaded into the software simulator. Then, the software simulator is caused to execute the test program until the stored clock number is reached. Then, the error is reproduced.

FIG. 4 is a diagram for explaining another conventional example of logic verification using an emulator. First, the simulator on the emulator is initialized, and a test program is loaded on the simulator. In the course of causing the simulator to execute the test program, the value of the FF / RAM of the simulator is dumped every sampling cycle, and the dump value is sent to the host. The host uses the dumped FF / R
When the value of AM is received, the value of FF / RAM is compared with the expected value. Note that the expected value is stored in the memory.

If an error is detected in the expected value comparison, a software simulator is started. The software simulator simulates a computer to be developed with software. When starting the software simulator, the values of all flip-flops and RAM several cycles before the error detection point are loaded into the flip-flops and RAM of the simulation device. And
Have the software simulator run the test program and reproduce the error. Note that the loaded flip-flop and RAM values also include a test program.

[0007]

In the logic verification method shown in FIG. 3, the number of cycles in which an error is detected (synonymous with the number of clocks) is recorded, and a software simulator is used from the beginning to the error detection cycle. Had to run the test program. in this case,
For example, when an error is detected at a relatively shallow stage of a program, such as an initial stage of logic verification, there is no particular problem. However, when logic verification progresses and errors are detected only at a deep stage of the test program, or when the number of steps of the test program to be executed becomes enormous, it takes time until the errors are detected. A significant number of cycles of the test program will be executed. In such a case, if the software simulator is executed from the first 0th cycle every time debugging is performed, the time loss until the error is reproduced becomes large, and the efficiency becomes poor.

In the logic verification method as shown in FIG. 4, a software simulator is built in a computer host, and when an error is detected, the built-in software simulator is automatically started. In this case, the host holds the values of the FFs / RAMs immediately before the error is detected, and by giving these values to the software simulator at the time of startup, the problem of time loss can be solved. However, in the logic verification method as shown in FIG.
Since there is only one software simulator for debugging per host, the number of software simulators is limited. For example, if it is necessary to solve a logic design bug early, Since it is impossible to say that an analysis is performed, it cannot be said to be efficient. Even when there are a plurality of software simulators in the host, if they are started more than once, the load is imposed on the host and the efficiency is eventually lowered.

The present invention has been made in view of the above point, and provides a logic verification method using an emulator which can perform logic verification and debugging of a computer to be developed in a short time. It is an object.

[0010]

According to a first aspect of the present invention, there is provided a logic verification method using an emulator, wherein a simulation program on an emulator for simulating a computer executes a test program. A test program is executed from the beginning, and the simulator is stopped at a point in time before an error is detected. All the flip-flops and RAM values of the simulator at the stop point are dumped, and the dumped flip-flops are dumped. And RAM
Is loaded into a simulator on a software simulator that simulates the computer, and the simulator on the software simulator is started.

According to a second aspect of the present invention, there is provided a logic verification method using the emulator according to the first aspect, wherein the dumped values of the flip-flop and the RAM are loaded into a simulation device on a plurality of software simulators. And activating a simulation device of each software simulator.

The operation of the first aspect of the present invention will be described.
According to the first aspect of the present invention, the value of the FF / RAM of the simulation device several cycles before the error detection point can be obtained in a short time, so that the logic verification can be performed efficiently. The operation of the second aspect will be described. Claim 2
According to the invention, since the values of the FF / RAM can be loaded into a plurality of software simulators and the logic verification can be performed by the plurality of software simulators, it is possible to find a bug at an early stage.

[0013]

FIG. 1 is a diagram for explaining logic verification using an emulator of the present invention, and FIG. 2 is a diagram for explaining an emulator of the present invention. In the figure, 1
Is an emulator, 2 is a simulation device, 3 is a controller,
Indicates DASD, respectively.

The emulator used in the present invention will be described with reference to FIG. The emulator 1 includes a simulation device 2 and a controller 3. The simulation device 2 simulates the operation of a computer main body to be developed, and is composed of a group of programmable gate arrays on which logic is printed. Simulate RA in the simulation device 2
M exists, and the test program read from the DASD 4 is written in the RAM.

The controller 3 starts / stops the simulation device 1, detects an error by comparing a state value of the simulation device with an expected value, and dumps all flip-flops and RAM values existing in the simulation device. . Error detection processing is N
This is performed every memory cycle. It should be noted that the value of N is reduced in the early stage of development, and is increased in the later stage of development.

At the time of error detection processing, whether or not the locus of the value of the program counter of the simulation device matches the locus of the value of the program counter as a model, the value of the selected register in the simulation device becomes the expected value. The match is checked. If one or more mismatches exist, it is determined that an error has occurred.

The logic verification method of the present invention will be described with reference to FIG. First, all FFs / emulation targets
A list is created by picking up the RAM names, then the simulator on the emulator is initialized, and a test
Load the program into the simulator.

Next, a test program is executed by a simulator on the emulator, and if an error is detected, the number of cycles at that time is recorded. Next, the simulation program on the emulator is again executed by the simulator, and the simulator on the emulator is stopped at a certain time (several hundred to several thousand cycles) from the error detection cycle.

Next, the FF / R described in the above list
The value of AM is dumped in a file format, and this file is converted into a data format given to a software simulator as shown in the example below. Here, & V is a command on the simulator that gives a value to the flip-flop, and & mload is a command on the simulator that gives a value to the RAM. Example) & V ("processor-0.s-ering.rt.in-data-sreg39-36.q
[2] "= 0x0); & V (" processor-0.s-ering.rt.out-data-sreg79-72.q
[5] "= 0x1); & V (" processor-0.s-ering.rt.out-data-sreg79-72.q
[6] "= 0x1); & V (" processor-0.s-ering.rt.out-data-sreg79-72.q
[7] "= 0x0); & V (" processor-0.s-ering.rt.out-data-sreg79-72.q
[8] "= 0x1); & mload (" processor-0.s-core.s-cpu.r-pc.tstack.t219r
am "," SQramdata / SQramdata8 ");& mload (" processor-0.s-core.s-cpu.r-pc.fpc.ilt.ra
m "," SQramdata / SQramdata9 ");

After starting the software simulator, the debugger gives the values of all flip-flops and RAM to the software simulator, and executes the software simulator from there. As a result, the error can be reproduced. In the example of FIG. 1, there are four software simulators. There is one software simulator in one host. Each software simulator may be the same or different.

According to the logic verification method of the present invention, the time required to reproduce an error can be reduced as compared with the conventional method, and the disadvantage that the logic verification requires time in the conventional technology and the bug detection can be performed by a large number of people. The disadvantage of being unable to do so can be improved. The logic verification method of the present invention is effective in the following cases. (1) When using a multi-step test program. (2) When the number of program steps until error detection increases. (3) When it takes time to execute one cycle in the simulator.

Furthermore, debugging can be performed in parallel using a plurality of computers, which is particularly effective when one error needs to be analyzed early. Furthermore, by obtaining a plurality of sample data from the emulator, it is possible to perform different error analysis on a plurality of computers, respectively, and this is particularly effective when a large number of errors are detected. .

[0023]

As is apparent from the above description, according to the present invention, the time required for verification and debugging can be reduced. In particular, the efficiency of verification and debugging when using a large test program has been greatly improved. As a result, hardware development efficiency has improved.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining logic verification using an emulator of the present invention.

FIG. 2 is a diagram illustrating an emulator according to the present invention.

FIG. 3 is a diagram for explaining a conventional example of logic verification using an emulator.

FIG. 4 is a diagram for explaining another conventional example of logic verification using an emulator.

[Explanation of symbols]

 1 emulator 2 simulator 3 controller 4 DASD

Claims (2)

[Claims] A simulation program on an emulator for simulating a computer executes a test program. When an error is detected, the simulation program executes the test program from the beginning. At the time, the simulator is stopped, all flip-flops and RAM values of the simulator at the time of stop are dumped, and the values of the dumped flip-flops and RAM are stored on a software simulator that simulates the computer. A logic verification method using an emulator, wherein the method is loaded into a simulation device and starts the simulation device on a software simulator. 2. The method of claim 1, wherein said flip-flop and RA
2. The logic verification method using an emulator according to claim 1, wherein the value of M is loaded into simulators on a plurality of software simulators, and the simulators of each software simulator are started.