JPH04290443A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a TFT having excellent electrical characteristics by a method wherein a lamp light containing a light having a specific wavelength is applied to a specific polycrystalline silicon film into which impurity ions are implanted to activate the impurities. CONSTITUTION:An amorphous silicon film 102 is deposited on a quartz substrate 101 so as to have a thickness of 1000Angstrom and subjected to a lamp annealing with a light having a wavelength not less than 350nm and not larger than 500nm to be converted into a first polycrystalline silicon film. The surface of the polycrystalline silicon film is oxidized to form an SiO2 gate insulating film 103. Then a gate electrode 104 composed of a second polycrystalline silicon film having a thickness of 3500Angstrom is formed. Then impurities are introduced in such a manner that phosphorus ions are implanted with a concentration not less than 1X10<15>/cm<3> to form source/drain (105a and 105b) in a self- alignment manner by using the gate electrode 104 as a mask and lamp annealing is performed with a light having a wavelength not less than 350nm and not larger than 500nm to activate the impurities. Then an SiO2 interlayer insulating film 106 is formed and contact holes are drilled and Al wirings 107 are formed.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention mainly relates to TFT (Th
in Film Transistor).

0002

[Prior Art] Conventionally, in a method of manufacturing a TFT, particularly a method of manufacturing a TFT using a polycrystalline silicon film as a semiconductor layer,
Emphasis has been placed on solid phase growth as a means to improve the electrical characteristics of FTs. The solid phase growth method heat-treats amorphous silicon at a temperature of around 600°C for several tens of hours.
This is a method of converting into polycrystalline silicon with large grain size. T
It is known that the electrical characteristics of FT are better as the grain size of the crystal grains constituting the polycrystalline silicon film becomes larger. Polycrystalline silicon is usually produced by low pressure CVD (LPCV) using silane gas.
D) formed by a method. The film quality of the silicon film produced by the above method depends on the deposition temperature. For example, in the LPCVD method using SiH4 gas, the deposition temperature is about 580°C, and at a deposition temperature lower than that, amorphous silicon is formed, and at a deposition temperature higher than that, polycrystalline silicon is formed. is formed. The grain size of polycrystalline silicon increases as the deposition temperature increases, but polycrystalline silicon grown using a solid phase growth method has a much larger grain size than polycrystalline silicon deposited at a relatively high temperature.

Methods other than solid phase growth for increasing the grain size of polycrystalline silicon include methods of irradiating amorphous silicon or polycrystalline silicon with electron beams or laser beams, both of which are formed using the LPCVD method. Polycrystalline silicon having a larger grain size than that of polycrystalline silicon is obtained.

0004

However, all of the methods described above for increasing the grain size of polycrystalline silicon have problems when applied to mass production technology. That is, the solid phase growth method uses furnace annealing and is a simple method, but it has the problem that the processing time is long, that is, the throughput is low. Further, the quality of the polycrystalline silicon film obtained by solid-phase growth is influenced by the quality of the amorphous silicon film deposited before the solid-phase growth and the quality of the underlying layer of amorphous silicon. Even a film normally called amorphous silicon has a microscopic value of 100
This is because it has crystal grains of Å or less, and the size and distribution of grain sizes differ slightly depending on the deposition conditions of amorphous silicon, the material of the underlying layer, and its surface. Furthermore, electron beam annealing and laser beam annealing have problems in that the equipment is expensive and the throughput is low. Furthermore, since these beam annealing methods obtain a polycrystalline silicon film with a desired area by scanning the beam, boundaries are inevitably created. Since the number of times the boundary region is irradiated with the beam is different from other regions, the grain size of the polycrystalline silicon also differs, and the electrical characteristics of the finally obtained TFT also differ. Therefore, an object of the present invention is to propose a method for producing TFTs with excellent and uniform electrical characteristics while obtaining polycrystalline silicon with a large crystal grain size at a high throughput.

[0005]

[Means for Solving the Problems] The present invention includes a step of forming amorphous silicon to be a source, drain, and channel portion on an insulating substrate or an insulating film to a thickness of 2000 Å or less, and then , a step of polycrystalizing the amorphous silicon by lamp annealing containing light of 500 nm or less to form a first polycrystalline silicon film, a step of forming a gate insulating film, and a step of forming a first polycrystalline silicon film, which is to become a gate electrode. Step 2 of forming polycrystalline silicon, then source,
A step of introducing impurities into the drain and gate electrode regions at a concentration of 1×10 15 /cm 2 or more by ion implantation, and then activating the ion-implanted impurities by lamp annealing that includes light with a wavelength of 350 nm or more and 500 nm or less. The method is characterized by comprising a step of forming an interlayer insulating film, a step of forming a contact hole, and a step of wiring with Al or the like.

[0006]

[Operation] Polycrystalline silicon is usually formed by the LPCVD method. When SiH4, which is commonly used, is used as a source gas, the deposited film becomes polycrystalline silicon when the deposition temperature is 580°C or higher, and amorphous silicon when the temperature is lower than that. Since the film formation rate is higher as the deposition temperature is higher, the deposition temperature is usually about 600 to 625°C. At temperatures below this temperature, the film formation rate becomes slow and the throughput of the apparatus decreases. Therefore, a film normally deposited by LPCVD is a so-called polycrystalline silicon film. On the other hand, the light transmittance of a polycrystalline silicon film is also dependent on the deposition temperature; a silicon film in an amorphous state has a low light transmittance, and a film in a polycrystalline state has a high light transmittance. In addition, the light transmittance is wavelength dependent, for example, 60
As shown in Figure 2, the transmittance of a 1000 Å polycrystalline silicon film deposited at 0°C is 2 at wavelengths of 500 nm or more.
0% or more, that is, such light energy is not absorbed by the polycrystalline silicon film. The present invention was made after experimentally confirming these facts, and has the following effects. When amorphous silicon with a thickness of about 1000 Å is irradiated with energy light with a wavelength of 400 to 500 nm,
Amorphous silicon absorbs that light energy well and quickly heats up. This temperature rise causes grains to grow in the amorphous silicon, turning it into polycrystalline silicon. The film made of polycrystalline silicon becomes transparent to light of the wavelength, and its temperature hardly rises when irradiated with the energy light. This is because when converting amorphous silicon into polycrystalline silicon, the quality of the final polycrystalline silicon film, that is, the crystal grain size, will change even if the power and irradiation time of the energy light irradiation changes. , which means that it is always kept constant. If the grain size of polycrystalline silicon is constant, the electrical characteristics of a TFT using this film as a semiconductor layer will be uniform and the reproducibility will be excellent.

[0007] Furthermore, when impurities such as phosphorus are ion-implanted into a polycrystalline silicon film and the implanted ions are activated, the same effect as described above is obtained. When ion-implanting phosphorus at a high concentration (for example, 3 x 1015/cm2) into polycrystalline silicon, the polycrystalline silicon film becomes amorphous and its light transmittance decreases, allowing it to sufficiently absorb the energy of light with a wavelength of about 500 nm. I come to do it. Therefore, when polycrystalline silicon into which the impurities have been ion-implanted is irradiated with lamp light containing light with a wavelength of 500 nm or less, the impurities are activated and, at the same time, the silicon film that has been made amorphous by the implantation is crystallized and its transparency is improved. Rise. As the transparency increases, most of the lamp light passes through the polycrystalline silicon film, and the degree of temperature rise in the polycrystalline silicon film becomes smaller. Figure 3 is
3×1015 phosphorus ions on 500 Å polycrystalline silicon
/cm2 implantation and lamp annealing, the annealing time and temperature rise characteristics of the polycrystalline silicon film are shown. In this experiment, the lamp power was kept constant and annealing was performed for a certain period of time. Curve A is t2 at 100% lamp output.
Curve B shows the case of annealing for t4 seconds at a lamp output of 80%. In curve A, the temperature rise characteristic is such that the temperature rises rapidly until the annealing time t1, but after t1 the temperature rise becomes gradual. Curve B also shows similar temperature rise characteristics. This means that even if the lamp annealing conditions, i.e. lamp power and annealing time, vary, the maximum temperature of polycrystalline silicon is almost constant, i.e. self-controlled, and therefore the activity of the impurities ultimately obtained. This means that the degree of oxidation and the quality of the polycrystalline silicon film are always constant. FIG. 4 shows the sheet resistance of a sample under the same conditions as FIG. 3. Lamp output is 70-
It can be seen that the obtained sheet resistance remains constant even if it varies between 100%. This result also shows that the quality of the polycrystalline silicon film obtained remains constant even if the lamp output varies. In addition, lamp annealing is basically a short-time heat treatment, and there is almost no diffusion of impurities during this time, so T
The effective channel length of the FT does not become short, which is advantageous for miniaturization of the TFT.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a cross-sectional view of a TFT showing an embodiment of the present invention in order of steps. First, as shown in Fig. 1(a), amorphous silicon 102 is deposited to a thickness of 1000 Å on a quartz substrate 101 by the LPCVD method, and then the wavelength
First lamp annealing is performed using light having an energy intensity peak in a range of 350 nm or more and 500 nm or less to convert the amorphous silicon into a first polycrystalline silicon film. Next, as shown in (b), the first polycrystalline silicon film is patterned into the shape that will become the source, drain, and channel regions of the TFT, and then the surface of the first polycrystalline silicon is thermally oxidized. Si oxidizes and becomes gate insulating film
1200 Å of O2 is formed (103). Due to this oxidation, the thickness of the first polycrystalline silicon film decreases.
It becomes 500 Å or less. Next, as shown in (c), the thickness is 3
Gate electrode 1 made of 500 Å second polycrystalline silicon
04 and then energize the phosphorus ion at 90KeV
, ion implantation is performed at an implantation amount of 3×10 15 /cm 2 , and impurities are introduced so that sources and drains (105a, 105b) can be formed in a self-aligned manner using the gate electrode as a mask. By this implantation, the polycrystalline silicon in the source and drain regions is converted to amorphous silicon. Next, a second lamp annealing is performed using light having a peak energy intensity in a wavelength range of 350 nm or more and 500 nm or less to activate the ion-implanted phosphorus. The second lamp annealing takes several tens of seconds to raise the temperature of the silicon film, which has been made amorphous by several hundred Å of ion implantation, to 800°C or higher, which is a temperature sufficient for activation. That's fine. Under the process conditions shown in FIG. 1, the second lamp annealing reduces the sheet resistance of the source and drain regions to 1 KΩ/□ or less. Almost 100% of the implanted phosphorus ions are activated, crystal defects caused by implantation are sufficiently annealed out, and good characteristics of the junction between the source and drain parts are obtained. Next, as shown in FIG. 1(d), SiO2 106 with a thickness of 8000 Å is formed as an interlayer insulating film by the CVD method, then a contact hole for taking out the electrode is opened, and finally an Al wiring 107 is formed. . TFTs manufactured by the above method not only have excellent electrical properties, but also have
TFT with uniform characteristics on substrates larger than 5 inches
can be formed.

Although the first lamp annealing is performed before depositing amorphous silicon and patterning it into a shape that will become the source, drain, and channel region of a TFT, it may be performed after the patterning. Further, although the second lamp annealing step is performed after implanting phosphorus ions, it may be performed after forming the interlayer insulating film. In this case, lamp annealing has the effect of activating the implanted ions, making the interlayer insulating film denser, and improving the adhesion of the interlayer insulating film to the underlying layer, thereby streamlining the process.

[0010]The gist of the present invention is to convert amorphous silicon into polycrystalline silicon by lamp annealing to obtain homogeneous polycrystalline silicon with a large grain size, so the present invention is applicable not only to the production of transistors. It can also be applied to the manufacture of elements such as resistors and diodes. In resistor manufacturing, it is possible to manufacture elements with uniform resistance values, and in diodes, it is possible to manufacture elements with small reverse leakage current, excellent electrical characteristics, and uniformity.

[0011]

As described above, according to the present invention, TFTs with excellent electrical characteristics and uniform electrical characteristics even within a large substrate can be manufactured with high throughput. Furthermore, in the present invention, polycrystallization of amorphous silicon and activation of implanted ions by lamp annealing are performed in a self-controlled manner, so even if there are variations in the conditions of the lamp annealing equipment, constant and uniform device characteristics can be maintained. can get.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a method for manufacturing a TFT according to the present invention.

FIG. 2 is a diagram showing the wavelength dependence of light transmittance of polycrystalline silicon.

FIG. 3 is a diagram showing the relationship between the annealing time of lamp annealing and the temperature rise of polycrystalline silicon.

FIG. 4 is a diagram showing the relationship between the lamp output of the lamp annealing device and the sheet resistance of ion-implanted polycrystalline silicon.

[Explanation of symbols] 101 Quartz substrate 102 Amorphous silicon 103 SiO2 104 Polycrystalline silicon 105a, 105b Source, drain 106
SiO2 107 Al

Claims (4)

[Claims] Claim 1: 200 mm of amorphous silicon is deposited on an insulating substrate or an insulating film to form the source, drain, and channel portions.
A process of forming with a thickness of 0 Å or less, and then a process of forming with a wavelength of 350 nm.
The above steps include a step of polycrystalizing the amorphous silicon to form a first polycrystalline silicon film by lamp annealing that includes light of 500 nm or less, a step of forming a gate insulating film, and a step of forming a gate electrode. A step of forming a second polycrystalline silicon, and then implanting impurities into the source, drain and gate electrode regions at a rate of 1×1015/c by ion implantation.
m2 or higher concentration, and then a wavelength of 350 nm.
A step of activating the ion-implanted impurity by lamp annealing containing light of 500 nm or more and 500 nm or less, next a step of forming an interlayer insulating film, next a step of opening a contact hole, and then a step of forming a contact hole, etc. 1. A method of manufacturing a semiconductor device, comprising a step of wiring. [Claim 2] The amorphous silicon film has a wavelength of 350 nm.
As described above, a method for manufacturing a semiconductor device is characterized in that the film is converted into a polycrystalline silicon film by irradiating energetic light containing light of 500 nm or less. [Claim 3] SiH4, S on an insulating substrate or an insulating film.
An amorphous silicon film is formed by low pressure CVD using silane gas such as i2H6, and the film is heated at a wavelength of 350 nm.
As described above, a method for manufacturing a semiconductor device is characterized in that the film is converted into a polycrystalline silicon film by irradiating energetic light containing light of 500 nm or less. 4. A polycrystalline silicon film is formed on an insulating substrate or an insulating film, and then ions of silicon or argon are implanted into the film to convert it into amorphous silicon. A method for manufacturing a semiconductor device, comprising converting the amorphous silicon film into a polycrystalline silicon film by irradiating energetic light including light with a wavelength of 350 nm or more and 500 nm or less.