JPH04288841A - Manufacture of schottky junction type field effect transistor - Google Patents

Abstract

PURPOSE:To provide a specified characteristic by forming a mask layer with an insulation material comprising SiO2, SiON or phosphosilicated glass or a different gate electrode layer which forms a laminated electrode body as a gate electrode layer by a metal layer having a low specific resistance. CONSTITUTION:A mask layer 11 is formed with an insulation material which comprises SiO2, SiON or phosphosilicated glass which is difficult to be etched by plasma ions of gas mainly composed of SF6 or CF4 used for electron cyclotron resonance plasma etching processing in a gate electrode layer 4 forming process. Or there is formed a different gate electrode layer which forms a laminated gate electrode body with the gate electrode layer 4 by a metal material having a low specific resistance. This construction makes it possible to manufacture easily Schottky junction type field effect transistors which show the functions of the prior art field effect transistors.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a Schottky junction field effect transistor.

0002

2. Description of the Related Art Conventionally, a Schottky junction field effect transistor has been proposed which will be described below with reference to FIG.

That is, it has a semiconductor substrate body 1 in which, for example, an n-type semiconductor active layer 3 is formed on the upper surface side of a semi-insulating semiconductor substrate 2 made of, for example, GaAs or on the semi-insulating semiconductor substrate 2 . The figure shows a case where the semiconductor active layer 3 is formed on the upper surface side of the semi-insulating semiconductor substrate 2 by implanting n-type impurity ions.

Further, a gate electrode layer 4 is formed on the semiconductor substrate 1, forming a Schottky junction 5 with the semiconductor active layer 3.

In this case, the gate electrode layer 4 is made of WSiN,
WSi, WN, WAl, TiW, TiN, MoSix
(where x is a positive number) and a high melting point metal material selected from TaSi, for example, a metal layer made of the metal material just mentioned is formed on the semiconductor substrate body 1, and then the metal layer S using a mask layer for
It is formed by electron cyclotron resonance etching using a gas mainly composed of F6 or CF4.

Furthermore, impurity ions are implanted into the semiconductor substrate 1 from the semiconductor active layer 3 side to both positions across the gate electrode layer 4 to give the same n type as the semiconductor active layer 3; A source region 6 and a drain region 7 having n+ type are formed by a subsequent thermal annealing process for activation.

Further, a source electrode layer 8 and a drain electrode layer 9 are ohmically applied on the source region 6 and drain region 7, respectively.

The above is the structure of the conventionally proposed Schottky junction field effect transistor.

According to the Schottky junction field effect transistor having such a structure, when a required power source is connected between the source electrode layer 8 and the drain electrode layer 9 through a load, the source electrode layer 8 and the drain electrode layer 9 are connected to each other through a load. When a control voltage is applied between the gate electrode layers 4, a depletion layer is formed in the semiconductor substrate 1 from the Schottky junction 5 and has a spread corresponding to the control voltage. A controlled current can be supplied according to the control voltage, and therefore, it functions as a field effect transistor.

[0010] Conventionally, as a method for manufacturing a Schottky junction field effect transistor similar to the conventional Schottky junction field effect transistor described above with reference to FIG. 13, a method described below with reference to FIGS. 14 to 17 has been proposed. .

In FIGS. 14 to 17, parts corresponding to those in FIG. 13 are designated by the same reference numerals, and detailed description thereof will be omitted.

The method for manufacturing the conventional Schottky junction field effect transistor shown in FIGS. 14 to 17 involves the following sequential steps to form a Schottky junction field effect transistor similar to the conventional Schottky junction field effect transistor shown in FIG. Manufacture type field effect transistors.

That is, it has a flat upper surface and is made of GaAs.
A semi-insulating semiconductor substrate 2 is prepared in advance (FIG. 14A).
).

[0014] In the semi-insulating semiconductor substrate 2,
An n-type semiconductor active layer 3 is formed by implanting n-type impurity ions, such as Si ions, from the upper surface side of the semi-insulating semiconductor substrate 2.
A semiconductor substrate body 1 is obtained in which a semiconductor active layer 3 having a mold is formed (FIG. 14B).

Next, a metal layer 4 forming a Schottky junction 5' with the semiconductor active layer 3 is placed on the semiconductor substrate body 1.
' is formed by, for example, sputtering method (Fig. 1
4C).

In this case, the metal layer 4' is made of WSiN, WS
It is made of a high melting point metal material selected from among i, WN, WAl, TiW, TiN, MoSix (where x is a positive number), and TaSi.

Next, a mask layer 11 is formed on the metal layer 4' (FIG. 15D).

In this case, the mask layer 11 is made of photoresist.

Next, by using the mask layer 11 as a mask for the metal layer 4', an electron cyclotron resonance plasma etching process is performed using plasma ions of a gas containing SF6 or CF4 as a main component, so that the metal layer 4' is etched between the metal layer 4' and the semiconductor active layer 3. The gate electrode layer 4 is formed by the region under the mask layer 11 of the metal layer 4' forming the Schottky junction 5 by a part of the Schottky junction 5' (FIG. 15E).

Next, the semiconductor active layer 3 is applied to the semiconductor substrate 1 using the gate electrode layer 4 and the mask layer 11 as a mask.
By implanting impurity ions, for example, Si ions, which give the same n-type characteristics as ' and 7' (Fig. 15F)
.

Next, mask layer 11 is removed from above gate electrode layer 4 (FIG. 16G).

Next, a protective layer 12 is formed on the semiconductor substrate 1 to cover and extend the gate electrode layer 14 (see FIG. 1).
6H).

In this case, the protective layer 12 is made of, for example, SiO2
, SiN or SiOx YY (where x and y
is a positive number), and is formed by, for example, a plasma CVD method.

Next, the impurity introduced regions 6' and 7' are activated by thermal annealing treatment at a temperature of, for example, 700° C. to 1200° C., and the activated sources are removed from them.
A source region 6 and a drain region 7 are obtained (FIG. 16I).

Next, from above the semiconductor substrate body 1, a protective layer 12 is formed.
is removed by, for example, a so-called wet etching process using a hydrofluoric acid etchant (FIG. 17J).

Next, a source electrode layer 8 and a drain electrode layer 9 are formed on the source region 6 and drain region 7, as shown in FIG.
Obtain a Schottky junction field effect transistor similar to the Schottky junction field effect transistor described above in 3.
Figure 17K).

The above is the conventional method for manufacturing a Schottky junction field effect transistor.

The Schottky junction field effect transistor (FIG. 17K) manufactured by the conventional Schottky junction field effect transistor manufacturing method described above has the same configuration as the conventional Schottky junction field effect transistor described above with reference to FIG. Therefore, it functions as a field effect transistor similar to the conventional Schottky junction field effect transistor described above with reference to FIG.

Furthermore, according to the conventional method for manufacturing a Schottky junction field effect transistor shown in FIGS. Transistors can be easily manufactured.

In addition, in the case of the conventional Schottky junction field effect transistor manufacturing method shown in FIGS. 14 to 17, impurity-introduced regions 6' and In the step (FIG. 16I) of activating these impurity-introduced regions 6' and 7' to obtain the source region 6 and drain region 7 from them (FIG. 16I) after the step of forming the impurity regions 6' and 7' (FIG. 15F), Thermal annealing treatment
Since this is carried out with the semiconductor substrate 1 covered with the protective layer 12, the step of activating the impurity introduced regions 6' and 7' and obtaining the source region 6 and drain region 7 from them ( In FIG. 16I), the elements of the semiconductor material constituting the semiconductor substrate body 1 are not unnecessarily scattered to the outside.

[0031] Also, the step of forming the metal layer 4' (FIG. 14)
In C), the metal layer 4' is made of WSiN, WSi,
WN, WAl, TiW, TiN, MoSix and Ta
The gate electrode layer 4 formed in the step of forming the gate electrode layer 4 (FIG. 14E) is made of a high melting point metal material selected from among Si, and therefore, the gate electrode layer 4 formed in the step of forming the gate electrode layer 4 (FIG. 14E) is made of a metal material with a high melting point selected from among Si, WSiN, WSi,
WN, WAl, TiW, TiN, MoSix and Ta
It is made of a high melting point metal material selected from among Si. Such metal materials have excellent heat resistance.

Therefore, by activating the impurity introduced regions 6' and 7' by thermal annealing, the source region 6
and the step of obtaining the drain region 7 (FIG. 16I),
The thermal annealing process can be performed at a high temperature as described above, and thus the source region 6 and drain region 7 can be obtained as sufficiently activated.

Furthermore, a step of forming the gate electrode layer 4 (
In FIG. 15E), the gate electrode layer 4 is
' is formed by electron cyclotron resonance plasma etching using plasma ions of a gas mainly composed of SF6 or CF4 using the mask layer 11 as a mask. As long as the metal layer 4' is irradiated perpendicularly to the top surface of the metal layer 4', the gate electrode layer 4 can be extended onto a plane whose side surface is perpendicular to the top surface of the semiconductor substrate 1. It can be formed as a thing. The main reason for this is that the plasma ions used for electron cyclotron resonance plasma etching processing can be obtained at a relatively low gas pressure in the etching chamber of an electron cyclotron resonance plasma etching device. It can be carried out in an atmosphere with a relatively low gas pressure, and therefore, during the electron cyclotron resonance plasma etching process, the density of plasma ions is relatively low. This is because, in addition to the plasma ions that irradiate the layer 4' perpendicularly to its top surface, there are not a large number of plasma ions that irradiate the metal layer 4' obliquely to its top surface due to collisions between plasma ions. .

For this reason, that is, the gate electrode layer 4 is
Since the protective layer 12 can be formed so that its side surface extends on a plane perpendicular to the upper surface of the semiconductor substrate 1, the protective layer 12 extends over the semiconductor substrate 1 to cover the gate electrode layer 4. (FIG. 16H), the protective layer 12
and the upper part of the gate electrode layer 4 in the thickness direction in the step of activating the impurity introduced regions 6' and 7' to form the source region 6 and the drain region 7 (FIG. 6I). Annie
It can be easily formed without creating relatively large spacings that would allow elements of the semiconductor material of which it is composed to escape from the semiconductor substrate body 1 during processing.

Furthermore, the plasma ions used in the electron cyclotron resonance plasma etching process in the step of forming the gate electrode layer 4 (FIG. 15E) are plasma ions obtained by plasmanizing SF6 or CF4 gas, and Alternatively, CF4 gas is easily available and has almost no adverse effect on the semiconductor substrate body 1.

From the above, according to the conventional method for manufacturing a Schottky junction field effect transistor shown in FIGS. 14 to 17, a Schottky junction field effect transistor having relatively good characteristics can be manufactured relatively easily. can be manufactured.

[0037]

[Problem to be Solved by the Invention] In the method for manufacturing the conventional Schottky junction field effect transistor described above with reference to FIGS. 14 to 17, the step of forming the gate electrode 4 (FIG. 15E)
It is desirable that the electron cyclotron resonance plasma etching process in step 4' be completed when the area of the metal layer 4' other than the area under the mask layer 11 is etched away, but in practice this is difficult. The etching process is performed by etching the mask layer 11 of the metal layer 4'.
The process ends when the area other than the bottom area has just been etched away. That is, so-called over-etching is performed. Therefore, the gate electrode layer 4 is obtained by side etching a certain amount of side etching taken from the side edge of the mask layer 11. However, in the case of the electron cyclotron resonance plasma etching process, the electron cyclotron resonance plasma etching process is performed until the area of the metal layer 4 other than the area under the mask layer 11 is just etched away (this is referred to as the first point). When the electron cyclotron resonance plasma etching process is performed at a 100% overetch rate, it is said that the electron cyclotron resonance plasma etching process is performed at a point beyond the above-mentioned first point (
This is generally referred to as the second time point), then the time from the start of the electron cyclotron resonance plasma etching process to the first time point (this is referred to as To
When the time from the first time point to the second time point (denoted as Ta) is 100% a%, the electron cyclotron resonance plasma etching process is
When it is said that the process was carried out at an over-etching rate (%) of 100+a)% (this is referred to as an over-etching rate F (%)), the over-etching rate F (%) of the metal layer 4' Since the etching characteristics obtained in terms of the etching amount relative to the etching amount are obtained as saturation characteristics, unless the mask layer 11 is etched to become narrow by plasma ions, the side etching amount will be reduced immediately before the start of the electron cyclotron resonance plasma etching process. When viewed from the side edges of the mask layer 11 in , the over-etching rate F (%) can be obtained at a substantially constant value regardless of the value.

However, since the mask layer 11 is made of photoresist and has relatively low etching resistance to the plasma ions used in the electron cyclotron resonance plasma etching process, the mask layer 11 is exposed to metal particles caused by plasma ions even from its side surfaces. The mask layer 11 is etched by an amount corresponding to the etching time for the layer 4', so that the mask layer 11 becomes narrower as shown by the chain line from the original state shown by the solid line in FIG.
The electrode layer 4 is formed to have a shorter length, as shown by the chain line in FIG. 15E, than the intended length shown by the solid line.

For this reason, in the case of the conventional Schottky junction field effect transistor manufacturing method described above with reference to FIGS. It was extremely difficult to create something with such characteristics.

Therefore, in the case of the conventional Schottky junction field effect transistor manufacturing method described above with reference to FIGS. 14 to 17,
The drawback is that it is extremely difficult to manufacture a Schottky junction field effect transistor with desired characteristics.

Accordingly, the present invention aims to propose a novel method for manufacturing a Schottky junction field effect transistor that does not have the above-mentioned drawbacks.

[0042]

[Means for Solving the Problems] A method for manufacturing a Schottky junction field effect transistor according to the present invention is shown in FIGS.
As in the case of the conventional Schottky junction field effect transistor manufacturing method described above, (a) a semiconductor active layer having a desired conductivity type is formed on the upper surface side of the semi-insulating semiconductor substrate or on the semi-insulating semiconductor substrate; A step of preparing a semiconductor substrate to be formed; (b) WSi on the semiconductor substrate;
N, WSi, WN, WAl, TiW, TiN, MoSi
(c) forming a metal layer made of a high melting point metal material selected from x (where x is a positive number) and TaSi and forming a Schottky junction with the semiconductor active layer; forming a mask layer on the metal layer;
(d) Electron cyclotron resonance plasma etching treatment is performed on the metal layer using the mask layer as a mask and using plasma ions of a gas mainly composed of SF6 or CF4 to remove the metal layer from the metal layer below the mask layer. a step of forming a gate electrode layer by a region;
e) In the semiconductor substrate body, from the semiconductor active layer side,
forming a semiconductor source region and a semiconductor drain region having the same conductivity type as the semiconductor active layer at both positions sandwiching the gate electrode layer.

However, in the method for manufacturing a Schottky junction field effect transistor according to the present invention, (f) in the step of forming the mask layer, the mask layer is -S used in the electron cyclotron resonance plasma etching process in the step of forming the electrode layer.
(i) SiO2, which is difficult to be etched by plasma ions of gas mainly composed of F6 or CF4;
SiON or phosphosilicate glass (PS
G) or formed of an insulating material consisting of (i
i) A metal material having low specific resistance is used as another gate electrode layer that forms a stacked gate electrode body together with the gate electrode layer.

[0044]

[Operations/Effects] In the method for manufacturing a Schottky junction field effect transistor according to the present invention, in the step of forming a mask layer in the conventional method for manufacturing a Schottky junction field effect transistor described above with reference to FIGS.
SF6 or CF4 used in electron cyclotron resonance plasma etching treatment in the process of forming the gate electrode layer instead of using photoresist.
(i) formed of an insulating material made of SiO2, SiON or phosphosilicate glass (PSG), which is difficult to be etched by plasma ions of a gas mainly composed of; or (ii) a metal having a low specific resistance. Depending on the material, the conventional Schottky junction field effect described above with reference to FIGS. This is similar to the method for manufacturing transistors.

Therefore, as in the case of the manufacturing method of the conventional Schottky junction field effect transistor described above with reference to FIGS. 14 to 17, a field effect transistor similar to the conventional Schottky junction field effect transistor described above with reference to FIG. A Schottky junction field effect transistor exhibiting the following functions can be easily manufactured.

Furthermore, according to the method for manufacturing a Schottky junction field effect transistor according to the present invention, the step of forming a metal layer is performed in the same manner as in the method for manufacturing a conventional Schottky junction field effect transistor described above with reference to FIGS. 14 to 17. In,
The metal layer is made of WSiN, WSi, WN, WAl, Ti.
The gate electrode layer is formed of a metal material selected from W, TiN, MoSix, and TaSi, and therefore, the gate electrode layer formed in the process of forming the gate electrode layer is WSiN, WS
i, WN, WAl, TiW, TiN, MoSix and T
It is made of a metal material selected from aSi. Such metal materials have excellent heat resistance.

Therefore, in the step of forming the source region and the drain region, when the source region and the drain region are obtained by thermal annealing, the source region and the drain region are
The source and drain regions can be obtained as fully activated for the reasons described in the case of the conventional Schottky junction field effect transistor manufacturing method described above with reference to FIGS. 14-17.

In addition, in the step of forming the gate electrode layer, the gate electrode layer is formed by forming a metal layer as in the case of the conventional Schottky junction field effect transistor manufacturing method described above with reference to FIGS. 14 to 17. Since the gate electrode layer is formed by electron cyclotron resonance plasma etching using plasma ions of a gas mainly composed of SF6 or CF4 using a mask layer as a mask, the side surface of the gate electrode layer is formed on the upper surface of the semiconductor substrate. For the same reasons as in the case of the conventional Schottky junction field effect transistor manufacturing method described above with reference to FIGS. As in the case of the manufacturing method of the conventional Schottky junction field effect transistor described above with reference to FIGS. 14 to 17, it can be manufactured relatively easily as it has relatively good characteristics.

However, in the method of manufacturing the Schottky junction field effect transistor according to the present invention, in the step of forming the mask layer used for forming the gate electrode layer from the metal layer by electron cyclotron resonance plasma etching, the mask is The layer is difficult to be etched by plasma ions of a gas mainly composed of SF6 or CF4 used in the electron cyclotron resonance plasma etching process in the process of forming the gate electrode layer.
(i) formed of an insulating material such as SiO2, SiON or phosphosilicate glass (PSG); or (ii) formed of a metal material with low resistivity and laminated with a gate electrode layer. It is formed as another gate electrode layer forming the electrode body.

Therefore, according to the method for manufacturing a Schottky junction field effect transistor according to the present invention, the electron cyclotron resonance plasma etching process using the mask layer as a mask for the metal layer for forming the gate electrode layer can be performed automatically. Even when bar etching is performed, the mask layer is hardly etched, or if it is etched, it is etched by a much smaller amount than in the conventional Schottky junction field effect transistor manufacturing method.

Therefore, according to the method for manufacturing a Schottky junction field effect transistor according to the present invention, the gate electrode layer is
It can be easily formed to have a predetermined length, and therefore, a Schottky junction field effect transistor can be easily manufactured to have desired characteristics.

Further, according to the method for manufacturing a Schottky junction field effect transistor according to the present invention, in the step of forming a mask layer, the mask layer is laminated with a gate electrode layer using a metal material having a low resistivity. When the gate electrode layer is formed as another gate electrode layer forming the gate electrode body, even if the gate electrode layer other than the gate electrode layer formed by the mask layer has a relatively high resistivity, the present invention Since the resistance of the gate of the Schottky junction field effect transistor manufactured by the method is reduced, the Schottky junction field effect transistor can be manufactured to operate at high speed.

[0053]

[Embodiment 1] Next, a first embodiment of the method for manufacturing a Schottky junction field effect transistor according to the present invention will be explained with reference to FIGS. 1 to 5. Let us discuss the case of manufacturing a Schottky junction field effect transistor. In FIGS. 1 to 5, parts corresponding to those in FIGS. 14 to 17 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The embodiment of the method for manufacturing the Schottky junction field effect transistor according to the present invention shown in FIGS. 1 to 5 is similar to the Schottky junction field effect transistor described above with reference to FIG. A Schottky junction field effect transistor is manufactured.

That is, a semi-insulating semiconductor substrate 2 similar to that described above in the step of FIG. 14A in the conventional Schottky junction field effect transistor manufacturing method described above with reference to FIGS. 14 to 17 is prepared in advance (FIG. 1A).

[0056] In the semi-insulating semiconductor substrate 2,
A semiconductor active layer 3 similar to that described above in the step of FIG. 14B in the conventional Schottky junction field effect transistor manufacturing method described above with reference to FIGS. A semiconductor substrate body 1 similar to that described above is obtained in the step of FIG. 14B in the conventional Schottky junction field effect transistor manufacturing method (FIG. 1B).

14 to 1 on the semiconductor substrate body 1.
In the same manner as described above in the step of FIG. 14C in the conventional Schottky junction field effect transistor manufacturing method described above in Section 7, the Schottky junction 5' is formed with the same metal material and with the semiconductor active layer 3. A metal layer 4' is formed in a similar manner to a thickness of, for example, 0.1 μm to 1.0 μm (FIG. 1C).

Next, a mask material layer 21 is formed on the metal layer 4'.
' is formed to a thickness of, for example, 0.05 μm to 0.5 μm by sputtering, plasma CVD, or the like (FIG. 2D).

In this case, the mask material layer 21' is made of SiO
2. Made of SiON or phosphosilicate glass (PSG).

Next, the mask material layer 21' is subjected to a reactive ion etching process using a fluoride, for example, CF4, using the mask layer 22 as a mask, to remove the mask material layer 21' from the mask material layer 21' as described above in FIGS. 14 to 17. Figure 14 shows the conventional Schottky junction field effect transistor manufacturing method.
A mask layer 21 is formed which corresponds to the mask layer 11 formed in step C but is made of a different material (FIG. 2F).

Next, mask layer 22 is removed from above mask layer 21 (FIG. 3G).

Next, in accordance with the process shown in FIG. 15E in the conventional Schottky junction field effect transistor manufacturing method described above with reference to FIGS. 14 to 17, SF6 or CF4 is applied to the metal layer 4' using the mask layer 21 as a mask. The gate electrode layer 4 is formed by the region under the mask layer 21 of the metal layer 4' forming the Schottky junction 5 by electron cyclotron resonance plasma etching using plasma ions of a gas mainly composed of (Figure 3H).

Next, the gate electrode layer 4 and the mask layer 21 on the semiconductor substrate 1 are masked in accordance with the process shown in FIG. 15F in the conventional Schottky junction field effect transistor manufacturing method described above with reference to FIGS. By implanting impurity ions that give n-type conductivity, a structure similar to that formed in the step of FIG. 15F in the conventional Schottky junction field effect transistor manufacturing method described above in FIGS. 14 to 17 is Similar source regions 6' and 7' are similarly formed (FIG. 3I).

Next, the mask layer 21 is removed from above the gate electrode layer 4 in the same manner as in the step shown in FIG. 16G in the conventional Schottky junction field effect transistor manufacturing method described above with reference to FIGS. 14 to 17. (Figure 4J).

14 to 1 on the semiconductor substrate body 1.
A protective layer 12 similar to that in the step of FIG. 16H in the conventional Schottky junction field effect transistor manufacturing method described above in Section 7 is formed in the same manner (FIG. 4K).

Next, as in the step of FIG. 16I in the conventional Schottky junction field effect transistor manufacturing method described above with reference to FIGS. 14 to 17, impurity introduced regions 6' and 7' are activated and their From this, an activated source region 6 and drain region 7 are obtained (FIG. 4L).

Next, from above the semiconductor substrate body 1, the protective layer 12 is
is removed in the same manner as in the step of FIG. 17I of the conventional Schottky junction field effect transistor manufacturing method described above with reference to FIGS. 14 to 17 (FIG. 5M).

Next, a source electrode is formed on the source region 6 and the drain region 7 in the same manner as in the step of FIG. 17K of the conventional Schottky junction field effect transistor manufacturing method described above with reference to FIGS. Layer 8 and drain electrode layer 9 are applied to obtain a Schottky junction field effect transistor similar to the Schottky junction field effect transistor described above with reference to FIG. 13 (FIG. 5N).

The above is the first embodiment of the method for manufacturing a Schottky junction field effect transistor according to the present invention.

According to the method for manufacturing a Schottky junction field effect transistor according to the present invention, a mask layer used for forming the gate electrode layer 4 from the metal layer 4' by electron cyclotron resonance plasma etching is formed. In the process, the mask layer is formed as the mask layer 11 using photoresist.
The conventional Schottky junction field effect transistor described above in FIGS. Since the manufacturing method is the same as that of the conventional Schottky junction field effect transistor, a detailed explanation will be omitted. A functional Schottky junction field effect transistor can be easily manufactured.

In addition, as in the case of the conventional Schottky junction field effect transistor manufacturing method described above with reference to FIGS. After the step of forming regions 6' and 7' (FIG. 1G), the step of activating these impurity-introduced regions 6' and 7' to obtain source region 6 and drain region 7 from them (FIG. 3I) ), the thermal annealing process is performed with the semiconductor substrate 1 covered with the protective layer 12, so the impurity introduced regions 6' and 7' are activated and the source is removed from them. In the step of obtaining the source region 6 and drain region 7 (FIG. 3I), the elements of the semiconductor material constituting the semiconductor substrate body 1 are not unnecessarily scattered to the outside.

Further, the step of forming the metal layer 4' (FIG. 1C)
), the metal layer 4' is made of WSiN, WSi, WN, WAl, WSiN, WSi, WN, WAl,
The gate electrode layer 4 formed in the step of forming the gate electrode layer 4 (FIG. 3H) is formed of a metal material selected from TiW, TiN, MoSix, and TaSi. WN, WAl, TiW, TiN,
It is made of a metal material selected from MoSix and TaSi. Such metal materials have excellent heat resistance. Therefore, in the step (FIG. 3I) of activating impurity introduced regions 6' and 7' by thermal annealing treatment to obtain source region 6 and drain region 7, the thermal annealing treatment is performed at a high temperature. can be done with, thus,
The source region 6' and drain region 7' can be sufficiently activated.

Furthermore, a step of forming the gate electrode layer 4 (
In FIG. 3H), the gate electrode layer 4 is formed using a mask layer 21 as a mask for the metal layer 4', as in the case of manufacturing the conventional Schottky junction field effect transistor described above with reference to FIGS. 14 to 17. Since it is formed by an electron cyclotron resonance plasma etching process using plasma ions of a gas containing SF6 or CF4 as a main component, it is different from the conventional Schottky junction field effect transistor manufacturing method described above in FIGS. 14 to 17. Similarly, game
The top electrode layer 4 can be formed so that its side surface extends on a plane perpendicular to the top surface of the semiconductor substrate body 1. Therefore, in the step of forming the protective layer 12 extending over the gate electrode layer 4 on the semiconductor substrate 1 (FIG. 4K), the protective layer 12 is formed in the thickness direction of the gate electrode layer 4. During the thermal annealing process in the step (FIG. 4L) of activating the impurity introduced regions 6' and 7' to form the source and drain regions, it is formed from the semiconductor substrate 1. It can be formed without creating any spacing that would allow the elements of the semiconductor material containing the material to dissipate.

Furthermore, the plasma ions used in the electron cyclotron resonance plasma etching process in the step of forming the gate electrode layer 4 (FIG. 3H) are SF6 or C
These are plasma ions obtained by turning F4 gas into plasma, and SF6 or CF4 gas is easily available and has almost no adverse effect on the semiconductor substrate 1.

From the above, in the case of the manufacturing method of the Schottky junction field effect transistor according to the present invention, the method shown in FIGS.
Similar to the method for manufacturing the conventional Schottky junction field effect transistor described above with reference to FIG. 17, a Schottky junction field effect transistor having relatively good characteristics can be manufactured relatively easily.

However, in the case of the Schottky junction field effect transistor according to the present invention shown in FIGS. 1 to 5, the mask layer 21 is used to form the gate electrode layer 4 from the metal layer 4' by electron cyclotron resonance plasma etching. In the step of forming the gate electrode layer 4 (FIGS. 2D to 2G), the mask layer 21 is exposed to plasma ions of a gas mainly composed of SF6 or CF4 used in the electron cyclotron resonance plasma etching process in the step of forming the gate electrode layer 4. SiO2, which is difficult to be etched by
, SiON or PSG.

Therefore, according to the method for manufacturing a Schottky junction field effect transistor according to the present invention shown in FIGS. 1 to 5, the mask layer 21 for the metal layer 4' for forming the gate electrode layer 4 is used as a mask. Even if the electron cyclotron resonance plasma etching treatment is performed by over-etching, the gate electrode layer 4 can be formed with a predetermined side etching amount as shown in FIG. The layer 21 is, as shown in FIG.
If there is little or no etching, Figure 1
Etching is performed by a much smaller amount than in the case of the conventional Schottky junction field effect transistor manufacturing method described above with reference to FIGS. 4 to 17.

Therefore, according to the method of manufacturing a Schottky junction field effect transistor according to the present invention shown in FIGS. 1 to 5,
The gate electrode layer 4 can be easily formed to have a predetermined length, so that a Schottky junction field effect transistor having desired characteristics can be easily manufactured.

[0079]

[Example 2]

Next, with reference to FIGS. 8 to 12, a second method of manufacturing a Schottky junction field effect transistor according to the present invention will be described.
Let's describe an example.

In FIGS. 8 to 12, parts corresponding to those in FIGS. 1 to 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The method for manufacturing the Schottky junction field effect transistor according to the present invention shown in FIGS. A Schottky junction field effect transistor similar to that manufactured by the method described above is manufactured.

That is, as shown in FIGS. 8 to 10, the same sequential steps as those in the method for manufacturing the Schottky junction field effect transistor according to the present invention described above with reference to FIGS. 1 to 3 are performed.

However, the mask material layer 21 is formed on the metal layer 4'.
In the step of FIG. 8C corresponding to the step of FIG. 1C for forming 4', a mask material layer 23' made of a metal material having low resistivity such as Au, Al, Pt, etc. is formed on the metal layer 4', and In the step of FIG. 10H corresponding to the step of FIG. 3H for forming the mask layer 21, a laminated gate electrode body 24 is formed by forming the mask layer 23 from the mask material layer 23' and the gate electrode layer 4. Then, another gate electrode layer is formed. Therefore, the mask material layer 21' is replaced by the mask material layer 23'.
', and the mask layer 21 is read as the mask layer 23, and the steps are similar to the sequential steps of the method for manufacturing the Schottky junction field effect transistor according to the present invention described above with reference to FIGS. 1 to 5.

Next, as shown in FIGS. 11 and 12, FIG.
The step of removing the mask layer in the method for manufacturing a Schottky junction field effect transistor according to the present invention described above in FIG. , a Schottky junction field effect transistor similar to the Schottky junction field effect transistor described above with reference to FIG. 5N is similarly obtained (FIG. 12M).

The above is the second embodiment of the method for manufacturing a Schottky junction field effect transistor according to the present invention.

According to the method for manufacturing a Schottky junction field effect transistor according to the present invention, a mask layer used for forming the gate electrode layer 4 from the metal layer 4' by electron cyclotron resonance plasma etching is formed. In the process, the mask layer is made of SiO2, S
Instead of the method of manufacturing the Schottky junction field effect transistor according to the present invention described above with reference to FIGS. 1 to 5, in which the mask layer 21 is formed of iON or PSG, the mask layer 23 is formed of a metal material having a low resistivity. 1-1, except that it is not removed and left as a gate electrode layer, which is a stacked gate electrode body 24.
This is similar to the method for manufacturing the Schottky junction field effect transistor according to the present invention described above with reference to FIG. Although a detailed explanation will be omitted, it is clear that the same effects as those of the method for manufacturing the Schottky junction field effect transistor according to the present invention described above with reference to FIGS. 1 to 5 can be obtained.

Furthermore, according to the method for manufacturing a Schottky junction field effect transistor according to the present invention shown in FIGS. 8 to 12,
In the step of forming the mask layer 23 (FIGS. 8C to 10H), the mask layer 23 is formed into a laminated gate electrode body 24 together with the gate electrode layer 4 using a metal material having a low specific resistance.
Since it is formed as another gate electrode layer to form
Gate electrode layer 4 that is not a gate electrode layer due to mask layer 23
However, even if the Schottky junction field effect transistor has a relatively high resistivity, the gate resistance of the manufactured Schottky junction field effect transistor will be low, so the Schottky junction field effect transistor can be manufactured as a device that operates at high speed. can do.

[0089]

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of sequential steps showing a first embodiment of a method for manufacturing a Schottky junction field effect transistor according to the present invention.

2A and 2B are schematic cross-sectional views showing a first embodiment of the method for manufacturing a Schottky junction field effect transistor according to the present invention, in successive steps following the steps in FIG. 1; FIG.

3A and 3B are schematic cross-sectional views showing a first embodiment of the method for manufacturing a Schottky junction field effect transistor according to the present invention, in successive steps following the steps in FIG. 2; FIG.

4A and 4B are schematic cross-sectional views showing a first embodiment of the method for manufacturing a Schottky junction field effect transistor according to the present invention, in successive steps following the steps in FIG. 3;

5A and 5B are schematic cross-sectional views showing a first embodiment of the method for manufacturing a Schottky junction field effect transistor according to the present invention, in successive steps following the steps in FIG. 4; FIG.

FIG. 6: Gas in an electron cyclotron resonance plasma etching apparatus when forming a gate electrode layer by electron cyclotron resonance plasma etching treatment on a metal layer, for explaining the method for manufacturing a Schottky junction field effect transistor according to the present invention. FIG. 3 is a diagram showing the relationship between the side etching amount of the gate electrode layer and the overetching rate (%) for the metal layer, with pressure as a parameter.

FIG. 7 is a diagram illustrating a method for manufacturing a Schottky junction field effect transistor according to the present invention, showing the difference between a mask layer and a metal layer when forming a gate electrode layer by electron cyclotron resonance plasma etching using the mask layer as a mask. FIG. 2 is a diagram showing the amount of lateral etching versus etching time in comparison with a mask layer used in a conventional method for manufacturing a Schottky junction field effect transistor.

FIGS. 8A and 8B are schematic cross-sectional views showing sequential steps of a second embodiment of the method for manufacturing a Schottky junction field effect transistor according to the present invention; FIGS.

9 is a schematic cross-sectional view showing a second embodiment of the method for manufacturing a Schottky junction field effect transistor according to the present invention, in successive steps following the steps in FIG. 8; FIG.

10A and 10B are schematic cross-sectional views showing a second embodiment of the method for manufacturing a Schottky junction field effect transistor according to the present invention, in successive steps following the steps in FIG. 9;

11A and 11B are schematic cross-sectional views showing a second embodiment of the method for manufacturing a Schottky junction field effect transistor according to the present invention, in successive steps following the steps in FIG. 10;

12A and 12B are schematic cross-sectional views showing a second embodiment of the method for manufacturing a Schottky junction field effect transistor according to the present invention, in successive steps subsequent to the steps in FIG. 11;

FIG. 13 is a schematic cross-sectional view showing a Schottky junction field effect transistor similar to that manufactured by the method for manufacturing a Schottky junction field effect transistor according to the present invention and the conventional method for manufacturing a Schottky junction field effect transistor.

FIGS. 14A and 14B are schematic cross-sectional views showing sequential steps in a conventional Schottky junction field effect transistor manufacturing method.

15A and 15B are schematic cross-sectional views showing a conventional method for manufacturing a Schottky junction field effect transistor in successive steps subsequent to the steps in FIG. 14;

16A and 16B are schematic cross-sectional views showing a conventional method for manufacturing a Schottky junction field effect transistor in successive steps subsequent to the steps in FIG. 15. FIG.

17A and 17B are schematic cross-sectional views showing a conventional method for manufacturing a Schottky junction field effect transistor in sequential steps following the sequential steps shown in FIG. 16. FIG.

[Explanation of symbols]

1 Semiconductor substrate body 2
Semi-insulating semiconductor substrate 3
Semiconductor active layer 4
Gate electrode layer 4'
metal layer

Claims (2)

[Claims] 1. A step of preparing a semiconductor substrate body in which a semiconductor active layer having a desired conductivity type is formed on the upper surface side of a semi-insulating semiconductor substrate or on the semi-insulating semiconductor substrate; Above, WSiN, WSi, WN, W
A metal layer is formed of a high melting point metal material selected from among Al, TiW, TiN, MoSix (where x is a positive number) and TaSi, and forms a Schottky junction with the semiconductor active layer. a step of forming a mask layer on the metal layer; and electron cyclotron resonance plasma etching of the metal layer using plasma ions of a gas mainly composed of SF6 or CF4, using the mask layer as a mask. A step of forming a gate electrode layer from the metal layer by a region under the mask layer, and a step of forming a gate electrode layer in the semiconductor substrate body from the semiconductor active layer side with the gate electrode layer sandwiched therebetween. In the method for manufacturing a Schottky junction field effect transistor, the method includes forming a semiconductor source region and a semiconductor drain region having the same conductivity type as the semiconductor active layer in the step of forming the mask layer. The S layer is used in the electron cyclotron resonance plasma etching process in the step of forming the gate electrode layer.
SiO2 and SiO, which are difficult to be etched by plasma ions of gases mainly composed of F6 or CF4.
A method for manufacturing a Schottky junction field effect transistor, characterized in that it is formed from an insulating material made of N or phosphosilicate glass (PSG). 2. A step of preparing a semiconductor substrate body in which a semiconductor active layer having a desired conductivity type is formed on the upper surface side of a semi-insulating semiconductor substrate or on the semi-insulating semiconductor substrate; Above, WSiN, WSi, WN, W
A metal layer is formed of a high melting point metal material selected from among Al, TiW, TiN, MoSix (where x is a positive number) and TaSi, and forms a Schottky junction with the semiconductor active layer. a step of forming a mask layer on the metal layer; and electron cyclotron resonance plasma etching of the metal layer using plasma ions of a gas mainly composed of SF6 or CF4, using the mask layer as a mask. A step of forming a gate electrode layer from the metal layer in a region under the mask layer by processing, and forming the gate electrode layer on the semiconductor active layer side in the semiconductor substrate body or on the semiconductor substrate body. Forming the mask layer in a method for manufacturing a Schottky junction field effect transistor, which includes forming a semiconductor source region and a semiconductor drain region having the same conductivity type as the semiconductor active layer at both positions across the layer. In the step, the mask layer has a low specific resistance that is difficult to be etched by plasma ions of a gas mainly composed of SF6 or CF4 used in the electron cyclotron resonance plasma etching treatment in the step of forming the gate electrode layer. A method for manufacturing a Schottky junction field effect transistor, characterized in that another gate electrode layer which forms a laminated gate electrode body with the gate electrode layer is formed of a metal material.