JP2869546B2 - Manufacturing method of Schottky junction type field effect transistor - Google Patents

Description

The present invention relates to a method for producing a Schottky junction field effect transistor.

[Prior Art] Conventionally, a Schottky junction type field effect transistor described below with reference to FIG. 6 has been proposed.

That is, there is a semiconductor substrate 1 in which, for example, a semiconductor active layer 3 having, for example, an n-type is formed on the upper surface side of the semi-insulating semiconductor substrate 2 made of GaAs or on the semi-insulating semiconductor substrate 2. The figure shows a case where the semiconductor active layer 3 is formed on the upper surface side in the semi-insulating semiconductor substrate 2 by implanting n-type impurities. A gate electrode layer 4 forming a Schottky junction 5 with the semiconductor active layer 3 is formed on the semiconductor substrate 1.

In this case, the gate electrode layer 4 is made of WSiN, WSi, WN, WAl,
A metal layer made of a metal material selected from TiW, TiN, MoSi _x (where x is a positive number) and TaSi, for example, a metal layer made of the metal material just described by sputtering is used as the semiconductor substrate 1.
On the metal layer and then by etching using a mask layer for the metal layer.

Furthermore, in the semiconductor substrate 1, from both sides of the semiconductor active layer 3, at both positions sandwiching the gate electrode layer 4, the same n-type impurity ions as those of the semiconductor active layer 3 are implanted.
A source region 6 and a drain region 7 having an n ⁺ type formed by a thermal annealing process for subsequent activation are formed.

A source electrode layer 8 and a drain electrode layer 9 are provided on the source region 6 and the drain region 7 in ohmic contact, respectively.

The above is the configuration of the conventionally proposed Schottky junction field effect transistor.

According to the Schottky junction type field effect transistor having such a configuration, the control between the source electrode layer 8 and the gate electrode layer 4 is performed while a required power source is connected between the source electrode layer 8 and the drain electrode layer 9 through a load. When a voltage is applied, a depletion layer having an extension according to the control voltage is formed from the Schottky junction 5 in the semiconductor substrate body 1, so that a current controlled from the power supply by the load according to the control voltage is applied to the load. , And thus has a function as a field effect transistor.

Conventionally, a method described below with reference to FIG. 7 has been proposed as a method of manufacturing a Schottky junction field effect transistor similar to the conventional Schottky field effect transistor described above with reference to FIG.

7, parts corresponding to those in FIG. 6 are denoted by the same reference numerals, and detailed description will be omitted.

The method of manufacturing the conventional Schottky junction field effect transistor shown in FIG.
A Schottky junction field effect transistor similar to the conventional Schottky field effect transistor described above with reference to the drawing is manufactured.

That is, a semi-insulating semiconductor substrate 2 having a flat upper surface and made of GaAs is prepared in advance (FIG. 7A).

Then, an n-type semiconductor active layer 3 is formed in the semi-insulating semiconductor substrate 2 by implanting n-type impurity ions made of, for example, Si ions from its upper surface side. A semiconductor substrate 1 having an n-type semiconductor active layer 3 formed on the upper surface side in 2 is obtained (FIG. 7B).

Next, a metal layer 4 'forming a Schottky junction 5' with the semiconductor active layer 3 is formed on the semiconductor substrate 1 by, for example, a sputtering method (FIG. 7C).

In this case, the metal layer 4 'is made of WSiN, WSi, WN, WAl, Ti
It is made of a metal material selected from W, TiN, MoSi _x and TaSi.

Next, a mask layer 11 made of, for example, a photoresist is formed on the metal layer 4 '(FIG. 7D).

Next, a mask of the metal layer 4 'is formed by performing an etching process on the metal layer 4' using the mask layer 11 as a mask, and forming a Schottky junction 5 by a part of the Schottky junction 5 'with the semiconductor active layer 3. The gate electrode layer 4 is formed by the region below the layer 11 (FIG. 7E).

 In this case, a high frequency plasma etching apparatus is used.

The high-frequency plasma etching apparatus is denoted by reference numeral 20 in FIG. 8 and has a flat sample mounting surface 25a and a conductive sample mounting table 25, and a sample mounting table 25 of the sample mounting table 25. Forming an etching chamber 22 having an electrode plate 26 having a surface 26a facing in parallel with the mounting surface 25a, and a gas containing SF ₆ or CF ₄ as a main component in the etching chamber 22. Gas introduction tube 23 for introducing gas, and etching chamber 22
A container 21 leading out an exhaust pipe 24 for exhausting the inside
Having.

Further, the high-frequency plasma etching apparatus 20 includes an electrode plate 26
And a high-frequency source 27 connected between the apparatus and the sample mounting table 25.

Then, an etching process for forming the gate electrode layer 4 is performed on the sample mounting surface 25a of the sample mounting table 25 disposed in the etching chamber 22 of the high-frequency plasma etching apparatus 20 described above. A semiconductor substrate body 1 having a metal layer 4 ′ on which a mask layer 11 is formed is formed on the upper surface, and the semi-insulating semiconductor substrate 2 is arranged on the sample mounting surface 25 a side. While exhausting the inside of the etching chamber 22 through the exhaust pipe 24, the gas introduction pipe 23 is inserted into the etching chamber 22.
Through which a gas containing SF ₆ or CF ₄ as a main component is introduced,
The gas is converted into plasma by a high-frequency current from a high-frequency power supply 27, and plasma etching is performed by irradiating the plasma ions to the upper surface of the metal layer 4 'vertically.

In the conventional method of manufacturing a Schottky junction field effect transistor shown in FIG. 7, after forming the gate electrode layer 4 as described above, the mask layer 11 is removed from the gate electrode layer 4 (FIG. 7F). ).

Next, the semiconductor substrate 1 is given the same n-type as the semiconductor active layer 3 using the gate electrode layer 4 as a mask.
By implanting impurity ions made of ions, the gate electrode layer 4 is formed in the semiconductor substrate 1 from the semiconductor active layer 3 side.
Source region 6 'having an n ⁺ type
And a drain region 7 'is formed (FIG. 7G).

Next, a protective layer 12 extending over the gate electrode layer 14 is formed on the semiconductor substrate 1 (FIG. 7H).

The protective layer 12 is made of, for example, SiO ₂ , SiN, or SiO _x Y _Y (where x and y are positive numbers).
It is formed by the method.

Next, the source region 6 'and the drain region 7' are activated by, for example, a thermal annealing process at a temperature of 700 DEG C. to 1200 DEG C. to obtain the activated source region 6 and drain region 7 (FIG. 7I).

Next, the protective layer 12 is removed from the semiconductor substrate 1 by a so-called wet etching process using a hydrofluoric acid-based etchant (FIG. 7J).

Next, a source electrode layer 8 and a drain electrode layer 9 are formed on the source region 6 and the drain region 7, and a Schottky junction field effect transistor similar to the Schottky junction field effect transistor described above with reference to FIG. 8 is obtained. (FIG. 7K).

The above is the method of manufacturing the conventional Schottky junction type field effect transistor.

The Schottky junction field effect transistor (FIG. 7K) manufactured by the above-described conventional Schottky junction field effect transistor manufacturing method has the same configuration as the conventional Schottky junction field effect transistor described above with reference to FIG. Therefore, it functions as a field effect transistor similar to the conventional Schottky field effect transistor described above with reference to FIG.

According to the conventional method for manufacturing a Schottky junction field effect transistor shown in FIG. 7, as is apparent from the above description, a Schottky junction field effect transistor exhibiting the function as the above-described field effect transistor is provided by:
It can be easily manufactured.

In the case of the conventional method of manufacturing a Schottky junction field effect transistor shown in FIG. 7, a step of forming a source region 6 'and a drain region 7' in the semiconductor substrate 1 at both positions with the gate electrode layer 4 interposed therebetween. In a step (FIG. 7I) of activating the source region 6 'and the drain region 7' after (FIG. 7G), the thermal annealing process is performed as follows.
Since the semiconductor substrate 1 is covered with the protective layer 12, the semiconductor substrate 1 is formed in the step of activating the source region 6 'and the drain region 7' (FIG. 7I). The unnecessary elements of the semiconductor material do not scatter unnecessarily.

In the step of forming the metal layer 4 '(FIG. 7C), the metal layer 4' is formed by adding WSiN, WSi, WN, WAl, TiW, TiW.
N, MoSi _x and is formed of a metal material selected from among TaSi, therefore, the gate electrode layer 4 formed in the step of forming a gate electrode layer 4 (Fig. 7 E) is, WSiN, WSi, WN, WA
l, TiW, TiN, made of a metal material selected from among MoSi _x and TaSi. And such a metal material is excellent in heat resistance.

Therefore, in the step of activating the source region 6 'and the drain region 7' (FIG. 7I), the thermal annealing can be performed at the high temperature as described above, and thus the source region 6 'and the drain A sufficiently activated source region 6 and drain region 7 in the region 7 'can be formed.

Further, a step of forming a gate electrode layer 4 (FIG. 7E)
In using an RF plasma etching apparatus 20 described above in FIG. 8, and 'the etching process for the plasma ions of a gas mainly composed of SF ₆ or CF ₄ metal layer 4' metal layer 4 with respect to the upper surface of the Therefore, the gate electrode layer 4 can be formed as having a side surface extending on a surface perpendicular to the upper surface of the semiconductor substrate 1 because the plasma etching process is performed by vertically irradiating the gate electrode layer 4.

Therefore, in the step of forming the protective layer 12 extending over the semiconductor substrate 1 so as to cover the gate electrode layer 4 (FIG. 7H), the protective layer 12 is separated from the semiconductor substrate 1 and the gate electrode layer 4. During the thermal annealing process in the step of activating the source region 6 'and the drain region 7' (FIG. 7I), the semiconductor material constituting the semiconductor material 1 is diffused from the semiconductor substrate 1. It can be easily formed without causing acceptable problems.

Further, plasma ions used in the plasma etching process in the step of forming the gate electrode layer 4 (FIG. 7E) are plasma ions obtained by turning SF ₆ or CF ₄ gas into plasma, and SF ₆ or CF ₄ The gas is
It is easily available and has almost no adverse effect on the semiconductor substrate 1.

From the above, according to the conventional method for manufacturing a Schottky junction field effect transistor shown in FIG. 7, it is relatively easy to manufacture a Schottky junction field effect transistor having relatively good characteristics. it can.

[Problem to be Solved by the Invention] In the conventional method of manufacturing the Schottky junction field effect transistor described above with reference to FIG. 7, the plasma etching in the step of forming the gate electrode 4 (FIG. 7E) is performed by etching the metal layer 4. It is desirable that the etching be completed when the region under the mask layer 11 has just been removed by etching. However, since it is difficult in practice, the plasma etching process is performed so that the region of the metal layer 4 under the mask layer 11 is just removed by etching. It ends at the point when it was done. That is, so-called over-etching is performed.

By the way, in the case of the conventional method of manufacturing the Schottky junction field effect transistor described above with reference to FIG. 7, the plasma ions used in the plasma etching process in the step of forming the gate electrode layer 4 (FIG. 7E) are shown in FIG. The plasma ions are obtained using such a high-frequency plasma etching apparatus 20,
This cannot be obtained unless the inside of the etching chamber 22 is set to a relatively high gas pressure.

Thus, the step of forming the gate electrode layer 4 (the seventh step)
The plasma etching process in FIG. E) is performed in an atmosphere having a relatively high gas pressure. Therefore, during the plasma etching process, the plasma ion density is relatively large, and therefore, the collision between the plasma ions causes the metal layer 4 The plasma ions which irradiate the metal layer 4 'perpendicularly to its upper surface and the plasma ions which irradiate the metal layer 4' obliquely to its upper surface are generated in the plasma ions which irradiate the metal layer 4 '. ing. Further, since the density of the plasma ions is relatively large, the temperature of the semiconductor substrate 1 is increasing.

From the above, in the case of the conventional method of manufacturing a Schottky junction field effect transistor described above with reference to FIG. 7, in the step of forming the gate electrode layer 4 (FIG. 7E), over-etching is actually performed for the reason described above. Since the plasma etching process has been performed until the time when the region under the mask layer 11 of the metal layer 4 is just removed by etching (this is referred to as a first time point), the plasma etching process is performed. Was performed at an over-etching rate of 100%.
Time point beyond the time point (this is generally called the second time point)
If you make up, that the, and time (which T _a from start of the plasma etching process from the first time point with respect to time to the first time point (referred to as T _o) to the second time point ) Is 100% in a%, and when the plasma etching treatment is performed at an overetching rate (%) of (100 + a)% (this is referred to as an overetching rate F (%)), the gate electrode layer 4 is obtained by side-etching with the side etching amount taken from the side edge of the mask layer 11 in proportion to the value of the above-mentioned over-etching rate F (%).

For this reason, in the conventional method of manufacturing the Schottky junction field effect transistor described above with reference to FIG. 7, it was extremely difficult to form the gate electrode layer 4 having a predetermined length.

Therefore, the conventional method for manufacturing a Schottky junction field effect transistor described above with reference to FIG. 7 has a drawback that it is extremely difficult to manufacture a Schottky junction field effect transistor having desired characteristics. Was.

Therefore, the present invention proposes a novel method of manufacturing a Schottky junction field effect transistor that does not have the above-mentioned disadvantages.

[Means for Solving the Problems] The method of manufacturing the Schottky junction field effect transistor according to the present invention is the same as the method of manufacturing the conventional Schottky junction field effect transistor described above with reference to FIG. Providing a semiconductor substrate on which a semiconductor active layer having a desired conductivity type is formed on the upper surface side of the semiconductor substrate or on the semi-insulating semiconductor substrate; and (b) forming the semiconductor substrate on the semiconductor substrate. Forming a metal layer forming a Schottky junction with the active layer; (c) forming a mask layer on the metal layer; and (d) forming the mask layer with respect to the metal layer. A step of forming a gate electrode layer in a region below the mask layer from the metal layer by etching as a mask, and (e) removing the mask layer from the gate electrode layer. By implanting impurity ions that give the same conductivity type as the semiconductor active layer using the gate electrode layer as a mask with respect to the semiconductor substrate, the gate electrode layer is embedded in the semiconductor substrate from the semiconductor active layer side. At both positions,
Forming a source region and a drain region,
Then, in the step of forming the (f) the metal layer to form the metal layer, WSiN, WSi, WN, WAl , TiW, TiN, a metal material selected from among MoSi _x and TaSi, also, (g )
In the step of forming the gate electrode layer, the etching process on the metal layer is performed by forming plasma ions of a gas containing SF ₆ or CF ₄ as a main component with the metal material and forming the mask layer on the upper surface. Plasma etching is performed by irradiating the metal layer perpendicularly to its upper surface.

However, the method of manufacturing a Schottky junction field effect transistor according to the present invention is based on the method of manufacturing a Schottky junction field effect transistor, wherein in the step of forming the (h) gate electrode layer, SF ₆ or CF ₄ is used as a main component. A plasma etching process can be performed by vertically irradiating the metal layer made of the metal material and forming the mask layer on the upper surface with gaseous plasma ions, and the plasma etching process can be performed. If the etching process is performed, the over-etching rate of the metal layer made of the metal material and forming the mask layer on the upper surface (the plasma etching process is performed to remove the metal layer other than the region under the mask layer by etching. If done until then, it was done with 100% overetch rate (%) When the plasma etching process is performed up to a second time point beyond the first time point where the region of the metal layer other than the portion below the mask layer is just removed by etching, the plasma etching process is performed. Of the time from the first time point to the second time point with respect to the time from the start time to the first time point
When the value of the 0 fraction is a%, it is defined that the etching was performed at an overetching rate of (100 + a)%), and the side etching amount from the side edge of the mask layer in the region below the mask layer. Using an electron cyclotron resonance plasma etching apparatus whose etching characteristics are obtained by exhibiting saturation characteristics, the etching process for the metal layer is defined as the plasma etching process, and the plasma etching process is performed at an over-etching rate at the saturation point of the etching characteristics. The etching is performed at the above over-etching rate.

Preparation of Schottky junction type field effect transistor according to [Operation and Effect] The present invention, in the manufacturing method of the conventional Schottky junction field-effect transistor described above in FIG. 7, in the step of forming the gate electrode layer, SF ₆ or CF ₄ Plasma etching apparatus capable of performing a plasma etching process by vertically irradiating plasma ions of a gas whose main component is a metal material to a top surface of a metal layer having a mask layer formed on a top surface thereof , And the etching process for the metal layer made of a metal material is replaced with the plasma etching process just described.
A plasma etching process is performed by vertically irradiating plasma ions of a gas containing ₆ or CF ₄ as a main component to the metal layer made of the above metal material and forming the above mask layer on the upper surface thereof. If such a plasma etching process is performed, the overetching rate of the metal layer made of the metal material and forming the mask layer on the upper surface (the plasma etching process is performed by the mask of the metal layer) If this was done until the area other than below the layer was just etched away,
The plasma etching process is defined as being performed at an over-etching rate (%) of 0%, and the first region where the region of the metal layer other than under the mask layer is just removed by etching.
Is performed from the time point of the plasma etching process to the second time point, the time is compared with the time from the start time point of the plasma etching process to the first time point with respect to the time from the first time point to the second time point. When the percentage value is a%,
Electrons obtained by exhibiting saturation characteristics in terms of the etching characteristics in terms of the side etching amount taken from the side edge of the mask layer in the region below the mask layer with respect to (100 + a)% overetching rate). Using a cyclotron resonance plasma etching apparatus, the etching process on the metal layer is defined as the plasma etching process, and the plasma etching process is performed at an over etching rate equal to or higher than the over etching rate at the saturation point of the etching characteristic. Except for this, it is the same as the case of the conventional method of manufacturing the Schottky junction field effect transistor described above with reference to FIG.

For this reason, as in the case of the method of manufacturing the conventional Schottky field effect transistor described above with reference to FIG. 7, it exhibits the same function as the field effect transistor similar to the conventional Schottky field effect transistor described above with reference to FIG. A Schottky junction field effect transistor can be easily manufactured.

According to the method of manufacturing a Schottky junction field effect transistor according to the present invention, the metal layer is formed in the step of forming the metal layer in the same manner as in the method of manufacturing the conventional Schottky junction field effect transistor described above with reference to FIG. , WS
iN, WSi, WN, WAl, TiW, TiN, and a metal material selected from among MoSi _x and TaSi, therefore, the gate electrode layer formed in the step of forming a gate electrode layer is, WSiN, WS
i, WN, WAl, TiW, TiN, made of a metal material selected from among MoSi _x and TaSi. And such a metal material is excellent in heat resistance.

Therefore, after the step of forming the source region and the drain region, the step of forming a protective layer extending over the gate electrode layer on the semiconductor substrate body, and after the step, the source region and the drain are subjected to thermal annealing treatment. When the step of activating the region is performed, the step of activating the source region and the drain region is performed in the step of activating the source region and the drain region for the reason described in the case of the method of manufacturing the conventional Schottky junction field effect transistor described above with reference to FIG. The region can be sufficiently activated, and the plasma etching in the step of forming the gate electrode layer is performed by the same method as the method of manufacturing the conventional Schottky junction field effect transistor described above with reference to FIG. Since the plasma etching process is performed by irradiating the upper surface of the mask layer vertically, The gate electrode layer is formed so that its side surface extends perpendicular to the upper surface of the semiconductor substrate body, so that the Schottky junction field-effect transistor having relatively good characteristics can be relatively easily manufactured. can do.

However, in the case of the method of manufacturing a Schottky junction field effect transistor according to the present invention, in the step of forming a gate electrode layer, plasma ions of a gas containing SF ₆ or CF ₄ as a main component are made of the metal material and the mask is formed on the upper surface. The metal layer forming the layer can be subjected to a plasma etching process by irradiating the upper surface thereof perpendicularly, and if such a plasma etching process is performed, the metal layer is made of a metal material and the mask layer is formed on the upper surface. Over-etching rate of the metal layer forming the above (if the plasma etching treatment was performed until the area of the metal layer other than under the mask layer was just removed by etching, this was determined to be 100% over-etching rate. (%), And the plasma etching treatment is performed except for the metal layer under the mask layer. If the process is performed from the first point in time when the region is just etched away to the second point in time, this is done from the first point in time with respect to the time from the start of the plasma etching process to the first point in time. When the value of 100% of the time up to the second time point is a%, it is defined that the etching was performed at an overetching rate of (100 + a)%. Using an electron cyclotron resonance plasma etching apparatus in which the etching characteristics in terms of the side etching amount show saturation characteristics, the etching process on the metal layer is the plasma etching process, and the plasma etching process is the etching characteristics. At an over-etching rate equal to or higher than the over-etching rate at the saturation point.

For this reason, according to the method for manufacturing a Schottky junction field effect transistor according to the present invention, even if the gate electrode layer is obtained by being side-etched as viewed from the side edge of the mask layer,
As long as the plasma etching process is performed at the above-described over-etching rate, the side etching amount can be obtained at a substantially constant value regardless of the value.

Therefore, according to the method for manufacturing a Schottky junction field effect transistor according to the present invention, the gate electrode layer can be easily formed as having a predetermined length, and
A Schottky junction type field effect transistor can be easily manufactured with desired characteristics.

Embodiment 1 Next, referring to FIG. 1, an embodiment of a method for manufacturing a Schottky junction field effect transistor according to the present invention will be described with reference to FIG. Let's talk about the manufacturing method of the effect transistor.

1, parts corresponding to those in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the embodiment of the method for manufacturing a Schottky junction field effect transistor according to the present invention shown in FIG. 1, the following sequential steps are taken, and the same Schottky junction field effect transistor as the Schottky junction field effect transistor described above with reference to FIG. Fabricate effect transistors.

That is, a semi-insulating semiconductor substrate 2 similar to that of FIG. 7A is prepared in advance (FIG. 1A).

Then, a semiconductor active layer 3 similar to that of FIG. 7B is formed in the semi-insulating semiconductor substrate 2, and thus a semiconductor substrate 1 similar to that of FIG. 7B is obtained (FIG. 1). B).

Next, on the semiconductor substrate 1, a metal layer 4 'made of the same metal material as in the case of FIG. 7C is formed.
Figure C).

Next, a mask layer 11 similar to that of FIG. 7C is formed on the metal layer 4 '(FIG. 1D).

Next, as in the case of FIG. 7D, the gate electrode layer 4 is formed in a region of the metal layer 4 'under the mask layer 11 by an etching process using the mask layer 11 as a mask. 1 FIG. E).

However, in this case, an electron cyclotron resonance plasma etching apparatus is used.

This electron cyclotron resonance plasma etching apparatus is indicated by 40 in FIG. 2 and is apparently publicly known. Therefore, although not described in detail, a plasma ion generation chamber 42 is formed, and the plasma ion generation chamber is formed. A gas introduction tube 43 for introducing a gas containing SF ₆ or CF ₄ as a main component, and a microwave introduction tube 45 for introducing a microwave into a plasma ion generation chamber 42 through a window 44. And a container 41 that derives.

Further, the electron cyclotron resonance plasma etching apparatus 40 has an electromagnetic coil 46 arranged around the container 41.

Further, the electron cyclotron resonance plasma etching apparatus 40 includes a sample mounting table 53 that communicates with the plasma ion generation chamber 42 through the window 51 and has a flat sample mounting surface 53a. A chamber 50 is formed from which a chamber 52 is formed and an exhaust pipe 54 for exhausting the interior of the etching chamber 52 together with the chamber 42 for plasma ion generation.

However, the electron cyclotron resonance plasma etching apparatus applies plasma ions of a gas containing SF ₆ or CF ₄ as a main component to a metal layer 4 ′ made of the above-described metal material and having a mask layer 11 formed on the upper surface. The plasma etching process can be performed by vertically irradiating the metal layer, and if such a plasma etching process is performed, the overetching rate of the metal layer 4 'made of the above-mentioned metal material and forming the mask layer 11 on the upper surface can be improved. (If the plasma etching process was performed until the region of the metal layer other than the region under the mask layer was just removed by etching, this was defined as performed at an over-etching rate (%) of 100%. The etching process is performed for a second time beyond the first point in time where the region of the metal layer other than under the mask layer is just etched away. If the process is performed up to the time point, the value of the percentage of the time from the first time point to the second time point with respect to the time from the start time of the plasma etching process to the first time point is a% Is defined as being performed at an over-etching rate of (100 + a)%, the mask layer 11 in a region below the mask layer 11
Using an electron cyclotron resonance plasma etching apparatus obtained by exhibiting a saturation characteristic using gas pressure as a parameter as shown in FIG. 3 and FIG. The etching process for the metal layer 4 'is the plasma etching process, and the plasma etching process is performed at an over-etching rate equal to or higher than the over-etching rate at the saturation point of the etching characteristics.

Next, the mask layer 11 is removed from above the gate electrode layer 4 as in the case of FIG. 7F (FIG. 1F).

Next, the same source region 6 'and drain region 7' as in the case of FIG. 7G are formed in the semiconductor substrate 1 by implanting impurity ions into the semiconductor substrate 1 as in the case of FIG. 7G. Is similarly formed (FIG. 1G).

Next, the same protective layer 12 as in FIG. 7H is formed on the semiconductor substrate 1 (FIG. 1H).

Next, as in the case of FIG. 7I, the source region 6 'and the drain region 7' are activated to obtain the similarly activated source region 6 and drain region 7 (FIG. 1I).

Next, from above the semiconductor substrate 1, the protective layer 12 was
(FIG. 7J).

Next, on the source region 6 and the drain region 7, the same source electrode layer 8 and drain electrode layer 9 as in the case of FIG.
To obtain a Schottky junction field effect transistor similar to the Schottky junction field effect transistor described above with reference to FIG. 7 (FIG. 1K).

The above is the embodiment of the method for manufacturing the Schottky junction field effect transistor according to the present invention.

According to the method of manufacturing the Schottky junction field effect transistor according to the present invention, in the step of forming the gate electrode layer 4, the high frequency plasma etching apparatus 20 is used to simply perform an etching process on the metal layer 4 'by plasma etching. Instead of the method of manufacturing the conventional Schottky junction field effect transistor described above with reference to FIG.
7, except that the plasma etching process is performed at the above-described over-etching rate, which is the same as the method of manufacturing the conventional Schottky junction field effect transistor described above with reference to FIG. Although omitted, a Schottky junction field effect transistor exhibiting a function as a field effect transistor can be easily manufactured in the same manner as in the conventional method of manufacturing a Schottky junction field effect transistor described above with reference to FIG. .

7, the source region 6 'and the drain region 7' are provided at both positions with the gate electrode layer 4 interposed therebetween in the same manner as in the conventional method of manufacturing a Schottky junction field effect transistor described above with reference to FIG. (FIG. 1G)
Thereafter, in a step of activating the source region 6 'and the drain region 7' (FIG. 1I), the thermal annealing is performed in a state where the semiconductor substrate 1 is covered with the protective layer 12. Therefore, in the step of activating the source region 6 ′ and the drain region 7 ′ (FIG. 1I), the elements of the semiconductor material constituting the semiconductor substrate 1 are not unnecessarily scattered to the outside. . Further, 'in the step (FIG. 1 C) to form a, the metal layer 4' metal layer 4, WSiN, WSi, WN, WAl , TiW, TiN, MoSi x and TaS
i, the gate electrode layer 4 formed in the step of forming the gate electrode layer 4 (FIG. 1E) is made of WSiN, WSi, WN, WAl, TiW, TiN, Mo
Made of a metal material selected from among Si _x and TaSi. And
Such a metal material has excellent heat resistance.

Therefore, in the step of activating the source region 6 'and the drain region 7' (FIG. 1I), the thermal annealing can be performed at a high temperature, and the source region 6 'and the drain region 7' can be sufficiently formed. Can be activated.

Further, a step of forming a gate electrode layer 4 (FIG. 1E)
In the etching process for the metal layer 4 ', SF ₆
Alternatively, the plasma etching process is performed by vertically irradiating plasma ions of a gas containing CF ₄ as a main component to the upper surface of the metal layer 4 ′.
Are formed as those whose side surfaces extend on a plane perpendicular to the upper surface of the semiconductor substrate body 1.

For this reason, in the step of forming the protective layer 12 extending over the gate electrode layer 4 on the semiconductor substrate 1 (FIG. 1H), the protective layer 12 is During the thermal annealing process in the step of activating the source region 6 ′ and the drain region 7 ′ (FIG. 1I), the elements of the semiconductor material forming the semiconductor substrate 1 are diffused from the semiconductor substrate 1. Can be formed without causing the problem of allowing

Further, plasma ions used in the plasma etching process in the step of forming the gate electrode layer 4 (FIG. 1E) are plasma ions obtained by turning SF ₆ or CF ₄ gas into plasma, and SF ₆ or CF ₄ The gas is
It is easily available and has almost no adverse effect on the semiconductor substrate 1.

From the above, the method of manufacturing the Schottky junction field effect transistor according to the present invention shown in FIG. 1 is the same as the method of manufacturing the conventional Schottky junction field effect transistor described above with reference to FIG. As a field-effect transistor having relatively good characteristics,
It can be manufactured relatively easily.

However, in the case of the method of manufacturing the Schottky junction field effect transistor according to the present invention shown in FIG. 1, in the step of forming the gate electrode layer, plasma ions of a gas containing SF ₆ or CF ₄ as a main component are made of the above metal material. In addition, the metal layer 4 ′ having the mask layer 11 formed on the upper surface can be subjected to plasma etching by irradiating the metal layer 4 ′ vertically to the upper surface. Over-etching rate of the metal layer 4 'forming the mask layer 11 on the upper surface (when the plasma etching treatment is performed until the region of the metal layer other than under the mask layer is just removed by etching, This is defined as being performed at an over-etching rate (%) of 100%, and the plasma etching process is performed on the metal layer. If the region other than the region under the mask layer has been removed from the first point in time just after being etched away to the second point in time, this is compared with the time from the start of the plasma etching process to the first point in time. When the value of 100% of the time from the first time point to the second time point is a%, it is defined that the etching was performed at an overetching rate of (100 + a)%). Using an electron cyclotron resonance plasma etching apparatus obtained by exhibiting a saturation characteristic in an etching characteristic in terms of a side etching amount taken from a side edge of the layer 11, an etching process on the metal layer 4 'is defined as the plasma etching process. The plasma etching process is performed at an over-etching rate equal to or higher than the over-etching rate at the saturation point of the etching characteristics.

Therefore, according to the method of manufacturing the Schottky junction field effect transistor according to the present invention shown in FIG. 1, even if the gate electrode layer 4 is obtained by side-etching as viewed from the side edge of the However, as long as the plasma etching process is performed at the above-described over-etching rate, a predetermined substantially constant value can be obtained regardless of the value.

Therefore, according to the method of manufacturing the Schottky junction field effect transistor according to the present invention shown in FIG.
Can be easily formed as having a predetermined length, and therefore, a Schottky junction field effect transistor can be easily manufactured having desired characteristics.

Embodiment 2 Next, another embodiment of a Schottky junction field effect transistor according to the present invention will be described with reference to FIG.

In FIG. 5, portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The embodiment of the method for manufacturing a Schottky junction field effect transistor according to the present invention shown in FIG. 5 employs the following sequential steps to obtain the same Schottky junction field effect transistor as the Schottky junction field effect transistor described above with reference to FIG. Fabricate effect transistors.

That is, the same semi-insulating semiconductor substrate 2 as in the case of FIG. 1A is prepared in advance (FIG. 5A).

Then, a semiconductor active layer 3 similar to the case of FIG. 1B is formed in the semi-insulating semiconductor substrate 2, thereby obtaining a semiconductor substrate 1 similar to the case of FIG. 1B (FIG. 5). B).

Next, on the semiconductor substrate 1, a metal layer 4 'made of the same metal material as in the case of FIG.
Figure C).

Next, a mask material layer 13 'made of, for example, SiO ₂ different from the metal material is formed on the metal layer 4' (FIG. 5D).

Next, a mask layer 11 similar to that of FIG. 1C is formed on the mask material layer 13 '(FIG. 5E).

Next, by performing an etching process on the mask material layer 13 ′ using the mask layer 11 as a mask, the mask layer 13 is formed by a region of the mask material layer 13 below the mask layer 11.
A mask body 14 is formed by the mask layers 13 and 11 (FIG. 5F).

Next, in accordance with the case of FIG. 1D, the metal layer 4 'is formed by an etching process on the metal layer 4' using the mask body 14 as a mask. (FIG. 5G).

Next, the mask layer 11 of the mask body 14 is removed from above the mask layer 13 (FIG. 5H).

Next, the semiconductor substrate 1 is implanted with impurity ions according to the case of FIG. 1G using a stacked body of the metal layer 4 ″ and the mask body 13 as a mask, so that the semiconductor substrate 1 1 A source region 6 'and a drain region 7' similar to those in FIG. G are formed (FIG. 5I).

Next, the metal layer 4 ″ and the mask 13 are formed on the semiconductor substrate 1.
And a protective layer 15 made of the same metal material as that of the metal layer 4 ″ is formed so as to extend over the laminate (FIG. 5J).

Next, the source region 6 'and the drain region 7' are activated according to the case of FIG. 1 to obtain the activated source region 6 and drain region 7 (FIG. 5K).

Next, the protective layer 15 is removed from the semiconductor substrate 1 by a method similar to the case of forming the gate electrode layer 4 in [Example 1] described above with reference to FIG. 1 (FIG. 5L).

Next, on the source region 6 and the drain region 7, the same source electrode layer 8 and drain electrode layer 9 as in the case of FIG.
To obtain a Schottky junction field effect transistor similar to the Schottky junction field effect transistor described above with reference to FIG. 1 (FIG. 5M).

The above is the embodiment of the method for manufacturing the Schottky junction field effect transistor according to the present invention.

According to the method of manufacturing the Schottky junction field effect transistor according to the present invention described above, the same operation and effect as in the case of [Example 1] can be obtained, although detailed description is omitted.

[Brief description of the drawings]

1A to 1K are schematic cross-sectional views in sequential steps showing an embodiment of a method for manufacturing a Schottky junction field effect transistor according to the present invention. FIG. 2 is a schematic sectional view showing an embodiment of an electron cyclotron resonance plasma etching apparatus which can be used for the method of manufacturing a Schottky junction field effect transistor according to the present invention. FIG. 3 is a diagram showing the relationship between the gas pressure and the etching rate of the metal layer in the electron cyclotron resonance plasma etching apparatus for explaining the method for manufacturing the Schottky junction field effect transistor according to the present invention. FIG. 4 is a diagram illustrating the relationship between the over-etching rate and the side etching amount, with the gas pressure in the etching apparatus as a parameter, for explaining the method of manufacturing the Schottky junction field effect transistor according to the present invention. 5A to 5M are schematic cross-sectional views in a sequential step showing another embodiment of the method for manufacturing a Schottky junction field effect transistor according to the present invention. FIG. 6 is a schematic cross-sectional view showing a Schottky junction field effect transistor manufactured by the method of manufacturing a Schottky junction field effect transistor according to the present invention and the conventional method of manufacturing a Schottky junction field effect transistor. 7A to 7K are schematic cross-sectional views in sequential steps showing a method for manufacturing a conventional Schottky junction field effect transistor. FIG. 8 is a schematic diagram showing a high-frequency plasma etching apparatus used for a conventional Schottky junction field effect transistor. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Semi-insulating semiconductor substrate 3 ... Semiconductor active layer 4 ... Gate electrode layer 4 ', 4 "... Metal layer 5 ... Schottky junction 6, 6' ... Source region 7, 7 ': Drain region 8: Source electrode layer 9: Drain electrode layer 11: Mask layer 12: Protective layer 13, 13': Mask layer 14: Mask body 15: Protective layer 20: High frequency Plasma etching apparatus 21 Container 22 Etching chamber 23 Gas introduction tube 24 Exhaust tube 25 Sample holder 26 Electrode 27 High frequency source 40 Electron cyclotron resonance plasma Etching equipment 41… Container 42… Plasma ion generation chamber 43… Gas introduction tube 44… Window 45… Microwave introduction tube 46… Electromagnetic coil 50… Container 51… Window 52… Etching Chamber 53 ... Sample table 54 ... Exhaust tube

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/775-29/778 H01L 21/337-21/338 H01L 29/812

Claims (1)

(57) [Claims] A step of preparing a semiconductor substrate on which a semiconductor active layer having a desired conductivity type is formed on an upper surface side of the semi-insulating semiconductor substrate or on the semi-insulating semiconductor substrate; Forming a metal layer forming a Schottky junction with the semiconductor active layer; forming a mask layer on the metal layer; masking the mask layer with respect to the metal layer A step of forming a gate electrode layer by a region under the mask layer from the metal layer by removing the mask layer, and removing the mask layer from above the gate electrode layer. By implanting impurity ions giving the same conductivity type as that of the semiconductor active layer using the gate electrode layer as a mask, the gate electrode is introduced into the semiconductor substrate from the semiconductor active layer side. Forming a source region and a drain region at both positions sandwiching the pole layer; and forming the metal layer in the step of forming the metal layer.
iN, WSi, WN, WAl, TiW, TiN, and a metal material selected from among MoSi _x and TaSi, in the step of forming the gate electrode layer, a gas mainly composed of SF ₆ or CF ₄ plasma A plasma etching process can be performed by vertically irradiating the metal layer made of the metal material and forming the mask layer on the upper surface thereof to the upper surface, and such a plasma etching process can be performed. If it is performed, the overetching rate of the metal layer made of the metal material and forming the mask layer on the upper surface (the plasma etching process is performed until the region of the metal layer other than under the mask layer is just removed by etching). If you do that, 100%
And the plasma etching process was performed until the second time point beyond the first time point where the region of the metal layer other than under the mask layer was just etched away. In that case, when the value of 100% of the time from the first time to the second time with respect to the time from the start of the plasma etching process to the first time is a%, (100+
a) defined as performed at% overetching rate)
Using an electron cyclotron resonance plasma etching apparatus in which the etching characteristics in terms of the side etching amount taken from the side edge of the mask layer in the region below the mask layer exhibit saturation characteristics, the etching process for the metal layer is performed. The above plasma etching process,
A method for producing a Schottky junction field effect transistor, characterized in that the plasma etching process is performed at an over-etching rate equal to or higher than the over-etching rate at the saturation point of the etching characteristics.