JPH04288837A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the generation of power source over current induced by a faulty chip when a common power source is used in aging under a wafer state or a chip wall surface short circuit induced by a common wiring after the end of dicing. CONSTITUTION:A fuse 5 is formed in each chip where the fuse 5 is mounted between a power source terminal 6 of each chip 4 and a common wiring. The fuse 5 is so designed that it may selectively be blown.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method for aging a wafer.

0002

[Prior Art] FIG. 2 shows, for example, Japanese Patent Application Laid-Open No. 63-204621
This figure shows a conventional wafer chip layout that can be aged in a wafer state as shown in the publication, and in the figure, 1 is a wafer, 2 is a common pad for power supply, 3 is a common power supply wiring, and 4 is a chip.

Next, the operation will be explained. The common power supply wiring 3 is used to share the same functional terminals of each chip 4, such as a power supply terminal and a ground terminal, and these are connected to the common pad 2 for power supply. Aging of the chip 4 is performed to detect initial failures, and aging is generally performed at a high temperature of about 125° C. for several hours with the external power supply between the common power supply pads 2 set to the maximum operating voltage. After that, a wafer test is performed and non-defective products are sent to the subsequent process. Also, the common power supply wiring 3 is cut when dicing the wafer 1.
Each player had 4 chips.

0004

[Problem to be Solved by the Invention] Since the conventional semiconductor integrated circuit device is configured as described above, there is a problem in that during dicing, the common power supply wiring is short-circuited at the gap on the chip side, resulting in a short-circuit between the power supply and the ground. If there is a failure mode in which there is a short circuit between the power supply and the ground on even one chip among all the chips, there are problems such as excessive power supply current flowing between the common power supply pads and the risk of destroying the power supply. Ta.

[0005] This invention was made to solve the above-mentioned problems, and there is no problem even if a short circuit occurs on the chip side surface during dicing, and even if there is a defective chip, there is no problem An object of the present invention is to obtain a semiconductor integrated circuit device in which an excessive current does not flow in a power supply current.

[0006]

SUMMARY OF THE INVENTION A semiconductor integrated circuit device according to the present invention has a fuse inserted between the power supply wiring of each chip and a common power supply wiring, and the fuse is formed within each chip.

[0007]

[Operation] The fuse according to the present invention makes it possible to disconnect a defective chip from the power supply and to disconnect the power supply wiring of each chip and the common power supply wiring within the chip before dicing.

[0008]

[Example] Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1, 2, and 34 are the same as 1, 2, 3, and 4 shown in the conventional example of FIG. 2, so the explanation will be omitted. 5 is a fuse, and 6 is a power supply terminal for each chip 4.

[0009] The common power supply wiring 3 is connected to the common pad 2 for power supply.
and each fuse 5 in each chip 4, each fuse 5
The other terminals are connected to the power supply terminal 6 of each chip 4. Further, each fuse 5 is formed inside each chip 4.

Each fuse 5 can be easily made of, for example, a thin metal film, and has been put to practical use in bipolar field programmable ROMs and the like.

Next, the operation will be explained. A wafer test is performed on the wafer 1, and for defective wafers 1, an auxiliary circuit or the like is provided on the chip 4 so that the fuse 5 can be cut, or the power supply terminal 6 of the defective chip 4 is connected to the power supply terminal 6. The common supply pads 2 can be insulated.

Next, a voltage is applied to the power supply common pad 2 of the wafer 1 after the wafer test, and the wafer 1 is placed in a high temperature furnace for aging. All the fuses 5 of the wafer 1 that has been aged are cut by using a large current or laser irradiation. Thereby, the power supply terminal 6 of each chip 4 and the common power supply wiring 3 can be insulated.

Since the fuse 5 is formed in each chip 4, only the common power supply wiring 3 is short-circuited on the wall surface of the chip side during dicing, and no defective chips 4 are generated due to a short-circuit on the wall surface of the chip side.

[0014]

As described above, according to the present invention, by providing a fuse, it is possible to reduce the burden on the aging power supply for defective chips.

[0015] Also, there is an effect of eliminating the problem of short-circuiting of the common power supply wiring on the wall surface of the chip side during dicing, resulting in a short-circuit between the power supply and the ground.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing a wafer chip layout of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a wafer chip layout of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

1 Wafer 2 Common pad for power supply 3 Common power supply wiring 4 Chip 5 Fuse 6 Power terminal

Claims (1)

[Claims] 1. A semiconductor integrated circuit characterized in that a power supply wiring of each chip that is finally divided into individual chips and a common power supply wiring of each of the chips are connected by a fuse provided on each of the chips. Device.