JPH04287975A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To apply an LDD structure to a transistor having a vertical structure by ion implanting second conductivity type impurity to a main surface of a semiconductor substrate by a low dose and high implantation energy, and then ion implanting second conductivity type impurity by a high dose and low implantation energy. CONSTITUTION:Phosphorus of second conductivity type impurity of low dose is ion implanted on a first conductivity type semiconductor substrate 11 by high energy, and then first second conductivity type impurity 19a to become first second conductivity type impurity 19 is formed. Then, arsenic of second conductivity type impurity of high dose is ion implanted by low energy, and then a second conductivity type impurity 17a to become a drain region 17 is formed. Thus, the ion implantation of the impurity by the low dose and high implantation energy and the ion implantation of the impurity by the high dose and low implantation energy are combined thereby to easily realize an LDD structure for a vertical structure transistor.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a vertical transistor including an LDD structure.

0002

2. Description of the Related Art One of the problems that arises with the miniaturization of MOS devices in semiconductor devices is the so-called hot carrier effect.
This phenomenon is known as a phenomenon in which high-energy electrons (or holes) are injected into the gate oxide film due to the high electric field generated by reducing the channel length. When these high energy carriers, that is, hot carriers, are injected into the gate oxide film, new interface states are formed, increasing the threshold voltage, decreasing the current driving force, and sub-levels.
This leads to deterioration of device characteristics such as an increase in the threshold coefficient, and thus injection of hot carriers into the gate oxide film becomes an important factor in determining the life of the MOS transistor.

Conventionally, in order to improve the deterioration of device characteristics caused by hot carrier injection, so-called LDD (Lightly Doped Drain) has been conventionally used in such short channel transistors.
) structure has been widely adopted. This LDD structure has a low concentration impurity layer between the channel and the high concentration impurity layer of the drain region, but due to the presence of this low concentration impurity layer, the bias to the drain region can be applied over a wide range. The electric field in the vicinity of the drain region is relaxed, and as a result, the hot carrier effect is suppressed.

Next, the procedure for forming this type of LDD structure according to a conventional example is shown in FIGS. 2(a) to 2(e). In the configuration of the conventional device shown in FIG. 2, reference numeral 1 indicates a p-type semiconductor substrate made of silicon single crystal or the like, 2 indicates a field oxide film for isolation between elements, and 3 indicates a gate oxide film 4 on the semiconductor substrate 1. gate electrode selectively formed through the gate electrode, 5
, and 6 are n+ type source regions selectively formed on the main surface of the substrate corresponding to both sides of the gate electrode 4, respectively.
and the drain region. In addition, 7 is a gate oxide film 4
8 indicates a channel formed directly under the channel 7 through which current flows, and 8 indicates a low concentration impurity layer formed between the channel 7 and the source region 5 and drain region 6, respectively. Layer 9 is a spacer selectively deposited on both side wall edges of the gate electrode 4. In addition,
In the case of this conventional example, a p-type substrate with an impurity concentration of about 1×1015 [cm-3] is used as the semiconductor substrate 1,
The source region 5 and the drain region 6 are each of n+ type with an impurity concentration of about 1×1020 [cm-3], and the low concentration impurity layer 8 has an impurity concentration of about 1×1016 [cm-3]. The length L of the channel 7 directly under the gate oxide film 4 is approximately 0.8 μm, and the thickness tOX of the gate oxide film 4 is approximately 0. .0
The height h of the gate electrode 3 is approximately 0.03 μm, and the spacer 9
The width d is approximately 0.02 μm.

[0005] In this conventional LDD structure, first, an ordinary M
After forming a field oxide film 2, a gate oxide film 4, and a gate electrode 3 by the OS process (FIG. 2(a)), using the gate electrode 3 as a mask, a dose of 1013 [cm-2 ] is selectively implanted with an energy of about 50 keV to form an n-type impurity layer 8a which will later become the n-type impurity layer 8 (FIG. 2(b)). Next, an oxide film 9 is formed on the entire surface by vapor phase growth.
By depositing the oxide film 9a (FIG. 3(c)) and selectively removing the oxide film 9a by reactive ion etching, a spacer made of the oxide film 9a is formed on both side wall ends of the gate electrode 3. 9 is left ((d) in the same figure)
), then, using these gate electrodes 3 and each spacer 9 as a mask, the channel 7 and source region 5 are formed by selectively implanting As (arsenic) at a high concentration for normal source/drain formation. , and a drain region 6, and a p-type impurity layer 8 is formed between each of these regions 5 and 6 (see (e) in the same figure).
)).

[0006]

[Problem to be Solved by the Invention] Nowadays, as semiconductor devices become more and more highly integrated, it is becoming more and more common to use horizontal type It is being considered to employ a vertically structured transistor having a channel in a direction perpendicular to a semiconductor substrate, as will be described later, for dynamic memory cells and the like. For transistors with such a vertical structure, improvements in current driving ability,
In order to increase the speed of operation, efforts are being made to shorten the channel length, and in this case as well, deterioration of device characteristics due to injection of hot carriers becomes a problem, as described above.

[0007] As mentioned above, the LDD structure is
Although it is an effective solution to suppress carrier injection and improve device reliability, the conventional LD described above
In the method for forming the D structure, a low concentration impurity layer is formed by ion implantation using an oxide film spacer as a mask. On the other hand, the LD
There is a problem in that the method cannot be applied to form the D structure.

[0008] The present invention was made in order to solve the problems of the conventional art, and its purpose is to provide this invention which makes it possible to apply an LDD structure to a vertically structured transistor. It is an object of the present invention to provide a method for manufacturing a semiconductor device, in particular a method for forming an LDD structure in a vertically structured transistor.

[0009]

[Means for Solving the Problems] In order to achieve the above-mentioned object, a method for manufacturing a semiconductor device according to the present invention includes a method for manufacturing a semiconductor device in which a trench is dug in a direction perpendicular to a semiconductor substrate of a first conductivity type. It has a channel on the wall surface, and a source region made of a second conductivity type high concentration impurity layer on the inside side of the substrate of the channel,
Drain regions each formed of a second conductivity type high concentration impurity layer are formed on the main surface side of the substrate through a second conductivity type low concentration impurity layer for the LDD structure, and a gate oxide film is formed on the channel. A method for manufacturing a vertical structure transistor including an LDD structure in which a gate electrode is formed, wherein first, a second conductive type is implanted on the main surface of the first conductive type semiconductor substrate by a low dose and high implantation energy. A first step of ion-implanting an impurity to form a first second conductivity type impurity layer, followed by a second step of forming a first second conductivity type impurity layer with a high dose and low implantation energy, overlapping the first second conductivity type impurity layer. a second step of ion-implanting a second conductivity type impurity to form a second second conductivity type impurity layer; A conductivity type low concentration impurity layer is formed, a drain region of the second conductivity type high concentration impurity layer is formed by the latter second conductivity type impurity layer, and after the third step, other configurations are performed. It is characterized in that each part of the element is formed sequentially.

0010

[Operation] Therefore, in the method for forming an LDD structure according to the present invention, a second implant is performed on the main surface of the semiconductor substrate of the first conductivity type by a low dose and high implant energy in the first step.
A conductivity type impurity is ion-implanted to form a first second conductivity type impurity layer, and subsequently, in a second step, a first conductivity type impurity layer is formed.
The second conductivity type impurity layer is superimposed on the second conductivity type impurity layer by ion-implanting the second conductivity type impurity at a high dose and low implantation energy to form a second second conductivity type impurity layer.
The ion implantation of the second conductivity type impurity in the first step is performed with high energy, so the range of the ions is large, and the impurity ions are more concentrated than the second conductivity type impurity ion implantation in the second step. Although it penetrates deeply, the impurity concentration is lowered due to the small dose, resulting in the desired L.
A low concentration impurity layer of the second conductivity type for the DD structure is formed, and on the other hand, the ion implantation of the second conductivity type impurity in the second step is performed at low energy to increase the range of the ions. Because it is small, it only enters shallowly, but because the dose is large, the impurities are raised high and the second stage is not as expected.
A drain region is formed of a conductive type high concentration impurity layer.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to FIG. 1A to 1E show a method for manufacturing a semiconductor device to which an embodiment of the present invention is applied, in which main steps of a method for manufacturing a vertical structure transistor including an LDD structure are sequentially schematically shown. Each is a sectional view.

That is, in the configuration of the embodiment shown in FIG. 1, reference numeral 11 denotes a p-type semiconductor substrate made of silicon single crystal, etc., and 12 denotes both lower inner wall surfaces of a trench dug in a direction perpendicular to the substrate 11. 13 is a polysilicon buried layer buried between the oxide films 12, and 14 is a polysilicon buried layer formed selectively through a gate oxide film 15 formed on both inner wall surfaces of the upper side of the trench. The gate electrodes 16 and 17 are n+ type source regions and drain regions, respectively, which are selectively formed on the main surface of the substrate corresponding to both sides of the gate electrode 14 . Further, 18 is a channel formed directly under the gate oxide film 4 through which a current flows; 19 is a low concentration impurity layer selectively formed between the channel 18 and the source region 16 and the drain region 17; Here, it is an n-type impurity layer. Note that 20 is a p- layer for isolation between elements, which is selectively formed on the main surface of the substrate corresponding to the bottom of the trench.

In the vertical structure transistor including the LDD structure according to the method of this embodiment, first, on a p-type (in this case, the first conductivity type) semiconductor substrate 11,
P (phosphorus) as an n-type (similarly, in this case, second conductivity type) impurity with a dose of about 5 x 1013 [cm-2]
by ion implantation at an energy of about 180 [keV],
N-type impurity layer 19 that will later become each n-type impurity layer 19
form a. That is, in this first step, P 2 ions are implanted at a low dose and at high implantation energy, that is, ions of the second conductivity type are implanted (FIG. 1(a)). Next, the dose was 5×1015 [cm-2]
Similarly, n-type impurity As (arsenic) is ion-implanted at an energy of about 180 [keV] to form an n+-type impurity layer 17a that will later become the drain region 17. In other words, in this second step, the above-mentioned As ions of the same conductivity type, that is, ions of the second conductivity type, are implanted over the n-type impurity layer 19a at a high dose and low implantation energy (FIG. 1(b)).

That is, in each of these steps, the former P ion implantation is carried out with high energy, so the range of the ions is large, and the P 2 impurity ions penetrate deeper than the latter As ion implantation. , because the dose is small, the impurity concentration is lowered and the desired n
- type impurity layer 19a is formed.On the other hand, the latter type of As ion implantation is performed at low energy and the range of the ions is small, so the ion implantation is only shallow, but because the dose is large, the impurity layer 19a is formed. is raised and the expected n+
A type impurity layer 17a is formed.

Therefore, in this case, as will be described later, the n+ type impurity layer 17a formed by the latter ion implantation
will eventually become the drain region 17 of the vertically structured transistor, and the region where impurities can reach only by ion implantation of the former is likewise the n- type impurity layer between the channel 18 and the n+ type drain region 17. It will be 19.

[0016] Next, on the p-type semiconductor substrate 11 on which the layers 19a and 17a were sequentially formed, a patterned resist (not shown) was left by photolithography in areas other than the areas where the vertical transistors were to be formed. After that, use the remaining resist pattern as a mask,
The substrate 11 is selectively etched to a depth of about 1 μm, for example, by reactive ion etching.
While forming the dug groove 21, SiO2/Si3 is subsequently formed in the dug groove 21 using a vapor phase growth method.
By depositing N4 and also selectively removing it by reactive ion etching, the trenches 2 are formed.
A SiO2/Si3N4 layer 22 is formed on the inner wall surface of 1 (
Figure 1(c)).

Next, using the SiO2/Si3N4 layer 22 as a mask, the groove 21 is selectively dug to a depth of, for example, about 1 μm again by reactive ion etching, and then etched in the same manner. , SiO2
Using the /Si3N4 layer 22 as an implantation mask, P 2 is ion-implanted at a high concentration from an oblique direction into the side wall surface of the dug portion to form an n+ type source region 16 (FIG. 1(d)).

Furthermore, a p-type impurity, here B (boron), is ion-implanted into the bottom of the dug portion of the trench 21 to form a p- layer 20 for isolation between elements. The surface of the SiO2 is thermally oxidized in a dry oxygen atmosphere to form an oxide film 12, and polysilicon is again buried by vapor phase growth to form a buried layer 13, and the SiO2
/Si3N4 layer 22 is removed, and the SiO2/Si3N4 layer 22 is removed.
The removed portion of the Si3N4 layer 22 is thermally oxidized in a dry oxygen atmosphere to form a gate oxide film 15, and then polysilicon is deposited by vapor phase epitaxy, resist is patterned by photolithography, and The gate electrode 14 is selectively formed on the gate oxide film 15 by reactive ion etching (FIG. 1(e)).
).

After that, by performing a predetermined process, the drain region 17 and channel 18 are formed as expected.
A vertical structure transistor including an LDD structure having an n-type impurity layer 19 between the two can be extremely easily constructed.

[0020]

Effects of the Invention As described in detail above, according to the method of the present invention, a groove is formed in a direction perpendicular to a semiconductor substrate of a first conductivity type, and the channel has a channel on the inner wall surface. A source region is formed by a high concentration impurity layer of the second conductivity type on the inside of the substrate, and a drain is formed by a high concentration impurity layer of the second conductivity type via a low concentration impurity layer of the second conductivity type for the LDD structure on the main surface side of the substrate. L regions are formed in each region, and a gate electrode is formed on the channel via a gate oxide film.
In a method for manufacturing a vertical structure transistor including a DD structure, in a first step, impurities of a second conductivity type are ion-implanted at a low dose and with high implantation energy into the main surface of a semiconductor substrate of a first conductivity type. Then, in a second step, a second conductivity type impurity is formed over the first second conductivity type impurity layer using a high dose and low implantation energy. Since the second second conductivity type impurity layer is formed by ion implantation, the following effects are obtained.

[0021] That is, the second step in the first step of the former
Since the ion implantation of the conductivity type impurity is performed with high energy, the range of the ions is large, and the impurity ions penetrate deeper than the ion implantation of the second conductivity type impurity in the latter second step. Since the dose is small, the impurity concentration is lowered, forming a low concentration impurity layer of the second conductivity type for the LDD structure to be obtained. Because the ion implantation is performed at low energy, the range of the ions is small and the ions enter only shallowly. However, the dose is large, so the impurity concentration is increased, and this causes the drain to be formed by the second conductivity type high concentration impurity layer. A region is formed,
As a result, as described above, by combining the ion implantation of the second conductivity type impurity with a low dose and high implantation energy, and the ion implantation of the second conductivity type impurity with a high dose and low implantation energy, As expected, the LDD structure can be extremely easily realized even for vertical structure transistors, and this makes it possible to improve the characteristics, improve reliability, and extend the life of this type of vertical structure transistor. This provides excellent features.

[Brief explanation of the drawing]

1(a) to (e) schematically show in sequence the main manufacturing steps of a vertical structure transistor including an LDD structure to which an embodiment of the semiconductor device manufacturing method according to the present invention is applied; each section is a cross-sectional view; It is a diagram.

[Figure 2] (a) to (e) are conventional LDDs.
FIGS. 1A and 1B are cross-sectional views sequentially schematically showing the main manufacturing steps of the transistor according to the structure.

[Explanation of symbols]

11 P-type semiconductor substrate 12 Oxide film 13 Polysilicon buried layer 14 Gate electrode 15 Gate oxide film 16 N+ type source region 17 N+ type drain region 18 Channel 19 Low concentration impurity layer (n- type impurity layer) 20 Element isolation p -Layer 21 Digging groove 22 SiO2/Si3N4 layer

Claims (1)

[Claims] 1. A channel is formed on the inner wall surface of a trench dug in a direction perpendicular to a semiconductor substrate of a first conductivity type, and a highly concentrated impurity layer of a second conductivity type is formed on the inside side of the substrate of the channel. A source region and a drain region of a high concentration impurity layer of the second conductivity type are respectively formed on the main surface side of the substrate via a low concentration impurity layer of the second conductivity type for the LDD structure, and a gate oxidation layer is formed on the channel. A method for manufacturing a vertical structure transistor including an LDD structure in which a gate electrode is formed through a film, the method comprising: first implanting a semiconductor substrate with a low dose and high energy on the main surface of the semiconductor substrate of the first conductivity type; A first step of ion-implanting a second conductivity type impurity to form a first second conductivity type impurity layer; and a second step of ion-implanting a second conductivity type impurity using implantation energy to form a second second conductivity type impurity layer, the former first second conductivity type impurity layer forming the LDD structure. forming a low concentration impurity layer of a second conductivity type, forming a drain region of the high concentration impurity layer of the second conductivity type by the second second conductivity type impurity layer; , a method for manufacturing a semiconductor device, characterized in that each part of other constituent elements is sequentially formed.