JPH04286352A - Electronic component package - Google Patents

Electronic component package

Info

Publication number
JPH04286352A
JPH04286352A JP3075593A JP7559391A JPH04286352A JP H04286352 A JPH04286352 A JP H04286352A JP 3075593 A JP3075593 A JP 3075593A JP 7559391 A JP7559391 A JP 7559391A JP H04286352 A JPH04286352 A JP H04286352A
Authority
JP
Japan
Prior art keywords
insulating layer
opening
layer
package
metal plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3075593A
Other languages
Japanese (ja)
Inventor
Hiroshi Ohashi
寛 大橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Radio Co Ltd
Original Assignee
Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Radio Co Ltd filed Critical Japan Radio Co Ltd
Priority to JP3075593A priority Critical patent/JPH04286352A/en
Publication of JPH04286352A publication Critical patent/JPH04286352A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Abstract

PURPOSE:To enhance an electronic component in electrical properties by a method wherein it is lessened in grounding resistance and thermal resistance. CONSTITUTION:External connection terminals 12 and 12', a flat metal plate 11, a first insulating layer 13 provided with an opening, a second insulating layer 14, and a metal ring layer 15 are successively formed to constitute an electronic package, where an electronic element 16 is mounted on the plane metal plate 11. For the wiring of the electronic element 16 concerned, conductive patterns 18 and 19 are formed on the first insulating layer 13 to connect the element 16 to the outside. Furthermore, the peripheral part of the openings of the insulating layers is soldered to hermetically seal the package concerned.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、IC等の電子素子を気
密封止するために用いるパッケージに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package used for hermetically sealing electronic devices such as ICs.

【0002】0002

【従来の技術】従来のパッケージ構造を図3に示す。2. Description of the Related Art A conventional package structure is shown in FIG.

【0003】第1層、第2層、第3層のセラミック基板
1,2,3を積層し、第3層セラミック基板3の上にニ
ッケル鍍金した金属リング4が約800℃の温度でろう
付けされている。金属リング材料は、セラミックの熱膨
張差による歪み、クラックを防ぐためにコバールが用い
られる。
[0003] First, second, and third layer ceramic substrates 1, 2, and 3 are laminated, and a nickel-plated metal ring 4 is brazed on top of the third layer ceramic substrate 3 at a temperature of about 800°C. has been done. Kovar is used as the metal ring material to prevent distortion and cracking due to differences in thermal expansion of ceramics.

【0004】第1層セラミック基板1の中央部表面にタ
ングステン等の高融点金属を用いて導電パターン7が形
成され、パッケージが外側に設けられた接続端子部8へ
、パッケージ外側端面を介して接続されている。第2層
セラミック基板2の開口部周辺にも、高融点金属で導電
パターン7´が形成されパッケージ外側に設けられた接
続端子部8へ接続されている。第3層セラミック基板3
は、第2層セラミック基板2の開口部よりも大きな開口
部を有している。
A conductive pattern 7 is formed on the central surface of the first layer ceramic substrate 1 using a high melting point metal such as tungsten, and the package is connected to a connecting terminal portion 8 provided on the outside through the outer end surface of the package. has been done. A conductive pattern 7' made of a high melting point metal is also formed around the opening of the second layer ceramic substrate 2, and is connected to a connecting terminal section 8 provided on the outside of the package. Third layer ceramic substrate 3
has an opening larger than that of the second layer ceramic substrate 2.

【0005】第1層、第2層、第3層の各セラミック基
板1,2,3は、約1000℃以上の温度で積層し圧接
した状態で熱処理することにより、気密性を有する接合
が得られる。このようなパッケージ構造で、ICなどの
電子素子5は第2層セラミック基板2開口部に接着固定
される。第2層セラミック基板2上の導電パターン7´
と電子素子5とを細い金線6で接続した後、金属リング
4の上に金属の蓋9をかぶせる。蓋9の金属材料は通常
ニッケル鍍金したコバール板を用い、金属リング周辺を
溶接し電子素子5を気密封止する。電子素子5をこのよ
うに気密封止することで電子部品としての高い信頼性が
得られ、プリント基板などに組み込まれる。
[0005] The ceramic substrates 1, 2, and 3 of the first layer, second layer, and third layer are laminated at a temperature of approximately 1000° C. or higher and heat treated while being pressed together to obtain an airtight bond. It will be done. With such a package structure, the electronic device 5 such as an IC is adhesively fixed to the opening of the second layer ceramic substrate 2. Conductive pattern 7′ on second layer ceramic substrate 2
After connecting the electronic element 5 and the metal ring 4 with a thin gold wire 6, a metal lid 9 is placed over the metal ring 4. The metal material of the lid 9 is usually a nickel-plated Kovar plate, and the periphery of the metal ring is welded to hermetically seal the electronic element 5. By hermetically sealing the electronic element 5 in this manner, high reliability as an electronic component can be obtained, and the electronic element 5 can be incorporated into a printed circuit board or the like.

【0006】[0006]

【発明が解決しようとする課題】このようなパッケージ
を、プリント基板などに組み込んだ時、電子素子5の裏
面は、第1層セラミック基板1の中央部の導電パターン
7を介してプリント基板の接地回路に接続される。この
場合、第1層セラミック基板1の導電パターン7の電気
抵抗、及び熱抵抗が大きいことにより電気特性が劣化す
るこがあった。
[Problem to be Solved by the Invention] When such a package is assembled into a printed circuit board, etc., the back surface of the electronic element 5 is connected to the ground of the printed circuit board via the conductive pattern 7 in the center of the first layer ceramic substrate 1. connected to the circuit. In this case, the electrical characteristics may deteriorate due to the large electrical resistance and thermal resistance of the conductive pattern 7 of the first layer ceramic substrate 1.

【0007】[0007]

【課題を解決するための手段】本発明はこれらの欠点を
解決するため、パッケージの構成を、下部から外部接続
端子板及び平面金属板、開口部を有する第1、第2絶縁
層、金属リング層を順次積層し、底面の平面金属板に電
子素子を装着し、その配線のため第1絶縁層に導電パタ
ーンを形成してスルーホール構造で外部接続を行い、か
つ前記各絶縁層の開口部周辺をろう付けにより密封構造
としたもので、以下実施例につき図面により詳細に説明
する。
[Means for Solving the Problems] In order to solve these drawbacks, the present invention changes the structure of the package from the bottom to the external connection terminal plate, the flat metal plate, the first and second insulating layers having openings, and the metal ring. Layers are sequentially laminated, an electronic element is mounted on a flat metal plate on the bottom surface, a conductive pattern is formed on the first insulating layer for wiring, external connection is made with a through-hole structure, and openings in each of the insulating layers are formed. The periphery is sealed by brazing, and examples will be explained in detail below with reference to the drawings.

【0008】[0008]

【実施例】図1は本発明の実施例で、パッケージの破断
面を示す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention, showing a broken surface of a package.

【0009】11は0.2mm厚みのコバールを用いた
金属板で、約0.5mm厚さの第1アルミナ絶縁基板1
3の開口部を密閉するように、開口部周辺でろう付けさ
れている。12の接続端子板も、第1アルミナ絶縁基板
13の開口部周辺でろう付けされている。12´は金属
板11と一体成形された接続端子板である。
Reference numeral 11 denotes a metal plate made of Kovar with a thickness of 0.2 mm, and a first alumina insulating substrate 1 with a thickness of about 0.5 mm.
3 is brazed around the opening to seal it. 12 connection terminal plates are also brazed around the opening of the first alumina insulating substrate 13. 12' is a connection terminal plate integrally formed with the metal plate 11.

【0010】第1アルミナ絶縁基板13表面には、タン
グステン等の高融点金属で導電パターン18を形成し、
パッケージ外部接続パターン19を介して接続端子板1
2と接続している。
A conductive pattern 18 is formed on the surface of the first alumina insulating substrate 13 using a high melting point metal such as tungsten.
Connection terminal plate 1 via package external connection pattern 19
It is connected to 2.

【0011】第2アルミナ絶縁基板14は約0.5mm
の厚みで、第1アルミナ絶縁基板13の開口部よりも1
〜2mm大きな開口部を有する。第1アルミナ絶縁基板
13、第2アルミナ絶縁基板14は圧接しながら約10
00℃の温度で熱処理することで気密性の接合が得られ
る。コバールリング15は、約0.5mm厚みのコバー
ル金属板を、約0.5mm幅のリング状に成形し、ニッ
ケル鍍金したもので、第2アルミナ絶縁基板14の開口
部周辺でろう付けされている。ICなどの電子素子16
は、第1アルミナ絶縁基板13の開口部の金属板11に
接着固定し、従来と同様に組み立て電子部品とした後、
プリント基板などの外部回路に組み込まれる。
The second alumina insulating substrate 14 has a thickness of about 0.5 mm.
The thickness is 1 mm thicker than the opening of the first alumina insulating substrate 13.
It has a ~2mm large opening. The first alumina insulating substrate 13 and the second alumina insulating substrate 14 are pressed together while
An airtight bond can be obtained by heat treatment at a temperature of 00°C. The Kovar ring 15 is made by forming a Kovar metal plate with a thickness of about 0.5 mm into a ring shape with a width of about 0.5 mm, plated with nickel, and brazed around the opening of the second alumina insulating substrate 14. . Electronic device 16 such as IC
is adhesively fixed to the metal plate 11 in the opening of the first alumina insulating substrate 13 and assembled into an electronic component in the same manner as before.
Built into external circuits such as printed circuit boards.

【0012】図2は、本発明のパッケージを用いた応用
を示す実施例で、図1の金属板11、接続端子板12´
を金属フレーム22´と一体成形し、複数個のパッケー
ジ21を連結したものである。第1アルミナ基板上の導
電パターン23と金属フレーム22とはパッケージの外
部端面を介し接続されている。電子素子をパッケージに
組み込み、従来と同様に金属蓋で気密封止した後、金属
フレーム22,22´をパッケージから切り離し、電子
部品として使用する。この実施例では、パッケージ21
が整列されているので、大量に電子素子をパッケージ2
1のアルミナ基板開口部24に組み込む場合の工数が減
る利点がある。このように、本発明のパッケージでは電
子素子を電気抵抗、および熱抵抗の低い金属板に接着固
定する構造になっているので、電子素子の裏面と、外部
の接地回路の間の電気抵抗、熱抵抗を著しく小さくする
ことができる。
FIG. 2 shows an example of an application using the package of the present invention, in which the metal plate 11 and the connection terminal plate 12' of FIG.
is formed integrally with a metal frame 22', and a plurality of packages 21 are connected to each other. The conductive pattern 23 on the first alumina substrate and the metal frame 22 are connected through the outer end surface of the package. After the electronic element is assembled into a package and hermetically sealed with a metal lid as in the conventional case, the metal frames 22, 22' are separated from the package and used as an electronic component. In this example, package 21
are aligned, so a large amount of electronic devices can be packaged 2
There is an advantage that the number of steps required for assembly into the alumina substrate opening 24 of No. 1 is reduced. In this way, the package of the present invention has a structure in which the electronic element is adhesively fixed to a metal plate with low electrical resistance and thermal resistance. The resistance can be significantly reduced.

【0013】[0013]

【発明の効果】以上説明したように、パッケージ底面に
金属板を用いた構成にしたことにより電気部品としてP
C板などの回路基板に組み込んだときの接地抵抗、熱抵
抗を小さくでき、電気特性を改善できる効果がある。
[Effects of the Invention] As explained above, by using a metal plate on the bottom of the package, it can be used as an electrical component.
When incorporated into a circuit board such as a C board, ground resistance and thermal resistance can be reduced, and electrical characteristics can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例を示す破断図。FIG. 1 is a cutaway view showing one embodiment of the present invention.

【図2】本発明のパッケージを用いた応用例。FIG. 2 is an application example using the package of the present invention.

【図3】従来例の破断図。FIG. 3 is a cutaway view of a conventional example.

【符号の説明】[Explanation of symbols]

11    金属板 12    接続端子板 12´  接続端子板 13    第1アルミナ絶縁基板 14    第2アルミナ絶縁基板 15    コバールリング 16    電子素子 17    金線 18    導電パターン 19    外部接続パターン 21    パッケージ 22    金属フレーム 22´  金属フレーム 23    導電パターン 24    アルミナ基板開口部 11 Metal plate 12 Connection terminal board 12´  Connection terminal board 13 First alumina insulating substrate 14 Second alumina insulating substrate 15 Kovar Ring 16 Electronic elements 17 Gold wire 18 Conductive pattern 19 External connection pattern 21 Package 22 Metal frame 22´  Metal frame 23 Conductive pattern 24 Alumina substrate opening

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  1層目は外部接続端子板及び平面金属
板、2層目は開口部を有する第1絶縁層、3層目は第1
絶縁層の開口部よりも大きな開口部を有する第2絶縁層
、4層目は金属リング層である4つの各層を積層した構
造からなる電子部品パッケージにおいて、前記底面の平
面金属板は、第1絶縁層の開口部を密閉するようにその
開口部周辺でろう付けされ、また外部接続端子板も第1
絶縁層の開口部周辺でろう付けされ、前記第1層絶縁層
は、その表面にパッケージ外部へ導通している導電パタ
ーンが形成され、外部接続端子板へスルーホール構造で
接続し、前記第2絶縁層は、第1絶縁層の開口部周辺で
接合され、前記金属リング層は、第2絶縁層の開口部周
辺でろう付けされていることを特徴とする電子部品パッ
ケージ。
Claim 1: The first layer is an external connection terminal plate and a flat metal plate, the second layer is a first insulating layer having an opening, and the third layer is a first insulating layer with an opening.
In an electronic component package having a structure in which four layers are stacked, the second insulating layer having an opening larger than the opening in the insulating layer, and the fourth layer being a metal ring layer, the flat metal plate on the bottom surface is The opening of the insulating layer is soldered around the opening to seal it, and the external connection terminal board is also connected to the first
The first insulating layer is brazed around the opening of the insulating layer, and the first insulating layer has a conductive pattern formed on its surface that is conductive to the outside of the package, and is connected to the external connection terminal board with a through-hole structure. An electronic component package characterized in that the insulating layers are bonded around the opening in the first insulating layer, and the metal ring layer is brazed around the opening in the second insulating layer.
【請求項2】  前記底面の平面金属板は、少なくとも
1個の外部接続端子板と一体に成形されていることを特
徴とする請求項第1項記載の電子部品パッケージ。
2. The electronic component package according to claim 1, wherein the bottom plane metal plate is integrally formed with at least one external connection terminal plate.
JP3075593A 1991-03-15 1991-03-15 Electronic component package Pending JPH04286352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3075593A JPH04286352A (en) 1991-03-15 1991-03-15 Electronic component package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3075593A JPH04286352A (en) 1991-03-15 1991-03-15 Electronic component package

Publications (1)

Publication Number Publication Date
JPH04286352A true JPH04286352A (en) 1992-10-12

Family

ID=13580656

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3075593A Pending JPH04286352A (en) 1991-03-15 1991-03-15 Electronic component package

Country Status (1)

Country Link
JP (1) JPH04286352A (en)

Similar Documents

Publication Publication Date Title
JP3009788B2 (en) Package for integrated circuit
US5227583A (en) Ceramic package and method for making same
US3673309A (en) Integrated semiconductor circuit package and method
US3303265A (en) Miniature semiconductor enclosure
JPH08274575A (en) Composite element mount circuit board
JPH0239097B2 (en)
JPS62257759A (en) Hybrid integrated circuit high voltage insulated amplifier package and manufacture of the same
JPH01168045A (en) Hermetically sealed circuit device
JPH04206658A (en) Hermetic seal type electric circuit device
JPH04286352A (en) Electronic component package
JP2005072421A (en) Package for housing electronic component and electronic device
JPH03196664A (en) Package for semiconductor device
JP2942424B2 (en) Package for storing semiconductor elements
JP3847220B2 (en) Wiring board
JP3850338B2 (en) Wiring board
JP3847216B2 (en) Wiring board
JP2002289748A (en) Substrate for mounting electronic component
JP3464137B2 (en) Electronic component storage package
JP3441170B2 (en) Wiring board
JP3780503B2 (en) Wiring board
JP3722737B2 (en) Wiring board
JP3020783B2 (en) Package for storing semiconductor elements
JP3020743B2 (en) Lead frame
JP3872400B2 (en) Electronic component storage package
JP2003068920A (en) Wiring board