JPH04286351A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04286351A
JPH04286351A JP5148891A JP5148891A JPH04286351A JP H04286351 A JPH04286351 A JP H04286351A JP 5148891 A JP5148891 A JP 5148891A JP 5148891 A JP5148891 A JP 5148891A JP H04286351 A JPH04286351 A JP H04286351A
Authority
JP
Japan
Prior art keywords
film
oxide film
gas
forming
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5148891A
Other languages
Japanese (ja)
Inventor
Shingo Omuro
大室 晋吾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP5148891A priority Critical patent/JPH04286351A/en
Publication of JPH04286351A publication Critical patent/JPH04286351A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To restrain gas from being discharged from a glass film so as to prevent a wiring disconnection caused by corrosion by a method wherein there are provided a process where a gas protective film is formed on an oxide film and the whole surface of an opening region and another process where the gas protective film is removed excluding the side wall of the opening through etching. CONSTITUTION:In this manufacturing method, an oxide film 5, a coated glass film 4, and an oxide film 3 are successively etched in this order using a patterned photosensitive film 6 as a mask to provide openings 7 to an aluminum wiring 2. After the photosensitive film 6 is removed, a gas protective film 8 is formed on the oxide film 5 and all the surface of the opening 7. Then, the gas protective film 8 is removed through dry etching excluding the side walls of the openings 7. In result, gas is prevented from generating from a glass film layer, so that a wiring is protected against corrosion.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に半導体基板上に形成した異なる配線層を接
合させる技術に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for bonding different wiring layers formed on a semiconductor substrate.

【0002】0002

【従来の技術】図2(a)〜(e)は従来の製造方法の
工程順を示す断面図である。まず、図2(a)に示すよ
うに絶縁膜1上にパターニングしたアルミニウム配線2
上に、CVD法により酸化膜3を形成する。次に図2(
b)に示すように酸化膜3上に塗布ガラス膜4を形成す
る。次に図2(c)に示すように塗布ガラス膜4上にC
VD法により再び酸化膜5を形成する。
2. Description of the Related Art FIGS. 2(a) to 2(e) are cross-sectional views showing the order of steps in a conventional manufacturing method. First, as shown in FIG. 2(a), aluminum wiring 2 is patterned on an insulating film 1.
An oxide film 3 is formed thereon by the CVD method. Next, Figure 2 (
As shown in b), a coated glass film 4 is formed on the oxide film 3. Next, as shown in FIG. 2(c), apply C on the coated glass film 4.
An oxide film 5 is formed again by the VD method.

【0003】次に図2(d)に示すようにパターニング
した感光性膜6をマスクとして、酸化膜5、塗布ガラス
膜4及び酸化膜3の順にエッチングを行い、アルミニウ
ム配線2上に開孔部7を形成する。次に図2(e)に示
すように感光性膜6を除去する。
Next, as shown in FIG. 2(d), using the patterned photosensitive film 6 as a mask, the oxide film 5, coated glass film 4, and oxide film 3 are etched in this order to form an opening on the aluminum wiring 2. form 7. Next, as shown in FIG. 2(e), the photosensitive film 6 is removed.

【0004】0004

【発明が解決しようとする課題】しかしながら、上述し
たような従来の方法では開孔部側壁にガラス膜層が露出
するので、後工程の熱処理等により、露出したガラス膜
層から水分を含んだガスが発生し、このガス中の成分に
よって配線が腐食されるおそれがあった。
[Problems to be Solved by the Invention] However, in the conventional method as described above, the glass film layer is exposed on the side wall of the opening, so that gas containing moisture is removed from the exposed glass film layer during heat treatment in a post-process. was generated, and there was a risk that the wiring would be corroded by the components in this gas.

【0005】[0005]

【課題を解決するための手段】本発明は、上記のような
点に鑑みてなされたもので、開孔部側壁をガス防護膜で
覆った。
[Means for Solving the Problems] The present invention has been made in view of the above points, and the side wall of the opening is covered with a gas protective film.

【0006】[0006]

【作用】上記のような方法を用いれば、開孔部側壁にガ
ラス膜が露出しないので、脱ガスが抑えられる。
[Operation] By using the method described above, the glass film is not exposed on the side wall of the opening, so that outgassing can be suppressed.

【0007】[0007]

【実施例】以下、本発明の実施例について詳細に説明す
る。まず、図1(a)に示すように絶縁膜1上にパター
ニングしたアルミニウム配線2上に、CVD法により酸
化膜3を形成する。次に、図1(b)に示すように酸化
膜3上に平坦化のための塗布ガラス膜4を形成する。
[Examples] Examples of the present invention will be described in detail below. First, as shown in FIG. 1(a), an oxide film 3 is formed on an aluminum wiring 2 patterned on an insulating film 1 by a CVD method. Next, as shown in FIG. 1(b), a coated glass film 4 for planarization is formed on the oxide film 3.

【0008】次に、図1(c)に示すように塗布ガラス
膜4上に、CVD法により再び酸化膜5を形成する。次
に、図1(d)に示すようにパターニングした感光性膜
6をマスクとして、酸化膜5、塗布ガラス膜4及び酸化
膜3の順にエッチングを行い、アルミニウム配線2上に
開孔部7を形成する。次に、図1(e)に示すように感
光性膜6を除去した後、酸化膜5と開孔部7の全面にガ
ス保護膜8をプラズマCVD法により形成する。次に、
図1(f)に示すように窒化膜8を、開孔部7側壁を除
きドライエッチングにより除去する。
Next, as shown in FIG. 1(c), an oxide film 5 is again formed on the coated glass film 4 by the CVD method. Next, using the patterned photosensitive film 6 as a mask, as shown in FIG. Form. Next, as shown in FIG. 1E, after removing the photosensitive film 6, a gas protective film 8 is formed on the entire surface of the oxide film 5 and the opening 7 by plasma CVD. next,
As shown in FIG. 1(f), the nitride film 8 is removed by dry etching except for the side walls of the opening 7.

【0009】上記ガス保護膜としては、窒化膜、オキシ
ナイトライド膜を用いるのがよい。
[0009] As the gas protection film, it is preferable to use a nitride film or an oxynitride film.

【0010】0010

【発明の効果】本発明によれば、微細化、高集積化を必
要とする超LSIの製造工程において、ガラス膜を用い
たことにより多層配線の層間絶縁膜の平坦化が達成され
ると同時に、多層配線を接合するためのコンタクトホー
ルには、ガス防護膜を用いたことによりガラス膜が露出
しないので、脱ガスが抑えられ、配線の腐食による断線
不良がなくなる。よって半導体装置の信頼性が向上する
Effects of the Invention According to the present invention, in the manufacturing process of VLSIs that require miniaturization and high integration, by using a glass film, it is possible to achieve flattening of the interlayer insulating film of multilayer wiring. Since the glass film is not exposed in the contact hole for joining the multilayer wiring by using a gas protective film, degassing is suppressed and disconnection defects due to corrosion of the wiring are eliminated. Therefore, reliability of the semiconductor device is improved.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の製造方法の工程順を示す断面図である
FIG. 1 is a cross-sectional view showing the order of steps in the manufacturing method of the present invention.

【図2】従来の製造方法の工程順を示す断面図である。FIG. 2 is a cross-sectional view showing the order of steps in a conventional manufacturing method.

【符号の説明】[Explanation of symbols]

1  絶縁膜 2  アルミニウム配線 3  酸化膜 4  塗布ガラス膜 5  酸化膜 6  感光性膜 7  開孔部 8  ガス防護膜 1 Insulating film 2 Aluminum wiring 3 Oxide film 4 Coated glass film 5 Oxide film 6 Photosensitive film 7 Opening part 8 Gas protective membrane

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】  半導体基板の主面に所望の素子を形成
し、全面に第1の酸化膜を形成する工程と、前記酸化膜
上に塗布ガラス膜を全面に形成し、凹凸部に滑らかな斜
面を形成する工程と、前記ガラス膜上に第2の酸化膜を
形成する工程と、前記第1、第2の酸化膜とガラス膜の
所望の部分を開孔する工程と、前記酸化膜上と開孔領域
全面にガス防護膜を形成する工程と、前記ガス防護膜を
開孔部側壁を除きエッチングにより除去する工程を含む
ことを特徴とする半導体装置の製造方法。
1. A step of forming a desired element on the main surface of a semiconductor substrate and forming a first oxide film on the entire surface, and forming a coated glass film on the entire surface of the oxide film to smooth the uneven parts. a step of forming a slope, a step of forming a second oxide film on the glass film, a step of opening holes in desired portions of the first and second oxide films and the glass film, and a step of forming a hole on the oxide film. A method for manufacturing a semiconductor device, comprising the steps of: forming a gas protective film over the entire surface of the opening region; and removing the gas protective film by etching except for the sidewall of the opening.
【請求項2】  前記ガス防護膜は窒化膜である請求項
1記載の半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the gas protection film is a nitride film.
【請求項3】  前記ガス防護膜はオキシナイトライド
膜である請求項1記載の半導体装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the gas protection film is an oxynitride film.
JP5148891A 1991-03-15 1991-03-15 Manufacture of semiconductor device Pending JPH04286351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5148891A JPH04286351A (en) 1991-03-15 1991-03-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5148891A JPH04286351A (en) 1991-03-15 1991-03-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04286351A true JPH04286351A (en) 1992-10-12

Family

ID=12888355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5148891A Pending JPH04286351A (en) 1991-03-15 1991-03-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04286351A (en)

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