JPH04286127A - Manufacture of insulated-gate field-effect transistor - Google Patents

Abstract

PURPOSE:To eliminate easy arrival of dopant at a gate oxide film through a lower semiconductor layer by forming a gate electrode in a multilayer structure of a semiconductor layer of a lower layer and a semiconductor or metal layer of an upper layer, and interposing a layer insulating film having a diffusion blocking capacity between the layers of the electrode layers. CONSTITUTION:A substrate is heat treated by a RTA(Rapid Thermal Annealing) using a lamp. In this case, an SiO2 film 5 between thin gate layers is melted to disappear in upper first and lower second polycrystalline Si layers 4 and 5. Boron implanted in the layer 4 is diffused at once in the layer 4 to reach a gate oxide film 3, and a p<+> type polycrystalline Si gate electrode 10 is formed. Since the RTA is conducted in an extremely short time, the boron in the layer 4 does not pass through the gate oxide film and arrive at the surface of an n-type Si substrate 1.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a method for manufacturing an insulated gate field effect transistor, and more specifically, when devices are miniaturized and polycrystalline silicon gate electrodes become thinner, impurities in the gate electrodes are reduced. In particular, when a pMOS transistor is a surface channel type in a CMOS circuit and p-type polycrystalline silicon is used as a gate electrode, the dopant introduced into the gate electrode is prevented from penetrating into the substrate. This provides a means to stably manufacture high-performance devices.

0002

Conventionally, insulated gate field effect transistors formed on silicon wafers use polycrystalline silicon as the gate electrode material because it is easy to set a low threshold voltage. is phosphine (PH3) or phosphorus oxychloride (
By thermal decomposition of POCl3), phosphorus was diffused in the vapor phase and doped into n-type.

On the other hand, complementary MOS (
In a CMOS (CMOS) circuit, the aforementioned n-type polycrystalline silicon is usually used for both the gate electrode of an nMOS transistor and the gate electrode of a pMOS transistor. Therefore, in order to set the threshold voltage of the pMOS transistor to around 0V, it is necessary to make the vicinity of the surface of the channel region of the pMOS transistor slightly p-type. At this time,
The channel of the pMOS transistor is formed slightly inside the substrate surface and is of a buried channel type. This buried channel type transistor has the advantage that carrier mobility is higher than that of a surface channel type transistor in which a channel is formed on the surface of a substrate, so that the driving ability of the transistor can be increased. However, due to the deep channel,
There is a drawback that when the channel length of a transistor is shortened, a so-called short channel effect is likely to occur, such as a decrease in threshold voltage or an increase in the likelihood of punch-through breakdown.

Therefore, in order to avoid the drawback that it is difficult to reduce the gate length of the buried channel type, C.
In a MOS circuit, a method has been proposed in which a pMOS transistor is made into a surface channel type by using p-type polycrystalline silicon for its gate electrode.

[0005]

[Problem to be solved by the invention] Surface channel type pMO
In S transistors, boron (B) is used as a dopant to make the polycrystalline silicon gate electrode p-type, but boron is also used as an n-type impurity such as phosphorus (P) or arsenic (As).
In contrast, the segregation coefficient at the [silicon/oxide film] interface during diffusion is smaller than 1, and there is a phenomenon in which boron introduced into the polycrystalline silicon gate electrode is absorbed by the underlying gate oxide film during the heat treatment process. This phenomenon is caused by the fact that when the device size is large and the gate oxide film is thick, even if boron is absorbed into the gate oxide film, the diffusion coefficient of boron in the oxide film is more than an order of magnitude smaller than that of silicon. Therefore, it is not a particular problem. However, if the device dimensions are reduced and the gate oxide film becomes thinner, the boron incorporated during gate oxidation passes through the gate oxide film and reaches the semiconductor substrate surface, causing the n-type semiconductor substrate to pass through the gate oxide film. This causes a problem in that the surface of the transistor is inverted to p-type and the threshold voltage is shifted positively. This phenomenon in which the dopant in the gate electrode material passes through the gate insulating film and reaches the surface of the semiconductor substrate is tentatively referred to as dopant penetration.

Therefore, the present invention aims to reduce the device size from sub-half micron to sub-quarter micron, and the thickness of the gate insulating film is accordingly extremely thin.
When making an S transistor into a surface channel type using a boron-doped p-type polycrystalline silicon gate electrode,
The purpose of this invention is to prevent boron from penetrating from the gate electrode to the substrate surface during the heat treatment described above, and to stably provide a high-performance CMOS integrated circuit.

[0007]

[Means for Solving the Problems] The above-mentioned problems include a step of forming a gate insulating film on a semiconductor substrate, and a step of forming a gate insulating film on the gate insulating film, the bottom layer of which is a semiconductor layer, and a thickness of 1 nm between each layer.
A step of forming a multilayer gate electrode consisting of a plurality of semiconductor layers or a semiconductor layer and a metal layer stacked via an interlayer insulating film with a thickness of 3 nm to 3 nm, and a semiconductor layer other than at least the bottom semiconductor layer of the multilayer gate electrode. layer or metal layer,
A step of introducing a dopant to impart conductivity to the lowermost semiconductor layer, and heating the semiconductor substrate to 1050° C. or higher, and bringing the interlayer insulating film of the multilayer gate electrode into contact with the top and bottom of the interlayer insulating film. According to the method for manufacturing an insulated gate field effect transistor according to the present invention, the dopant is dissolved and disappeared in the semiconductor or metal layer, and the dopant is solid-phase diffused from the upper semiconductor or metal layer into the lowermost semiconductor layer. resolved.

[0008]

[Operation] That is, in the present invention, the gate electrode has a multilayer structure consisting of a lower semiconductor layer (for example, a polycrystalline silicon layer) and an upper semiconductor or metal layer (for example, a polycrystalline silicon layer), and a dopant ( For example, an interlayer insulating film (for example, a SiO2 film) having a diffusion coefficient of boron (for example, boron) smaller than that of silicon and having a diffusion blocking ability is interposed. Therefore, even if the segregation coefficient of the dopant (e.g., boron) at the interface between the upper semiconductor or metal layer and the interlayer insulating film (e.g., polycrystalline silicon/SiO2 interface) is smaller than 1, the interlayer insulating film (e.g., SiO2 film) Because it has the ability to prevent dopant diffusion, the dopant (e.g., boron) does not easily reach the gate oxide film through the underlying semiconductor layer (e.g., polycrystalline silicon layer) due to the heat treatment process during the manufacturing process.

[0009] Furthermore, according to recent research using a transmission electron microscope, when a very thin SiO2 film of 1 nm to just under 3 nm sandwiched between polycrystalline silicon layers is heat-treated at a high temperature of 1050°C or higher, the heat treatment will deteriorate. It turns out that it disappears even for a short period of a few seconds. The mechanism of this phenomenon is still unclear, but the oxygen atoms that make up the oxide
It is assumed that it has dissolved into polycrystalline silicon.

In view of the above points, in the present invention, the gate electrode has a dopant diffusion blocking ability as described above,
In addition, as mentioned above, the lower semiconductor layer is connected to the underlying semiconductor layer through a very thin interlayer insulating film that is dissolved and removed by semiconductors and metals at high temperatures.
It has a multilayer structure in which the upper semiconductor or metal layer is laminated, and the dopant for imparting conductivity to the lower semiconductor layer is ion-implanted into the upper semiconductor or metal layer.
It is introduced by vapor phase growth method or solid phase diffusion method. Therefore, heat treatment during the subsequent manufacturing process (growth of interlayer insulating film,
Penetration of the dopant into the semiconductor substrate surface during reflow of the interlayer insulating film, etc.) is prevented by the interlayer insulating film of the gate. And as a high temperature heat treatment at the end of the process, 10
Short-time heat treatment (RTA: Ra
The interlayer insulating film of the gate is dissolved and disappeared by thermal annealing, and the dopant is diffused into the underlying semiconductor layer to impart conductivity to the underlying semiconductor layer. Since this heat treatment is for a very short time, the dopant does not penetrate through the gate oxide film and reach the semiconductor substrate surface, and no threshold fluctuation occurs in the transistor.

[0011]

[Example] The present invention will be described below with reference to an example shown in FIG.
) to (d) and process cross-sectional views shown in FIGS. 2(a) to (d). Note that the same objects are indicated by the same reference numerals throughout the figures.

Refer to FIG. 1(a) When forming a p-channel insulated gate field effect transistor (pMOS) by the method of the present invention, an n-type silicon (Si) substrate 1 is formed by, for example, selective oxidation (LOCOS) method as usual. A field oxide film 2 defining and exposing an element formation region 101 is formed on the surface.

Referring to FIG. 1(b), a gate oxide film 3 is then formed to a thickness of, for example, 7 nm on the element formation region 101 by thermal oxidation as usual.

Referring to FIG. 1(c), next, a first polycrystalline Si layer 4, which will become the lower gate electrode layer, is formed on the entire surface of the substrate to a thickness of, for example, 20 nm by CVD.
Then, on the first polycrystalline Si layer 4, a thin SiO2 film 5, which will become a gate interlayer insulating film, is formed with a thickness of, for example, 1 nm by thermal oxidation or CVD method, and then an upper layer is formed on it. The second polycrystalline Si becomes the gate electrode layer of
Layer 6 is formed with a thickness of, for example, 100 nm by CVD.

Referring to FIG. 1(d), the second polycrystalline Si layer 6, the SiO2 film 5, and the first polycrystalline Si layer 4 are then etched by a normal lithography method using reactive ion etching as an etching means. A thin SiO2 film 5 with a thickness of 1 nm is formed on the lower gate electrode layer made of the first polycrystalline Si layer 4 by sequential patterning.
A second polycrystalline S via a gate electrode interlayer insulating film consisting of
A multilayer gate electrode 110 is formed in which an upper gate electrode layer consisting of the i-layer 6 is laminated.

Referring to FIG. 2A, next, using the multilayer gate electrode 110 as a mask, boron ions (B
+ ) with acceleration energy of 5KeV and dose of 2×1
Ion implantation is performed at 0-2 to form a B+ implanted region 107S for the source region and a B+ implanted region 107D for the drain region.
form. At this time, the second polycrystalline Si layer 6 on the multilayer gate electrode 110 is also treated with B+
is injected. 106 indicates the B+ implantation region.

Referring to FIG. 2(b), next, as usual, an interlayer SiO2 film 8 with a thickness of about 200 nm and an interlayer SiO2 film 8 with a thickness of 30 nm are formed on the entire surface of the substrate by CVD.
An interlayer phosphosilicate glass (PSG) film 9 of about 0 nm in thickness is sequentially deposited. Then, as usual, the PSG film 9 is annealed in a nitrogen atmosphere at 850° C. At this time, B+ is activated and redistributed in the B+ implanted region 107S for the source region and the B+ implanted region 107D for the drain region. Thus, an n+ type source region 7A and an n+ type drain region 7B are formed. In addition, B+ implanted into the second polycrystalline Si layer 6 is also activated and diffused to reach the SiO2 film 5 between the gate layers, and a small amount of B+ is absorbed into the first layer below.
oozes into the polycrystalline Si layer 4, but the amount is extremely small. (6n is the n+ type second polycrystalline Si layer) See Figure 2(c) Next, RTA using a lamp (Rapid Thermal
1100 on the board by
Heat treatment is performed at ℃ for 5 seconds. At this time, S between the thin gate layers
The iO2 film 5 consists of upper and lower first and second polycrystalline Si layers 4 and 6.
The boron implanted into the second polycrystalline Si layer 4 diffuses into the first polycrystalline Si layer 4 and reaches the gate oxide film 3, forming a p+ type polycrystalline Si gate. Electrode 1
0 is formed. Note that since this RTA treatment is extremely short, boron in the first polycrystalline Si layer 4 does not penetrate through the gate oxide film 3 and reach the n-type Si substrate 1 surface, so that the boron in the first polycrystalline Si layer 4 does not penetrate into the gate lower region. The n-type impurity concentration is maintained at the initial value, and the threshold value does not change.

Referring to FIG. 2(d), contact holes are then formed in the interlayer PSG film 9 and the interlayer SiO2 film 8 according to the usual integrated circuit manufacturing process, and source wiring 11S and drain wiring 11D made of aluminum or the like are formed. Such surface channel type pM
The OS transistor is completed.

In the above embodiments, the present invention was applied to n-type Si.
Although the case where only a pMOS transistor is formed on a substrate has been described, the present invention can be implemented in exactly the same way even if a step of manufacturing an nMOS transistor is inserted between the above steps in a CMOS process.

In the method of the present invention, a refractory metal or a refractory metal silicide such as tungsten silicide (WSi2) may also be used for the upper gate electrode layer.
A similar effect can be obtained. Furthermore, the number of upper gate electrode layers is not limited to one layer.

Furthermore, silicon nitride or the like can also be used for the gate interlayer insulating film.

[0022]

[Effects of the Invention] As explained above, according to the present invention, p
Even when a MOS transistor is made to function as a surface channel transistor using a p-type polysilicon gate, boron doped in the gate electrode does not penetrate into the substrate and cause threshold fluctuation. Therefore pMOS
Since a CMOS circuit can be constructed by converting a transistor into a surface channel, even if the CMOS circuit is miniaturized to the quarter-micron region, it becomes possible to stably provide a high-performance integrated circuit without causing short channel effects.

[Brief explanation of the drawing]

[Fig. 1] Process cross-sectional diagram of one embodiment of the method of the present invention (Part 1)

[Fig. 2] Process sectional view of an embodiment of the method of the present invention (Part 2)

[Explanation of symbols] 1 n-type Si substrate 2 field oxide film 3 gate oxide film 4 first polycrystalline Si layer 5 thin SiO2 film 6 second polycrystalline Si layer 7S n+ type source region 7D n+ type drain region 8 interlayer SiO2 film 9 Interlayer PSG film 10 N+ type polycrystalline Si gate electrode 11S Source wiring 11D Drain wiring 101 Element formation region 106 B+ injection region 107S B+ injection region 107D for source region
B+ injection region 110 for drain region Multilayer gate electrode

Claims (2)

[Claims] 1. A step of forming a gate insulating film on a semiconductor substrate, and stacking layers on the gate insulating film, the bottom layer of which is a semiconductor layer, and an interlayer insulating film with a thickness of 1 nm to 3 nm interposed between each layer. forming a multilayer gate electrode consisting of a plurality of semiconductor layers or a semiconductor layer and a metal layer; A step of introducing a dopant to impart conductivity to the layer, and heating the semiconductor substrate to a temperature of 1050° C. or higher, and forming the interlayer insulating film of the multilayer gate electrode into a semiconductor or metal layer that contacts above and below the interlayer insulating film. A method for manufacturing an insulated gate field effect transistor, comprising the steps of: dissolving and dissipating the dopant into the lowermost semiconductor layer, and solid-phase diffusing the dopant from the upper semiconductor or metal layer into the lowermost semiconductor layer. 2. The semiconductor substrate is made of n-type silicon, the semiconductor layer is made of polycrystalline silicon, the insulating film is made of silicon oxide film, and the dopant is made of boron. A method of manufacturing the insulated gate field effect transistor described above.