JPH0428180B2 - - Google Patents

Info

Publication number
JPH0428180B2
JPH0428180B2 JP60214453A JP21445385A JPH0428180B2 JP H0428180 B2 JPH0428180 B2 JP H0428180B2 JP 60214453 A JP60214453 A JP 60214453A JP 21445385 A JP21445385 A JP 21445385A JP H0428180 B2 JPH0428180 B2 JP H0428180B2
Authority
JP
Japan
Prior art keywords
variables
input
output
multiplexers
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60214453A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6189721A (ja
Inventor
Herutsure Yoozefu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of JPS6189721A publication Critical patent/JPS6189721A/ja
Publication of JPH0428180B2 publication Critical patent/JPH0428180B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733Controllable logic circuits
    • H03K19/1737Controllable logic circuits using multiplexers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Electronic Switches (AREA)
JP60214453A 1984-09-28 1985-09-27 組合せ論理発生回路 Granted JPS6189721A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3435774 1984-09-28
DE3435774.2 1984-09-28

Publications (2)

Publication Number Publication Date
JPS6189721A JPS6189721A (ja) 1986-05-07
JPH0428180B2 true JPH0428180B2 (zh) 1992-05-13

Family

ID=6246689

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60214453A Granted JPS6189721A (ja) 1984-09-28 1985-09-27 組合せ論理発生回路

Country Status (5)

Country Link
US (1) US4825105A (zh)
EP (1) EP0176938B1 (zh)
JP (1) JPS6189721A (zh)
AT (1) ATE53152T1 (zh)
DE (1) DE3577953D1 (zh)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5451887A (en) * 1986-09-19 1995-09-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
US5477165A (en) * 1986-09-19 1995-12-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
US4940908A (en) * 1989-04-27 1990-07-10 Advanced Micro Devices, Inc. Method and apparatus for reducing critical speed path delays
US5170160A (en) * 1989-05-09 1992-12-08 Gte Laboratories Incorporated Broadband tree switch architecture for reducing pulse width narrowing and power dissipation
EP0418417A1 (de) * 1989-09-21 1991-03-27 Siemens Aktiengesellschaft Schaltungsanordnung zur Generierung kombinatorischer binärer Logik mit Multiplexern und Invertern
US5198705A (en) * 1990-05-11 1993-03-30 Actel Corporation Logic module with configurable combinational and sequential blocks
US5055718A (en) * 1990-05-11 1991-10-08 Actel Corporation Logic module with configurable combinational and sequential blocks
US5111455A (en) * 1990-08-24 1992-05-05 Avantek, Inc. Interleaved time-division multiplexor with phase-compensated frequency doublers
US5122685A (en) * 1991-03-06 1992-06-16 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US5416367A (en) * 1991-03-06 1995-05-16 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US5130574A (en) * 1991-05-06 1992-07-14 Lattice Semiconductor Corporation Programmable logic device providing product term sharing and steering to the outputs of the programmable logic device
JP3359932B2 (ja) * 1991-05-10 2002-12-24 株式会社東芝 プログラマブル・ロジック・ユニット回路及びプログラマブル・ロジック回路
US5243599A (en) * 1991-06-05 1993-09-07 International Business Machines Corporation Tree-type multiplexers and methods for configuring the same
US5138188A (en) * 1991-07-09 1992-08-11 Intel Corporation Edge-sensitive pulse generator
FR2697703B1 (fr) * 1992-10-30 1995-01-13 Sgs Thomson Microelectronics Multiplexeur recevant en entrée une pluralité de signaux identiques mais déphasés.
GB2267613B (en) * 1992-06-02 1996-01-03 Plessey Semiconductors Ltd Programmable logic cell
US5436574A (en) * 1993-11-12 1995-07-25 Altera Corporation Universal logic module with arithmetic capabilities
USRE38451E1 (en) * 1993-11-12 2004-03-02 Altera Corporation Universal logic module with arithmetic capabilities
US5526276A (en) * 1994-04-21 1996-06-11 Quicklogic Corporation Select set-based technology mapping method and apparatus
IL109491A (en) * 1994-05-01 1999-11-30 Quick Tech Ltd Customizable logic array device
US5491431A (en) * 1994-10-05 1996-02-13 Texas Instruments Incorporated Logic module core cell for gate arrays
US5635857A (en) * 1994-12-08 1997-06-03 Unisys Corporation IC chip using a common multiplexor logic element for performing logic operations
US5751165A (en) * 1995-08-18 1998-05-12 Chip Express (Israel) Ltd. High speed customizable logic array device
US5936426A (en) 1997-02-03 1999-08-10 Actel Corporation Logic function module for field programmable array
US6822976B1 (en) * 1999-11-03 2004-11-23 Intel Corporation Method and apparatus for high throughput multiplexing of data
US6294927B1 (en) * 2000-06-16 2001-09-25 Chip Express (Israel) Ltd Configurable cell for customizable logic array device
RU2504900C1 (ru) * 2012-10-05 2014-01-20 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Ульяновский государственный технический университет" Аналоговый мультиплексор

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59107637A (ja) * 1982-12-10 1984-06-21 Matsushita Electric Ind Co Ltd 論理回路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3428903A (en) * 1965-08-02 1969-02-18 Ibm Multipurpose logic circuit for performing 254 out of 256 discrete logical combinations of three variables
US3458240A (en) * 1965-12-28 1969-07-29 Sperry Rand Corp Function generator for producing the possible boolean functions of eta independent variables
US3576984A (en) * 1968-08-09 1971-05-04 Bunker Ramo Multifunction logic network
US3619583A (en) * 1968-10-11 1971-11-09 Bell Telephone Labor Inc Multiple function programmable arrays
US4257008A (en) * 1977-11-17 1981-03-17 Scientific Circuitry, Inc. Logic circuit building block and systems constructed from same
US4556947A (en) * 1982-08-23 1985-12-03 Motorola, Inc. Bi-directional switching circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59107637A (ja) * 1982-12-10 1984-06-21 Matsushita Electric Ind Co Ltd 論理回路

Also Published As

Publication number Publication date
EP0176938B1 (de) 1990-05-23
JPS6189721A (ja) 1986-05-07
EP0176938A1 (de) 1986-04-09
ATE53152T1 (de) 1990-06-15
DE3577953D1 (de) 1990-06-28
US4825105A (en) 1989-04-25

Similar Documents

Publication Publication Date Title
JPH0428180B2 (zh)
US5920498A (en) Compression circuit of an adder circuit
US5224065A (en) Arithmetic operation unit having bit inversion function
US5299145A (en) Adder for reducing carry processing
US4709346A (en) CMOS subtractor
US5325321A (en) High speed parallel multiplication circuit having a reduced number of gate stages
EP0849663B1 (en) Conditional sum adder using pass-transistor logic
US4623872A (en) Circuit for CSD-coding of a binary number represented in two's complement
JPS584440A (ja) 演算論理装置
JPH09222991A (ja) 加算方法および加算器
US5909386A (en) Digital adder
JPH01220528A (ja) パリテイ発生器
US3824589A (en) Complementary offset binary converter
US5216424A (en) Binary data converter
KR100201030B1 (ko) 이진-선택 인코더 네트워크
JP3540136B2 (ja) データ分割並列シフタ
МАРТИНОВИЧ et al. DESIGN AND SYNTHESIS OF TERNARY LOGIC ELEMENTS
JPS61105640A (ja) 並列補数回路
SU896620A1 (ru) Устройство дл умножени по модулю
JPH08212057A (ja) 全加算器
JPH01136230A (ja) 先行1検出回路
JPH0997165A (ja) 2進化10進数の純2進数変換回路及び純2進数の2進化10進数変換回路
Razavi NMOS realization of digital circuits with digital summation threshold gates
JPS62111526A (ja) バイナリ・グレイ変換回路
JPH10161851A (ja) 丸め処理回路

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees