JPH04278536A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPH04278536A
JPH04278536A JP6379391A JP6379391A JPH04278536A JP H04278536 A JPH04278536 A JP H04278536A JP 6379391 A JP6379391 A JP 6379391A JP 6379391 A JP6379391 A JP 6379391A JP H04278536 A JPH04278536 A JP H04278536A
Authority
JP
Japan
Prior art keywords
resist
substrate
lift
entire surface
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6379391A
Other languages
Japanese (ja)
Other versions
JP2744356B2 (en
Inventor
Shigeki Hamashima
濱嶋 茂樹
Koji Hirota
廣田 耕治
Hiroyuki Tsuchida
土田 浩幸
Noritomo Satou
徳朋 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3063793A priority Critical patent/JP2744356B2/en
Publication of JPH04278536A publication Critical patent/JPH04278536A/en
Application granted granted Critical
Publication of JP2744356B2 publication Critical patent/JP2744356B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To obtain the manufacturing method of a semiconductor element capable of surely eliminating evaporation material of unnecessary parts by lift-off. CONSTITUTION:In the manufacturing method of a semiconductor element wherein a desired evaporation pattern is formed by a lift-off method using photo resist, the whole surface of a substrate 14 is coated with photo resist, and a resist pattern 28 is formed on the substrate by selective exposure and development. After desired evaporation material 30 is evaporated on the whole surface of the substrate and the whole surface is irradiated with ultraviolet rays, the resist pattern 28 is baked. After that, the resist pattern 28 is eliminated by lift-off, together with the evaporation material 30 on the resist pattern 28.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、リフトオフ法を利用し
た半導体素子の製造方法に関する。リフトオフ法は半導
体素子の電極形成等によく用いられる方法であり、蒸着
物を残したくない部分にレジストを残すように予めポジ
レジストを露光・現像した後、全面に蒸着を行う。その
後、レジストを有機溶剤で溶かしてレジスト上の蒸着物
を取り除き、蒸着物の所望のパターンを形成する方法で
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing semiconductor devices using a lift-off method. The lift-off method is a method often used for forming electrodes of semiconductor devices, and after exposing and developing a positive resist in advance so as to leave the resist in areas where no deposits are desired, the resist is deposited over the entire surface. Thereafter, the resist is dissolved with an organic solvent to remove the deposited material on the resist, thereby forming a desired pattern of the deposited material.

【0002】この種のリフトオフ法は基板上に化合物半
導体結晶を櫛歯状に貼付し、各々の化合物半導体結晶部
分から信号を取り出す多素子型赤外線検知素子を製造す
る際に、選択的に所望の蒸着物を蒸着する方法としてよ
く用いられる。
In this type of lift-off method, compound semiconductor crystals are pasted on a substrate in a comb-teeth pattern, and when manufacturing a multi-element infrared sensing element in which signals are extracted from each compound semiconductor crystal part, a desired signal is selectively applied. It is often used as a method for depositing vapor deposits.

【0003】0003

【従来の技術】ポジ型レジストを用いてリフトオフ法に
より所望の蒸着パターンを形成するには、まず基板の全
面にポジレジストを塗布した後、蒸着物を残したくない
部分にレジストを残すようにレジストをパターニング露
光し、現像することにより、露光された部分のレジスト
を除去する。
[Prior Art] To form a desired vapor deposition pattern using a positive resist by the lift-off method, first apply the positive resist to the entire surface of the substrate, and then apply the resist to the areas where you do not want to leave the vapor deposits. The exposed portions of the resist are removed by patterning exposure and development.

【0004】次いで全体に所望の蒸着を行い、有機溶剤
中に浸漬すると有機溶剤によりレジストが溶剤中に溶け
出し、レジスト上の蒸着物が取り除かれて蒸着物の所望
のパターンが形成される。
[0004] Next, a desired vapor deposition is performed on the entire surface, and when the resist is immersed in an organic solvent, the organic solvent dissolves the resist into the solvent, and the deposited material on the resist is removed to form a desired pattern of the deposited material.

【0005】[0005]

【発明が解決しようとする課題】しかし、リフトオフ法
により所望の蒸着パターンを形成する場合、蒸着物がス
テップカバレッジの良い物である場合には、蒸着物がレ
ジストの側面で切れることなく繋がってしまい、非常に
リフトオフが困難となり、蒸着パターン不良を起こすと
いう問題があった。
[Problem to be Solved by the Invention] However, when forming a desired vapor deposition pattern by the lift-off method, if the vapor deposited material has good step coverage, the vapor deposited material may be connected to the sides of the resist without being cut. However, there was a problem in that lift-off was extremely difficult and a defective vapor deposition pattern occurred.

【0006】また、ポジレジストにベーキング、露光及
び現像を施すと、その形状がエッジ部分で鈍ってしまい
、全面に蒸着物を蒸着すると、蒸着物がポジレジストの
エッジ部分で切れることなく繋がってしまい、リフトオ
フが困難になることもある。特に、蒸着物の膜厚が厚く
なるほど、この傾向は強くなる。
Furthermore, when a positive resist is subjected to baking, exposure, and development, its shape becomes dull at the edges, and when a deposit is deposited on the entire surface, the deposit is connected without being cut at the edges of the positive resist. , lift-off may be difficult. In particular, this tendency becomes stronger as the thickness of the deposit increases.

【0007】本発明はこのような点に鑑みて成されたも
のであり、その目的とするところは、リフトオフにより
確実に不要部分の蒸着物を除去できる半導体素子の製造
方法を提供することである。
The present invention has been made in view of the above points, and an object thereof is to provide a method for manufacturing a semiconductor device that can reliably remove deposits from unnecessary portions by lift-off. .

【0008】[0008]

【課題を解決するための手段】ポジレジストを用いてリ
フトオフ法により所望の蒸着パターンを形成する半導体
素子の製造方法において、基板全面にポジレジストを塗
布した後、選択的露光・現像により基板上にレジストパ
ターンを形成してから、所望の蒸着物を基板全面に蒸着
する。次いで、紫外線の全面露光をした後、レジストパ
ターンのベーキングを行い、その後該レジストパターン
をその上の蒸着物と共にリフトオフにより除去する。
[Means for Solving the Problems] In a method for manufacturing a semiconductor device in which a desired vapor deposition pattern is formed by a lift-off method using a positive resist, the positive resist is applied to the entire surface of the substrate, and then the substrate is coated by selective exposure and development. After forming a resist pattern, a desired deposition material is deposited over the entire surface of the substrate. Next, after the entire surface is exposed to ultraviolet rays, the resist pattern is baked, and then the resist pattern is removed together with the deposited material thereon by lift-off.

【0009】代案として、紫外線の全面露光ステップを
蒸着物の蒸着ステップの前に行うようにしても良い。
[0009] Alternatively, a full exposure step to ultraviolet light may be performed before the step of depositing the vapor deposit.

【0010】0010

【作用】ポジレジストに紫外線を照射することにより、
ポジレジストの重合が切断される。このように重合が切
れたポジレジストを所定温度でベーキングすると、ポジ
レジストからガスが発生し、レジスト上の蒸着物にクラ
ックが入る為、有機溶剤を使用してのリフトオフを非常
に容易に行うことができる。
[Action] By irradiating the positive resist with ultraviolet rays,
The polymerization of the positive resist is cut. When a positive resist that has been polymerized in this way is baked at a predetermined temperature, gas is generated from the positive resist and cracks appear in the deposited material on the resist, making lift-off using an organic solvent very easy. Can be done.

【0011】[0011]

【実施例】以下、本発明の製造方法を多素子型赤外線検
知素子に適用した例について説明する。
EXAMPLES An example in which the manufacturing method of the present invention is applied to a multi-element type infrared sensing element will be described below.

【0012】図1は多素子型赤外線検知素子10の概略
斜視図を示しており、サファイア基板12上にはHgC
dTe等の化合物半導体結晶14が櫛歯状に接着剤によ
り接着されている。
FIG. 1 shows a schematic perspective view of a multi-element type infrared sensing element 10, in which HgC is formed on a sapphire substrate 12.
A compound semiconductor crystal 14 such as dTe is bonded with an adhesive in a comb-like shape.

【0013】凸状に形成された各々の化合物半導体結晶
14には一対の遮光膜18により赤外線を受光する受光
部16が画成されており、反射防止膜20が遮光膜18
の下を通り受光部16に渡り伸長して形成されている。 遮光膜18は例えばアルミニウム等から形成され、反射
防止膜20はZnS等から形成される。
A light receiving portion 16 for receiving infrared rays is defined in each compound semiconductor crystal 14 formed in a convex shape by a pair of light shielding films 18 , and an antireflection film 20 is defined by a pair of light shielding films 18 .
The light receiving section 16 is formed so as to extend through the bottom of the light receiving section 16 . The light shielding film 18 is made of aluminum or the like, and the antireflection film 20 is made of ZnS or the like.

【0014】各々の化合物半導体結晶14の一端にはワ
イヤボンディングにより信号を取り出す個別電極22が
それぞれ設けられており、他端にはアースに接続される
共通アース電極24が設けられている。
[0014] At one end of each compound semiconductor crystal 14, an individual electrode 22 for extracting a signal is provided by wire bonding, and at the other end, a common ground electrode 24 is provided to be connected to ground.

【0015】このような構造を有する多素子型赤外線検
知素子10を製造するにあたり、凸形状の各々の化合物
半導体結晶14上に電極、反射防止膜または遮光膜を以
下に説明するリフトオフ法により形成する。
In manufacturing the multi-element infrared sensing element 10 having such a structure, an electrode, an antireflection film, or a light shielding film is formed on each convex compound semiconductor crystal 14 by the lift-off method described below. .

【0016】本発明の製造プロセスを赤外線検知素子の
製造に適用した例を図2を用いて説明する。
An example in which the manufacturing process of the present invention is applied to manufacturing an infrared sensing element will be described with reference to FIG.

【0017】HgCdTe等の化合物半導体結晶14上
にポジレジストを全面に塗布した後、70〜80℃で約
10分間ベーキングを行う。次いで、マスクを使用して
ポジレジストを選択的に露光し、現像を行うと、図2(
a)に示すように化合物半導体結晶14上にレジストパ
ターン28が形成される。
After applying a positive resist to the entire surface of the compound semiconductor crystal 14 such as HgCdTe, baking is performed at 70 to 80° C. for about 10 minutes. Next, the positive resist is selectively exposed using a mask and developed, resulting in the image shown in Figure 2 (
As shown in a), a resist pattern 28 is formed on the compound semiconductor crystal 14.

【0018】次いで、図2(b)に示すように、全面に
蒸着物30を一様に蒸着する。蒸着物30は紫外線を透
過する物質であり、例えば、ZnS、SiO2 等の絶
縁物又は非常に薄いNi、Cr等が用いられる。
Next, as shown in FIG. 2(b), a deposit 30 is uniformly deposited over the entire surface. The deposit 30 is a substance that transmits ultraviolet rays, and for example, an insulating material such as ZnS or SiO2 or very thin Ni or Cr is used.

【0019】次いで、図2(c)に示すように、紫外線
の全面露光を行う。これにより、紫外線が蒸着物30を
透過してポジレジスト28の重合を切断する。
Next, as shown in FIG. 2(c), the entire surface is exposed to ultraviolet light. As a result, the ultraviolet rays pass through the deposit 30 and cut the polymerization of the positive resist 28.

【0020】このように重合が切られたポジレジスト2
8を70〜80℃で約10分間ベーキングを行うと、図
2(d)に示すようにレジスト28中に気泡32が発生
する。この気泡32によりレジスト28が膨張して、レ
ジスト28上の蒸着物30にクラック31が入る。
[0020]Positive resist 2 whose polymerization has been cut in this way
When resist 28 is baked at 70 to 80° C. for about 10 minutes, bubbles 32 are generated in resist 28 as shown in FIG. 2(d). The resist 28 expands due to the bubbles 32, and cracks 31 appear in the deposit 30 on the resist 28.

【0021】次いで、図2(e)に示すようにアセトン
等の剥離液中に浸漬すると、剥離液がクラック31を通
してレジスト28内に容易に染み込むことができ、その
結果レジストがその上の蒸着物とともに剥離され、図2
(f)に示すような蒸着パターン30を得ることができ
る。
Next, as shown in FIG. 2(e), when immersed in a stripping solution such as acetone, the stripping solution can easily penetrate into the resist 28 through the cracks 31, and as a result, the resist is immersed in the deposited material thereon. Figure 2
A vapor deposition pattern 30 as shown in (f) can be obtained.

【0022】上述した実施例では、ステップ(b)の蒸
着の後に紫外線露光ステップを行っているが、ステップ
(b)とステップ(c)とを逆にして、紫外線露光をし
てから蒸着ステップを行うようにしても良い。
In the above embodiment, the ultraviolet exposure step is performed after the vapor deposition in step (b), but steps (b) and (c) are reversed, and the vapor deposition step is performed after the ultraviolet exposure. You can do it as well.

【0023】また本発明は、化合物半導体結晶上に蒸着
パターンを形成する場合だけでなく、サファイア、シリ
コン基板上等に蒸着パターンを形成する場合にも利用可
能である。
Furthermore, the present invention can be used not only when forming a vapor deposition pattern on a compound semiconductor crystal, but also when forming a vapor deposition pattern on a sapphire or silicon substrate.

【0024】特に基板が紫外線に対して透明な場合には
、基板の裏面から紫外線の全面露光を行うことができ、
この場合には蒸着物として紫外線を透過しない物質も採
用可能である。
In particular, when the substrate is transparent to ultraviolet rays, the entire surface of the substrate can be exposed to ultraviolet rays from the back side.
In this case, a substance that does not transmit ultraviolet rays can also be used as the deposit.

【0025】[0025]

【発明の効果】本発明は以上詳述したように構成したの
で、リフトオフにより確実に不要部分の蒸着物を除去で
きるという効果を奏する。
Since the present invention is constructed as described in detail above, it is possible to reliably remove deposits from unnecessary portions by lift-off.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】赤外線検知素子の概略斜視図である。FIG. 1 is a schematic perspective view of an infrared sensing element.

【図2】本発明実施例の製造プロセスを示す図である。FIG. 2 is a diagram showing a manufacturing process of an example of the present invention.

【符号の説明】[Explanation of symbols]

10  多素子型赤外線検知素子 12  サファイア基板 14  化合物半導体結晶 16  受光部 22  個別電極 24  共通電極 28  ポジレジスト 30  蒸着物 31  クラック 32  気泡 10 Multi-element infrared sensing element 12 Sapphire substrate 14 Compound semiconductor crystal 16 Light receiving part 22 Individual electrode 24 Common electrode 28 Positive resist 30 Vapor deposits 31 Crack 32 Bubbles

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】  ポジレジストを用いてリフトオフ法に
より所望の蒸着パターンを形成する半導体素子の製造方
法において、基板(14)全面にポジレジストを塗布し
た後、選択的露光・現像により基板上にレジストパター
ン(28)を形成し、所望の蒸着物(30)を基板全面
に蒸着し、紫外線の全面露光をした後、前記レジストパ
ターン(28)のベーキングを行い、その後該レジスト
パターン(28)をその上の蒸着物(30)と共にリフ
トオフにより除去することを特徴とする半導体素子の製
造方法。
1. A method for manufacturing a semiconductor device in which a desired vapor deposition pattern is formed by a lift-off method using a positive resist, in which a positive resist is applied to the entire surface of a substrate (14), and then the resist is deposited on the substrate by selective exposure and development. After forming a pattern (28) and depositing a desired vapor deposit (30) on the entire surface of the substrate and exposing the entire surface to ultraviolet rays, the resist pattern (28) is baked, and then the resist pattern (28) is A method for manufacturing a semiconductor device, characterized in that it is removed together with the upper deposit (30) by lift-off.
【請求項2】  前記紫外線の全面露光ステップを蒸着
物(30)の蒸着ステップの前に行うことを特徴とする
請求項1記載の半導体素子の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of exposing the entire surface to ultraviolet rays is performed before the step of depositing the vapor deposit (30).
【請求項3】  前記基板(14)が紫外線透過基板で
あり、前記紫外線の全面露光を該基板の裏面より行うこ
とを特徴とする請求項1又は2記載の半導体素子の製造
方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate (14) is an ultraviolet-transmissive substrate, and the entire surface of the substrate is exposed to the ultraviolet rays from the back side of the substrate.
JP3063793A 1991-03-06 1991-03-06 Method for manufacturing semiconductor device Expired - Lifetime JP2744356B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3063793A JP2744356B2 (en) 1991-03-06 1991-03-06 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3063793A JP2744356B2 (en) 1991-03-06 1991-03-06 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH04278536A true JPH04278536A (en) 1992-10-05
JP2744356B2 JP2744356B2 (en) 1998-04-28

Family

ID=13239612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3063793A Expired - Lifetime JP2744356B2 (en) 1991-03-06 1991-03-06 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2744356B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5570028A (en) * 1978-11-20 1980-05-27 Matsushita Electric Ind Co Ltd Fabricating method of semiconductor device
JPS5831528A (en) * 1981-08-19 1983-02-24 Nec Corp Removing method of photoresist

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5570028A (en) * 1978-11-20 1980-05-27 Matsushita Electric Ind Co Ltd Fabricating method of semiconductor device
JPS5831528A (en) * 1981-08-19 1983-02-24 Nec Corp Removing method of photoresist

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Publication number Publication date
JP2744356B2 (en) 1998-04-28

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