JPH04273361A - Transmission line controller - Google Patents

Abstract

PURPOSE:To reduce the dullness of a waveform. CONSTITUTION:A using request signal for a transmission line is outputted to a transmission line controller 301 from an instruction processor 302 serving as a bus master device or an input/output instruction processor 303 containing both bus master and slave functions. The controller 301 arbitrates the received using request signal and then outputs an arbitrating signal to the immediately preceding arbitrating signal after confirming a fact that an answer signal is received from a partner device. In this case, a main storage device 304 serving as a bus slave device, a graphic processor 305 or an input/output instruction processor 303 sets an output buffer connected to the bus slave device to which a signal is outputted in an output state with the read/write instruction signal inputted from the processor 302. At the same time, the output buffer connected to the bus slave device to which no signal is outputted is set in an Hi-Z state respectively.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission line control device connected to a plurality of devices.

0002

[Prior Art] Conventionally, this type of transmission line control device is shown in FIG.
As shown in FIG. 2, there is a bus 407 as a transmission path, a bus arbitration circuit 406, and a 3-state buffer 401, and an instruction processing device 402 or an input/output instruction processing device 403, which is a bus master device, is connected to the bus arbitration circuit 406 to use the bus. was making a request. Then, only the devices permitted to use the bus output "0" and "1" through the 3-state buffer 401. The main memory device 404 or graphic processing device 405, which is a bus slave device that only inputs/outputs data and inputs addresses through a transmission line based on the use of other bus master devices or bus master devices, keeps the 3-state buffer 401 in a high state. Impedance (hereinafter H
(written as i-Z).

0003

SUMMARY OF THE INVENTION The conventional transmission line control device described above has the problem that the total line length is long, so the load capacity becomes large and the waveform becomes dull.

0004

[Means for Solving the Problems] A transmission line control device of the present invention includes data connection means for connecting data paths between a plurality of bus master devices and a plurality of bus slave devices; an address connection means for connecting an address route with a device; an arbitration means for receiving and arbitrating a request to use the data connection means and the address connection means from the plurality of bus master devices; data input selection means for selecting a data path for inputting data; and data output selection means for selecting a data path for outputting the data input by the data input selection means from the data connection means by permission of use of the arbitration circuit; address input selection means for selecting an address route for inputting the address of the data to the address connection means upon permission to use the arbitration circuit; and an address for outputting the address input by the address input selection means upon permission to use the arbitration circuit; and address output selection means for selecting a route.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained with reference to the drawings. FIG. 3 is a block diagram of one embodiment of the present invention. This embodiment includes an instruction processing device 302 that is a bus master device, a main storage device 304 and a graphic processing device 305 that are bus slave devices, an input/output instruction processing device 303 that has both bus master and bus slave functions, and a transmission A transmission line control device 301 (301a or 3
01b).

FIG. 1 is a block diagram of a first embodiment of the transmission line control device in FIG. 3, and FIG. 4 shows data output from each device,
FIG. 3 is an explanatory diagram showing the correspondence between addresses and signal names. The transmission path control device 301a transmits a use request signal REQa or REQb and a response signal REPb or REPc or REPd to an LSI 200 that is composed of a data transmission unit block 4 for transmitting data and an address transmission unit block 9 for transmitting addresses. Arbitration circuit 1a which inputs and outputs arbitration signal ACKa or ACKb, and arbitration signal AC
By inputting Ka or ACKb and inputting destination signal FTb, FTc or FTd, the LSI
The LSI 20 is controlled by a selection control circuit 2a that selects 200 data transmission paths, an input of an arbitration signal ACKa or ACKb, and an input of a read/write command signal RWa or RWb.
and an output control circuit 3a that controls the output path of 0. The data transmission unit block 4 indicates a 1-bit wide data transmission path, and there are 8 bits in the LSI 200. Similarly, the address transmission unit block 9 also represents a 1-bit width address transmission path, and there are 8 bits in the LSI 200.

[0007] Next, the instruction processing device 302
The operation of this embodiment when writing data to 04 will be explained. Here, bit 0 is explained for both data and address, but bits 1 to 7 are also controlled in the same way. The command processing device 302 outputs the use request signal REQa to the arbitration circuit 1a of the transmission path control device 301a. After arbitration, the arbitration circuit 1a confirms that a response signal REPb, REPc, or REPd has come from the partner device in response to the previous arbitration signal ACKa or ACKb, and outputs an arbitration signal ACKa. The arbitration signal ACKa becomes "1", and the read/write command signal R at that time
Since Wa is "1", the output control circuit 3a sets the output buffer 53a for the instruction processing device 302 to Hi-Z, and also sets the output buffer 63a for the main storage device 304 to the output state.

Next, by inputting the arbitration signal ACKa and the destination signal FTc to the selection control circuit 2a, the control signal is sent to the main storage device 30 of the data connection section 45.
It is output to the data write register selector 61a for 4. As a result, the data write register selector 61a
selects data path AD0a to which data AD0 from instruction processing device 302 is input. Therefore, data AD0 is output from output buffer 63a to main memory 304 via data path CD0a for main memory 304.

Furthermore, by outputting a control signal from the selection control circuit 2a, the main storage device 30 of the address connection section 46
The address selector 91a for 4 is the instruction processing device 302.
Main storage device 30 to which address AA0 from
Select address route AA0a for 4. Address AA
0 is the address output buffer 96 for the main storage device 304
a to the main storage device 304 via the address path CA0a for the main storage device 304. Thereafter, a response signal REPc from the main memory device 304 which is a bus slave
The instruction processing device 302 then ends the write operation.

Next, the operation of this embodiment when the input/output instruction processing device 303 reads data from the graphic processing device 305 will be explained. Input/output instruction processing device 30
3 outputs the use request signal REQb to the arbitration circuit 1a. After arbitration, the arbitration circuit 1a responds to the previous arbitration signal ACKa or ACKb with a response signal REPb or REPc.
Alternatively, after confirming that REPd has arrived, the arbitration signal ACKb is output. Since the arbitration signal ACKb is "1" and the read/write command signal RWb is "0" at that time, the output control circuit 3a is activated by the input/output command processing device 303.
The output buffer 73a for the graphic processing device 305 is set to the output state, and the output buffer 83a for the graphic processing device 305 is set to Hi-Z. The selection control circuit 2a inputs the arbitration signal ACKb and the destination signal FTd to the data connection section 45.
The master/slave selector 77a for the input/output instruction processing device 303 and the data output selector 78a for the input/output instruction processing device 303 process input data DD0 from the data path DD0a for the graphic processing device 305 for input/output instruction processing. It controls output to the data path BD0a for the device 303. In response to the response signal REPd from the graphic processing device 305, the input/output command processing device 303 takes in data from the graphic processing device 305.

Similarly, the selection control circuit 2a causes the address selector 92a for the graphic processing device 305 of the address connection unit 46 to select the address path BA0a to which the address BA0 from the input/output instruction processing device 303 is input. Control. The address BA0 is output from the address output buffer 97a for the graphics processing device 305 to the graphics processing device 305 via the address path DA0a for the graphics processing device 305.

FIG. 2 is a block diagram of a second embodiment of the information processing system of FIG. Transmission line control device 30
1b is an LSI 201 composed of a data transmission unit block 41 and an address transmission unit block 42, an arbitration circuit 1b, a selection control circuit 2b that selects a data transmission route of the LSI 201, and an output control circuit that controls the output route of the LSI 201. It is composed of a circuit 3b. LSI20
A data transmission unit block 41 within LSI 201 indicates a data transmission path with a width of 1 bit, and there are 8 bits in the LSI 201 . Similarly, the address transmission unit block 42 also represents a 1-bit width address transmission path, and there are 8 bits in the LSI 201.

Next, the instruction processing device 302 stores the main storage device 3.
The operation when writing data to 04 will be explained using FIGS. 2 and 3 and FIG. 5 which is a time chart. Here, bit 0 will be explained for both data and address, but bits 1 to 7 are controlled in the same way. The instruction processing device 302 outputs the use request signal REQa to the arbitration circuit 1b. After arbitration, the arbitration circuit 1b confirms that a response signal REPb, REPc, or REPd has come from the partner device in response to the previous arbitration signal ACKa or ACKb, and outputs an arbitration signal ACKa. Since the arbitration signal ACKa becomes "1" and the read/write command signal RWa at that time is "1", the output control circuit 3b sets the output buffer 53b for the instruction processing device 302 to H.
i-Z and also puts the output buffer 63b for the main storage device 304 into the output state.

Next, by inputting the arbitration signal ACKa and the destination signal FTc to the selection control circuit 2b, the control signal is sent to the main storage device 30 of the data connection section 47.
It is output to the data write register selector 61b for 4. As a result, the data write register selector 61b
selects the data path AD0b to which data AD0 from the instruction processing device 302 is input. Therefore, data AD0 is set in data write register 64, and at the same time, flip-flop (hereinafter referred to as F/F) 66 is also set to
1”.

Furthermore, by outputting a control signal from the selection control circuit 2b, the main storage device 30 of the address connection section 48
The address selector 91b for 4 is the instruction processing device 302.
Main storage device 30 to which address AA0 from
Select address route AA0b for 4. Address AA
0 is set in the address register 100 for the main memory device 304, and the address path CA0 for the main memory device 304 is set from the address output buffer 96b for the main memory device 304.
It is output to the main storage device 304 via b. Thereafter, the F/F 66 is reset by the response signal REPc from the main memory device 304, and the next write to the data write register 64 becomes possible.

Next, the operation when the input/output command processing device 303 reads data from the graphic processing device 305 will be explained using FIGS. 2 and 3 and the time chart of FIG. 6. The input/output command processing device 303 outputs the use request signal REQb to the arbitration circuit 1b. Arbitration circuit 1
b is the immediately preceding arbitration signal ACKa or ACKb after arbitration.
response signal REPb or REPc or REP
After confirming that d has arrived, it outputs an arbitration signal ACKb. Since the arbitration signal ACKb becomes "1" and the reading/writing command signal RWb at that time is "0", the output control circuit 3b puts the output buffer 73b for the input/output command processing device 303 into the output state, and changes the output buffer 73b for the graphic processing device 305 to the output state. output buffer 83b is set to Hi-Z. Selection control circuit 2
b is the arbitration signal ACKb and the destination signal F
Td, the master/slave selector 77b for the input/output command processing device 303 of the data connection unit 47 and the data output selector 78b for the input/output command processing device 303,
The input data DD0 from the data path DD0b for the graphic processing device 305 is controlled to be output to the data path BD0b for the input/output command processing device 303. Then, the data read register 85 receives data from the graphic processing device 3.
The data from 05 is set every clock.

Similarly, the selection control circuit 2b causes the address selector 92b for the graphic processing device 305 of the address connection section 48 to select the address path BA0b to which the address BA0 from the input/output instruction processing device 303 is input. to control. Address BA0 is set in the address register 101 for the graphics processing device 305, and is sent from the address output buffer 97b for the graphics processing device 305 to the graphics processing device 305 via the address path DA0b for the graphics processing device 305.
is output to.

When data is not set in the data read register every clock, the graphic processing unit 305
Data from the graphic processing device 305 is set in the data read register 85 in response to a response signal REPd from the graphics processing device 305 .

[0019] Since each LSI 200 and 201 can control 8-bit data and address, 16, 32
Two or four bits can also be used for bit data and addresses.

Furthermore, since the LSIs 200 and 201 do not have an internal arbitration circuit, the arbitration circuit 1 is connected to the LSIs 200 and 201 regardless of the number of LSIs 200 and 201 used.
It suffices to have one outside the .

[0021]

[Effects of the Invention] As explained above, the present invention has a built-in transmission line and connects a plurality of devices one-to-one with the transmission line to shorten the transmission line, thereby reducing waveform distortion. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the invention.

FIG. 2 is a block diagram of a second embodiment of the invention.

FIG. 3 is a block diagram of an embodiment of an information processing system using the present invention.

FIG. 4 is an explanatory diagram showing the correspondence between data, addresses, and signal names output from each device.

FIG. 5 is a diagram showing a time chart of a write operation from an instruction processing device to a main storage device according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a time chart of a read operation from the input/output instruction processing device to the graphics processing device according to the second embodiment of the present invention.

FIG. 7 is a block diagram of a conventional example.

[Explanation of symbols]

1a, 1b Arbitration circuits 2a, 2b Selection control circuits 3a, 3b Output control circuits 4, 41 Data transmission unit blocks 9, 42
Address transmission unit blocks 45, 47 Data connection parts 46, 48 Address connection parts 53a, 53b Output buffers 61a, 61b Data write register selectors 63a, 63b Output buffer 64 Data write register 66 F/F 73a, 73b Output buffers 77a, 77b Master /slave selector 78
a, 78b Data output selector 83a, 83b
Output buffer 85 Data read register 91a, 91b, 92a, 92b Address selector 96a, 96b, 97a, 97b Address output buffer 100, 101 Address register 200, 20
1 LSI 301a, 301b Transmission line control device 302
Instruction processing device 303 Input/output instruction processing device 304 Main storage device 305 Graphic processing device AA0a, AA0b Address path AD0a, A
D0b Data path BD0a, BD0b
Data route BA0a, BA0b Address route C
A0a, CA0b Address route CD0a
data path

Claims (3)

[Claims] 1. Data connection means for connecting data paths between a plurality of bus master devices and a plurality of bus slave devices; address connection means for connecting address paths between the plurality of bus master devices and a plurality of bus slave devices; arbitration means that receives and arbitrates requests for use of the data connection means and address connection means of the plurality of bus master devices; and data input selection means that selects a data path for inputting data to the data connection means based on permission to use the arbitration means. data output selection means for selecting a data path for outputting the data inputted by the data input selection means from the data connection means upon permission to use the arbitration means; Address input selection means for selecting an address route for inputting the address of data; and address output selection means for selecting an address route for outputting the address input by the address input selection means upon permission of use of the arbitration means. Characteristic transmission line control device. 2. The transmission line control device according to claim 1, wherein the data connection means includes a data read register that temporarily holds data. 3. When the bus master device performs a read operation, data is set in the data read register corresponding to the bus slave device designated by the bus master device every clock. Transmission line control device.