JP2003050775A - Data transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer device and its method, by which a large capacity FIFO buffer is secured fully. SOLUTION: In the data transfer device including an external memory 150, the external memory 150 is controlled as the FIFO buffer. When write from a local bus to a host bus is conducted, a first selector 137 selects an address of a FIFO pointer and stores the address and data in the FIFO buffer of the external memory 150. When the data transfer device issues a bus request to the host bus and acquires bus use right, the address and data are taken out from the FIFO buffer of the external memory 150 and written in a device on the host bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device. In particular, the present invention relates to a data transfer device capable of efficiently writing a large amount of data from an I / O device on a local bus to a memory on a host bus.

[0002]

2. Description of the Related Art Conventionally, in many data transfer devices for transferring data from a local bus to a host bus, a FIFO buffer is built in the data transfer device. Hereinafter, a conventional data transfer device will be described in detail with reference to the drawings.

FIG. 7 is a schematic block diagram showing the concept of a conventional data transfer device. In FIG. 7, 1 indicates a host bus and 2 indicates a local bus, each of which is composed of an address bus, a data bus, and a control line.

Reference numeral 3 is a CPU on the host bus, 4 is a memory on the host bus, and 5 is an I / O device on the local bus.

Next, 6 is a data transfer device main body, and 7
Indicates an arbiter in the data transfer device 6, 8 indicates a secondary bus master on the local bus, and 9 indicates a secondary bus target on the local bus.

A FIFO controller 10 controls the address storing FIFO buffer 11 and the data storing FIFO buffer 12.

Further, 13 is a primary bus target on the host bus, and 14 is a primary bus master on the host bus.

First, the write operation from the I / O device 5 to the memory 4 will be described. First, a write cycle from the I / O device 5 to the data transfer device 6 occurs on the local bus 2. At this time, when the I / O device 5 requests the right to use the local bus 2 from the arbiter 7, and the arbiter 7 passes the right to use the local bus 2 to the I / O device 5,
A write cycle from the I / O device 5 to the data transfer device 6 will occur.

Next, the data transfer device 6 internally latches the address and data as a target of this write cycle, and generates a write cycle to the memory 4 on the host bus 1.

At this time, first, the secondary bus target 9 controls the FIFO controller 10 to latch the address and data on the local bus 2 in the address storing buffer 11 and the data storing buffer 12, respectively.

Next, on the host bus 1, the primary bus master 13 requests the CPU 3 for bus arbitration to generate a write cycle to the memory 4, and the address latched in the address storage buffer 11 and the data The address latched in the storage buffer 12 will be driven.

[0012]

Generally, in a data transfer device, the bus arbitration number decreases as the capacity of the FIFO buffer for transferring data from the local bus to the host bus increases. It is believed to be more efficient.

However, in the conventional data transfer device, since the FIFO buffer is built in the LSI, it is necessary to increase the chip area itself, so that a large capacity is imposed due to physical restrictions. FI
There is a problem that the FO buffer cannot be built in and the bus usage efficiency cannot be improved sufficiently.

In order to solve the above problems, the present invention provides
An object of the present invention is to provide a data transfer device capable of securing a sufficiently large capacity FIFO buffer.

[0015]

To achieve the above object, a data transfer device according to the present invention is a data transfer device for transferring data from a first bus to a second bus,
A memory control unit that controls an external memory as a first-in first-out (FIFO) buffer is provided, and when the memory control unit writes from the first bus to the second bus, the address and data are stored. It is characterized by being temporarily stored in an external memory.

With such a structure, a sufficiently large capacity can be secured as a FIFO buffer, so that the number of bus arbitrations is reduced and the bus usage efficiency is improved.

Further, the data transfer apparatus according to the present invention is
In the memory control unit, the first address group for the mapped memory area and the second address group for the memory area used as the FIFO buffer are arranged in the address space, and the first address group and the second address group are arranged. Are preferably distinguished by the state of a particular bit. This is because it can be easily used properly only by bit control.

The data transfer apparatus according to the present invention is
In the memory control unit, it is preferable that the mapped memory area address and the memory area address used as the FIFO buffer are alternately arranged in the real address space. This is because when the memory is expanded, both the memory area address and the FIFO buffer address can be secured in the expanded area.

The data transfer apparatus according to the present invention is
In the memory control unit, it is preferable that the specific bit that distinguishes the first address group and the second address group is a specific bit of an address line that a plurality of external memories having different capacities have in common. This is because the capacity can be easily changed.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION A data transfer apparatus according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a data transfer device according to an embodiment of the present invention.

In FIG. 1, reference numeral 130 is a main body of the data transfer device, 100 is a CPU, and 110 is a memory, respectively, and the data transfer device 1 via the host bus 160.
It is connected to 30. Reference numeral 120 denotes an I / O device, which is connected to the data transfer device 130 via a local bus 170. In addition, both the host bus 160 and the local bus 170 have an address bus, a data bus,
And a control line.

The present embodiment is characterized in that the external memory 150 of the data transfer device 130 is arranged. Therefore, the components are different from the conventional data transfer device as follows.

First, 131 is an arbiter of the local bus 170, 132 is a secondary bus master of the local bus 170, and 133 is a secondary bus target of the local bus 170. Also, 13
Reference numeral 4 is an address decoder of the local bus 170.

Further, 135 is a FIFO data controller, 136 is a FIFO pointer controller, 138 is an address buffer, and 139 is an address buffer.
Indicates a data buffer, respectively. A first selector 137 and a second selector 140 are arranged to control the input to the memory buffer 143.

Further, 141 is a FIFO buffer for address storage from the local bus 170 to the host bus 160, and 142 is a local bus 170 to the host bus 160.
FIFO buffers for storing data in the memory are shown respectively.

Further, 143 is a memory buffer of the external memory 150, 144 is an address decoder of the host bus 160, 145 is a primary bus target of the host bus 160, and 146 is a primary bus master of the host bus 160. There is.

In the data transfer device 130, the arbiter 131 first arbitrates the local bus 170. In addition, the memory controller 147 includes the secondary bus master 132 and the secondary bus target 13.
3, the primary bus target 145, and the primary bus master 146.

The FIFO data controller 135 controls the memory controller 147 to store the memory 150 in the FIFO.
It will be controlled as an O buffer.

When writing from the I / O device 120 to a device on the host bus 160, the memory controller 147 controls the FIFO data controller 135 to use the external memory 150 as a FIFO buffer.

The first selector 137 receives the FIFO pointer controller 136 and the address buffer 138, and outputs it to the memory buffer 143. When the result decoded by the address decoder 134 is written in the memory 110 on the host bus 160,
When the value of the FIFO pointer controller 136 is written in the mapped memory area on the external memory 150, the value of the address buffer 138 is output by distinguishing each specific bit value.

Similarly, the second selector 140 receives the address buffer 138 and the data buffer 139, and outputs it to the memory buffer 143. The result decoded by the address decoder 134 is sent to the host bus 1
In the case of writing to the memory 110 on the memory 60, the value of the address buffer 138 is set in the address area of the FIFO buffer area, and the value of the data buffer 1 is set in the data area.
When writing the value of 39 to the mapped memory area on the external memory 150, the value of the data buffer 139 is output.

Next, regarding the flow of processing for writing from the local bus 170 to the host bus 160,
A detailed description will be given with reference to the drawings. FIG. 2 is a flow chart of a process of writing from the local bus 170 to the host bus 160.

In FIG. 2, first, the data transfer device 130.
Access to the data transfer device 130 (step 201: Yes), an address decoding process is performed (step 202).

Based on the result of the address decoding process,
It is determined whether the writing is to the memory 110 on the host bus 160 or the mapped memory in the external memory 150 (step 203).

If the write is to the memory 110 on the host bus 160 (step 203: Yes), whether the secondary bus master 132 of the local bus 170 has acquired the right to use the memory controller 147 in the data transfer device 130. It is determined (step 20)
4).

When the secondary bus master 132 has the right to use the memory controller 147 (step 204: Yes), the first selector 137 selects the FIFO pointer controller 136 (step 20).
5). Similarly, the second selector 140 selects the address buffer 138 (step 206).

Then, the address value of the target is transferred to the external memory 150 (step 207), and the FIFO pointer controller 136 increments the write pointer (step 208).

Next, while the first selector 137 selects the FIFO pointer controller 136 (step 209), the second selector 140 causes the data buffer 1 to operate.
After selecting 39 (step 210), the target data value is transferred to the external memory 150 (step 21).
1), the FIFO pointer controller 136 increments the write pointer (step 212).

Then, a bus request is made to the host bus 160 in the data transfer device 130 (step 21).
3) It is determined whether the right to use the host bus 160 has been acquired (step 214).

If the right to use the host bus 160 has been acquired (step 214: Yes), the host bus 1
The 60 primary bus master 146 requests the right to use the memory controller 147 (step 215), and determines whether or not the right to use the memory controller 147 has been acquired (step 216).

When the usage right of the memory controller 147 has been acquired (step 216: Yes), the memory 1
The address value of the target is transferred from the point point of the FIFO pointer controller 136 on the 50 to the memory buffer 143 (step 217), and the FIFO pointer controller 136 increments the read pointer (step 218).

Then, the data value of the target is transferred from the point of the FIFO pointer controller 136 on the memory 150 to the memory buffer 143 (step 21).
9), the FIFO pointer controller 136 increments the read pointer (step 220).

Finally, the data transfer device 130 refers to the memory buffer 143 and writes the target data to the target address temporarily stored in the memory buffer 143 (step 221).

On the other hand, if the writing was to the mapped memory in the external memory 150 (step 20)
3: No), it is determined whether or not the secondary bus master 132 of the local bus 170 has acquired the right to use the memory controller 147 in the data transfer device 130 (step 223).

When the secondary bus master 132 has the right to use the memory controller 147 (step 223: Yes), the first selector 137 selects the address buffer 138 (step 224). Similarly,
The second selector 140 selects the data buffer 139 (step 225).

Then, the target address value and data value are directly transferred to the external memory 150 (step 226).

Next, the FIFO pointer controller 13
6 will be described in detail with reference to FIG. Figure 3
FIG. 3 is a configuration diagram of a FIFO pointer controller 136 in the data transfer device according to the exemplary embodiment of the present invention.

In FIG. 3, reference numeral 300 is a FIFO counter, 301 is a selector, 302 is a 15-bit counter, and 303 is a circuit for controlling the output of the FIFO counter 300 from the output of the selector 301 and the output from the 15-bit counter 302. , 304 are circuits for controlling the memory address from the output of the FIFO counter 300 and the FIFO address signal, respectively.

In addition, S301 is an address / data switching signal, S302 is a write counter control signal, S303 is a FIFO address signal, S304 is an output signal of the selector 301, and S305 is an output signal from the 15-bit counter 302. S306 shows the output signals from the FIFO counter 300, respectively.

Further, S307 shows the output from the memory address control circuit 304, that is, the 17-bit memory address itself, and S308 shows the read counter control signal.

First, the selector 301 outputs "0" when an address is input to the FIFO from the input of the address / data switching signal S301, and outputs "1" when data is input.

Further, the control circuit 303 outputs the output S305 from the 15-bit counter to the output S3 from the selector 301.
04 is given. Similarly, the control circuit 304 outputs the FIFO address signal S30 to the output 306 from the control circuit 303.
Give 3. In the present embodiment, the FIFO address signal is "1" and the mapped memory address signal is "0".

Next, the write operation from the I / O device 120 arranged on the local bus 170 to the memory 110 arranged on the host bus 160 will be concretely described using data examples.

Here, it is assumed that the address 5000 is assigned to the memory 110 arranged on the host bus 160, and the data abcd is written from the I / O device 120 to the address 5000 at this time.

First, when it is determined that the address 5000 is assigned to the memory 110 on the host bus 160 as a result of being decoded by the address decoder 134, the address value '5000' is set to the address buffer 1
38, and the data value'abcd 'will be stored in the data buffer 139.

Next, the bus master 132 on the local bus
Waits until the right to use the external memory 150 is acquired, and when the right to use the external memory 150 is acquired, the first selector 137 selects the FIFO pointer controller 136.

FIFO pointer controller 1 at this time
The value of 36 is the output of the 15-bit counter 302 '000000
To the 000000000 ', the circuit 303 adds'1' indicating the address to the third bit to become '0000000000000100', and the circuit 304 adds' 1 'indicating the FIFO buffer area to the second bit to' 000000000000000010 '.
Becomes

Similarly, the second selector 140 selects the address buffer 138, and the target address value '50.
00 'is stored in the memory 150 as'000000000000000010'
Transfer to the address and increment the counter in the FIFO pointer controller 136 to '00000000000000011
Set to 0 '.

Subsequently, the first selector 137 causes the FIFO
When the pointer controller 136 is selected and the second selector 140 selects the data buffer 139, the target data value'abcd 'is transferred to the address'000000000000000110' of the external memory 150 and the counter in the FIFO pointer controller 136 is selected. Is incremented to be “000000000000001010”.

When the right to use the host bus 160 is obtained, the primary bus master 1 in the host bus 160
46 requests the right to use the external memory 150, and when the right to use the external memory 150 can be obtained, FI
The address of 5000, which is the target address, is transferred to the memory buffer 143 by referring to the read pointer of the FO pointer controller 136, and the read pointer of the FIFO pointer controller 136 is incremented.

Then, the FIFO pointer controller 1
The target pointer'abcd 'is transferred to the memory buffer 143 by referring to the read pointer of 36, and F
The read pointer of the IFO is incremented, and the primary bus master 146 on the host bus 160 in the data transfer device 130 writes the value of the memory buffer 143.

Next, the FIFO pointer controller 13
The pointer 6 will be described with reference to FIG. FIG. 4 is an exemplary diagram of pointers output from the FIFO pointer controller 136 in the data transfer apparatus according to the embodiment of the present invention.

In the example of FIG. 4, the second bit of the pointer output from the FIFO pointer controller 136 is always "1". On the other hand, as the address used as the mapped memory, the second bit is "0".
If you use the area marked as, the external memory 1
In 50, as shown in FIG. 5, the area used as the mapped memory and the area used as the FIFO buffer are physically arranged alternately.

In FIG. 5, the shaded area indicates the mapped memory area, and the white area indicates the memory area for the FIFO buffer. In the FIFO read pointer and the write pointer, the second bit is always (1) as shown in FIG. When the 128-megabit memory 610 is changed to the 512-megabit memory 620, both the memory area address and the FIFO buffer address are secured in the expanded 384-megabit area.

By using the memory areas and the FIFO buffer areas alternately arranged as shown in FIG. 5, the memory area can be used as either the 128 megabit memory 610 or the 512 megabit memory 620 as shown in FIG. It will be possible.

In FIG. 6, first, FIG. 6A shows a wiring pattern on the substrate. In FIG. 6A, the FIF
It is assumed that the 16th bit and the 17th bit of the O pointer controller 136 are assigned to the wiring 601 and the wiring 602, respectively.

In this case, the memory 610 shown in FIG.
When used as,
The NC terminal 611 and the NC terminal 612 are assigned respectively. Therefore, although the 16th and 17th bits are invalid, the FIFO pointer controller 1
The pointer of 36 is valid from the 15th bit to the 1st bit.

On the other hand, as shown in FIG.
When used as 20, the 16-bit address terminal 621 and the 17-bit address terminal 622 are allocated to the wiring 601 and the wiring 602. Therefore, the pointer of the FIFO point controller is 17
Since the first bit to the first bit are valid, a memory having a larger capacity than the memory 610 can be constructed.

Therefore, it is possible to easily change the memory capacity by utilizing the mapped memory areas and the FIFO buffer areas arranged alternately.

As described above, according to the present embodiment, since the external memory is used, there is no physical restriction on the capacity of the FIFO buffer, and the capacity can be made large. It becomes possible to efficiently handle a large amount of data such as.

Further, by alternately arranging the mapped memory area address and the memory area address used as the FIFO buffer for each predetermined area, it is possible to flexibly cope with a system design change such as a memory capacity change. It becomes possible to do.

[0072]

As described above, according to the data transfer apparatus of the present invention, since the external memory is used, the F
Since there is no physical restriction on the capacity of the IFO buffer and a large capacity can be taken, it becomes possible to efficiently handle large capacity data such as image and audio data.

Further, by alternately arranging the mapped memory area address and the memory area address used as the FIFO buffer for each predetermined area, it is possible to flexibly cope with a system design change such as a memory capacity change. It becomes possible to do.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a data transfer device according to an embodiment of the present invention.

FIG. 2 is a flowchart of write processing from a local bus to a host bus in the data transfer device according to the embodiment of the present invention.

FIG. 3 is a configuration diagram of a FIFO pointer controller in the data transfer device according to the embodiment of the present invention.

FIG. 4 is an exemplary diagram of a pointer output from a FIFO pointer controller.

FIG. 5 is an exemplary diagram of address arrangement of an external memory in the data transfer device according to the embodiment of the present invention.

FIG. 6 is an exemplary diagram of a wiring pattern and a pin arrangement of a memory on a substrate.

FIG. 7 is a block diagram of a conventional data transfer device.

[Explanation of symbols]

1, 170 Local bus 2, 160 Host bus 3, 100 CPU 4, 110 Memory 5, 120 I / O device 6, 130 Data transfer device 7, 131 Arbiter 8, 132 Secondary bus master 9, 133 Secondary bus target 10 FIFO controller 11 , 141 Address storage FIFO buffer 12, 142 Data storage FIFO buffer 13, 145 Primary bus master 14, 146 Primary bus target 134, 144 Address decoder 135 FIFO data controller 136 FIFO pointer controller 137 First selector 138 Address buffer 139 Data buffer 140 second selector 143 memory buffer 150 external memory 300 FIFO counter 301 selector 302 15-bit counter 303 F from the selector output and 15-bit counter output
Circuit for controlling output of IFO counter 304 Circuit for controlling memory address from output of FIFO counter and FIFO address signal S301 Address / data switching signal S302 Write counter control signal S303 FIFO address signal S304 Selector output signal S305 Output from 15-bit counter Signal S306 Output signal from FIFO counter S307 Output from memory address control circuit 304 (17-bit memory address) S308 Read counter control signal

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5B061 BA01 BB08 FF01 FF22 GG02                       GG15                 5B077 AA14 AA15 BA02 BA04 DD02                       DD21 MM03

Claims (4)

[Claims] 1. A data transfer device for transferring data from a first bus to a second bus, comprising a memory control unit for controlling an external memory as a FIFO (First-In First-Out) buffer, A data transfer device, wherein the memory control unit temporarily stores an address and data in the external memory when writing from the first bus to the second bus. 2. In the memory control unit, a first address group for a mapped memory area and a second address group for a memory area used as a FIFO buffer are arranged in an address space, and the first address 2. The data transfer device according to claim 1, wherein a group and the second address group are distinguished by the state of a specific bit. 3. The data transfer according to claim 1, wherein in the memory control unit, an address for a mapped memory area and an address for a memory area used as a FIFO buffer are alternately arranged in a real address space. apparatus. 4. In the memory control unit, the specific bit for distinguishing between the first address group and the second address group is a specific bit of an address line which is common to a plurality of external memories having different capacities. The data transfer apparatus according to claim 2, wherein