JPH04273153A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04273153A JPH04273153A JP5360791A JP5360791A JPH04273153A JP H04273153 A JPH04273153 A JP H04273153A JP 5360791 A JP5360791 A JP 5360791A JP 5360791 A JP5360791 A JP 5360791A JP H04273153 A JPH04273153 A JP H04273153A
- Authority
- JP
- Japan
- Prior art keywords
- grounding
- integrated circuit
- metal plate
- semiconductor device
- circuit element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 67
- 229910052751 metal Inorganic materials 0.000 claims abstract description 67
- 239000000919 ceramic Substances 0.000 claims abstract description 17
- 238000007789 sealing Methods 0.000 description 8
- 238000005219 brazing Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229910015363 Au—Sn Inorganic materials 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 229910017944 Ag—Cu Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は集積回路素子を搭載した
半導体装置に関し、特に高周波で使用される複数の接地
用電極を有する集積回路素子を搭載した半導体装置に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device equipped with an integrated circuit element, and more particularly to a semiconductor device equipped with an integrated circuit element having a plurality of grounding electrodes used at high frequencies.
【０００２】0002
【従来の技術】従来の高周波用集積回路素子を搭載して
なる半導体装置の一例として、例えば図３に示すものが
ある。ここで、図３（ａ）はキャップ封止を行っていな
い半導体装置の上面図、同図（ｂ）は（ａ）のＣ−Ｃ線
に沿う縦断面図、同図（ｃ）は底面図である。これらの
図において、セラミック基台１の上面には集積回路素子
６がＡｕ−Ｓｎ合金又は、Ａｇペースト等のソルダ（図
示せず）により、マウント固着されている。又、セラミ
ック基台１に設けたメタライズパターン２により電極部
２ａと接地部２ｂが形成され、これらと集積回路素子６
の電極（図示せず）とがＡｕ，Ａｌ等からなる金属細線
７ａ，７ｂで接続されている。尚、７ａは信号又は電源
用金属細線、７ｂは接地用金属細線である。前記メタラ
イズパターン２は導出用スルーホール３を介して底面に
まで延長され、外部導出リード４にＡｇ−Ｃｕ合金等の
ロウ材５によりロウ接されている。2. Description of the Related Art An example of a semiconductor device equipped with a conventional high frequency integrated circuit element is shown in FIG. Here, FIG. 3(a) is a top view of a semiconductor device without cap sealing, FIG. 3(b) is a longitudinal sectional view taken along line C-C in FIG. 3(a), and FIG. It is. In these figures, an integrated circuit element 6 is mounted and fixed on the upper surface of a ceramic base 1 using a solder (not shown) such as an Au-Sn alloy or Ag paste. Further, an electrode portion 2a and a ground portion 2b are formed by the metallized pattern 2 provided on the ceramic base 1, and these and the integrated circuit element 6 are connected to each other.
are connected to electrodes (not shown) by thin metal wires 7a and 7b made of Au, Al, etc. Note that 7a is a thin metal wire for signal or power supply, and 7b is a thin metal wire for grounding. The metallized pattern 2 extends to the bottom surface through the lead-out through hole 3, and is brazed to the external lead-out lead 4 with a brazing material 5 such as an Ag-Cu alloy.
【０００３】又、内部に搭載した集積回路素子６を環境
保護する目的で、ロウ接用メタライズパターンが施され
たアルミナセラミック又は、金属材料等からなるキャッ
プ１０をＡｕ−Ｓｎ合金等のロウ材１１によりセラミッ
ク基台１上にロウ接封止されている。Further, in order to protect the environment of the integrated circuit element 6 mounted inside, a cap 10 made of alumina ceramic or a metal material with a metallized pattern for soldering is replaced with a brazing material 11 such as an Au-Sn alloy. The ceramic base 1 is soldered and sealed onto the ceramic base 1.
【０００４】0004
【発明が解決しようとする課題】この従来の半導体装置
では、セラミック基台１の上面に集積回路素子６が搭載
され、かつこれと同一平面上に設けたメタライズパター
ン２の電極部２ａと接地部２ｂに夫々金属細線７ａ，７
ｂが接続されているために、特に接地用の金属細線７ｂ
が長くなり、半導体装置における接地インダクタンスが
大きくなるという問題を有していた。これは、高周波（
周波数：９００ＭＨＺ 以上）にて動作させるＦＥＴの
多段構成の増幅用集積回路素子を搭載した半導体装置で
は、接地インダクタンスが大きいために利得を大きく取
ることができないといった問題となる。[Problems to be Solved by the Invention] In this conventional semiconductor device, an integrated circuit element 6 is mounted on the upper surface of a ceramic base 1, and an electrode portion 2a and a ground portion of a metallized pattern 2 provided on the same plane as the integrated circuit element 6 are mounted on the upper surface of a ceramic base 1. 2b with thin metal wires 7a and 7, respectively.
b is connected, especially the thin metal wire 7b for grounding.
This has the problem of increasing the grounding inductance of the semiconductor device. This is a high frequency (
In a semiconductor device equipped with an amplifying integrated circuit element having a multi-stage configuration of FETs operated at a frequency of 900 MHz or higher, a problem arises in that a large gain cannot be achieved because of the large ground inductance.
【０００５】又、接地用の金属細線７ｂは集積回路素子
６の近傍に設けたメタライズパターン２の接地部２ｂに
接続されるが、集積回路素子６をマウント固着するソル
ダ（ＡｇペーストあるいはＡｕ−Ｓｎロウ材等）の広が
りにより、ソルダが接地部２ｂに到達され易く、この場
合には金属細線７ｂが接続できなくなり、或いは接続が
不十分となり、半導体装置の使用環境、特に、振動環境
下においてオープン不良となり易い等の問題を有してい
た。本発明の目的は接地用の金属細線の短縮化を図り、
かつ金属細線の接続不良を解消した半導体装置を提供す
ることにある。Further, the thin metal wire 7b for grounding is connected to the grounding part 2b of the metallized pattern 2 provided near the integrated circuit element 6, but solder (Ag paste or Au-Sn) for mounting and fixing the integrated circuit element 6 is used. Due to the spread of the solder (brazing material, etc.), the solder tends to reach the grounding part 2b, and in this case, the thin metal wire 7b cannot be connected, or the connection becomes insufficient, and it may become open in the operating environment of the semiconductor device, especially in a vibration environment. It had problems such as being easily defective. The purpose of the present invention is to shorten the length of a thin metal wire for grounding,
Another object of the present invention is to provide a semiconductor device in which poor connection of thin metal wires is eliminated.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置は、
集積回路素子を搭載し、かつメタライズパターンを形成
したセラミック基台の上面に、集積回路素子に近接して
接地用金属板を形成し、この接地用金属板と集積回路素
子の接地端子とを接地用の金属細線で接続した構成とす
る。又、接地用金属板に凹形状加工部を設け、この凹形
状加工部を跨ぐように集積回路素子とメタライズパター
ンとを接続する信号又は電源用の金属細線を延設する。[Means for Solving the Problems] A semiconductor device of the present invention includes:
A grounding metal plate is formed close to the integrated circuit element on the top surface of the ceramic base on which the integrated circuit element is mounted and a metallized pattern is formed, and this grounding metal plate and the ground terminal of the integrated circuit element are grounded. The configuration is such that they are connected using thin metal wires. Further, a concave-shaped processed portion is provided on the grounding metal plate, and a thin metal wire for signal or power supply that connects the integrated circuit element and the metallized pattern is extended so as to straddle this concave-shaped processed portion.
【０００７】[0007]
【作用】本発明によれば、接地用金属細線を短くして接
地インダクタンスを低減できる。又、信号又は電源用金
属細線が接地用金属板に接触することを防止し、この金
属細線の短縮化も実現できる。According to the present invention, the grounding inductance can be reduced by shortening the thin metal wire for grounding. Further, it is possible to prevent the thin metal wire for signal or power source from coming into contact with the grounding metal plate, and to shorten the thin metal wire.
【０００８】[0008]
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明の一実施例を示し、同図（ａ）はキャ
ップ封止前の半導体装置の上面図、同図（ｂ）は（ａ）
のＡ−Ａ線に沿う縦断面図である。これらの図において
、１はセラミック基台であり、その上面，側面及び底面
に施されたメタライズパターン２と導出用スルーホール
３を介して外部導出リード４がロウ材５によりロウ接け
されている。又、半導体装置内部には集積回路素子６が
マウント固着され、信号又は電源用の金属細線７ａによ
り前記メタライズパターン２の一部で構成された電極部
２ａに接続されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 shows an embodiment of the present invention, in which (a) is a top view of a semiconductor device before sealing with a cap, and (b) is a top view of a semiconductor device before sealing with a cap.
It is a longitudinal cross-sectional view along the AA line of. In these figures, reference numeral 1 denotes a ceramic base, to which an external lead 4 is soldered using a brazing material 5 via a metallized pattern 2 formed on the top, side, and bottom surfaces and a lead-out through hole 3. . Further, an integrated circuit element 6 is mounted and fixed inside the semiconductor device, and is connected to an electrode portion 2a formed of a part of the metallized pattern 2 by a thin metal wire 7a for signal or power supply.
【０００９】前記セラミック基台１の上面には前記メタ
ライズパターン２を包囲するように接地用金属板８が設
けられ、その外周部は封止用金属板９として構成される
。そして、この接地用金属板８には前記集積回路素子６
の接地端子と接続するための接地用の金属細線７ｂが接
続される。尚、これら接地用金属板８と封止用金属板９
とはＡｇ−Ｃｕ合金等からなり、前記セラミック基台１
に形成されたメタライズパターン２の電極以外の部分で
構成される接地部２ｂの上にロウ接されている。更に、
図に破線で示すキャップ１０はロウ材１１により封止用
金属板９に固着され、集積回路素子６を気密封止してい
る。A grounding metal plate 8 is provided on the upper surface of the ceramic base 1 so as to surround the metallized pattern 2, and its outer periphery is configured as a sealing metal plate 9. The integrated circuit element 6 is attached to this grounding metal plate 8.
A thin metal wire 7b for grounding is connected to the grounding terminal of the terminal. Furthermore, these grounding metal plate 8 and sealing metal plate 9
is made of Ag-Cu alloy or the like, and is made of the ceramic base 1.
The metallized pattern 2 is soldered onto a ground portion 2b formed of a portion other than the electrodes of the metallized pattern 2 formed on the ground portion 2b. Furthermore,
A cap 10 indicated by a broken line in the figure is fixed to the sealing metal plate 9 with a brazing material 11, and hermetically seals the integrated circuit element 6.
【００１０】したがって、この構成によれば、集積回路
素子６とメタライズパターン２の電極部２ａとの間に接
地用金属板８が配設され、かつこの接地用金属板８の表
面高さは電極部２ａの表面高さよりも高いため、集積回
路素子６と接地用金属板８とを接続する金属細線７ｂの
長さを短くすることができる。これにより、接地インダ
クタンスを小さくすることができる。因みに、本発明者
による測定結果では、接地用金属板８を設けたことによ
り、これが無い場合に比べて接地インダクタンスを １
／２〜 １／３に低減することができた。Therefore, according to this configuration, the grounding metal plate 8 is disposed between the integrated circuit element 6 and the electrode portion 2a of the metallized pattern 2, and the surface height of the grounding metal plate 8 is higher than that of the electrode. Since it is higher than the surface height of the portion 2a, the length of the thin metal wire 7b connecting the integrated circuit element 6 and the grounding metal plate 8 can be shortened. Thereby, grounding inductance can be reduced. Incidentally, according to the measurement results by the present inventor, by providing the grounding metal plate 8, the grounding inductance was reduced by 1 compared to the case without it.
It was possible to reduce the amount by 2 to 1/3.
【００１１】又、接地用金属板８と封止用金属板９とを
一体構造とすることで、多数端子の接地が必要な高周波
集積回路素子においても、接地用金属板８の位置ずれを
少なくできる。更に、集積回路素子６をマウント固着す
る時用いられるロウ材（Ａｕ−Ｓｎ合金，Ａｇペースト
等）は、接地用金属板８を厚く形成していることにより
、接地用金属板８の外側に迄はみ出すことがなく、電極
部２ａにおける金属細線７ａのボンディング不良やルー
ズコンタクトによるオープン不良等を防止することも可
能となる。Furthermore, by making the grounding metal plate 8 and the sealing metal plate 9 into an integral structure, the displacement of the grounding metal plate 8 can be reduced even in high frequency integrated circuit devices that require grounding of multiple terminals. can. Furthermore, the brazing material (Au-Sn alloy, Ag paste, etc.) used to mount and secure the integrated circuit element 6 can reach the outside of the grounding metal plate 8 by forming the grounding metal plate 8 thickly. There is no protrusion, and it is also possible to prevent bonding defects of the thin metal wires 7a in the electrode portions 2a, open defects due to loose contacts, and the like.
【００１２】図２は本発明の他の実施例を示し、同図（
ａ）はキャップ封止前の半導体装置の上面図、同図（ｂ
）は（ａ）のＢ−Ｂ線に沿う縦断面図である。尚、図１
の実施例と等価な部分には同一符号を付してある。
この実施例では、接地用金属板８の複数箇所に凹形状加
工部１２（図２（ａ）に斜線で示す領域）を形成し、こ
の凹形状加工部１２をまたぐように電極部２ａと集積回
路素子６を接続する信号又は電源用の金属細線７ａを延
設している。この凹形状加工部１２の加工方法としては
、エッチング法による片面マスキングによるハーフエッ
チング方法と、プレス加工によるコイニング加工方法な
らびに切削加工方法等が有る。FIG. 2 shows another embodiment of the present invention.
a) is a top view of the semiconductor device before capping;
) is a vertical cross-sectional view taken along line BB in (a). Furthermore, Figure 1
Parts equivalent to those in the embodiment are given the same reference numerals. In this embodiment, concave-shaped processed portions 12 (areas indicated by diagonal lines in FIG. 2(a)) are formed at multiple locations on the grounding metal plate 8, and the electrode portions 2a are integrated so as to straddle the concave-shaped processed portions 12. A thin metal wire 7a for signal or power supply connecting the circuit elements 6 is extended. Methods for processing the concave shaped portion 12 include a half-etching method using one-sided masking using an etching method, a coining method using press working, and a cutting method.
【００１３】この実施例においても、集積回路素子６の
周囲に接地用金属板８を配設することで接地用の金属細
線７ｂの長さを短くし、接地インダクタンスを低減する
ことができる。又、これに加えて、接地用金属板８に凹
形状加工部１２を設けることで、信号又は電源用の金属
細線７ａが接地用金属板８の角部と接触することが防止
でき、しかも金属細線の細径化によるコスト低減が図れ
るとともに、金属細線を短くして半導体装置の外形小型
化も実現できる。Also in this embodiment, by arranging the grounding metal plate 8 around the integrated circuit element 6, the length of the grounding thin metal wire 7b can be shortened and the grounding inductance can be reduced. In addition, by providing the concave processed portion 12 on the grounding metal plate 8, it is possible to prevent the thin metal wire 7a for signal or power supply from coming into contact with the corner of the grounding metal plate 8. By reducing the diameter of the thin wire, it is possible to reduce costs, and by shortening the thin metal wire, it is also possible to reduce the size of the semiconductor device.
【００１４】[0014]
【発明の効果】以上説明したように本発明の半導体装置
は、セラミック基台の上面に接地用金属板を設け、この
接地用金属板上に接地用の金属細線を接続しているので
、接地用金属板の板厚さに相当する分金属細線の長さを
短くすることができ、接地インダクタンスを低減し、高
周波増幅用半導体装置の利得を大幅に改善することが可
能となる。又、接地用金属板に凹形状加工部を設け、こ
こに信号又は電源用の金属細線を延設することで、この
金属細線と接地用金属板との接触を防止し、この金属細
線の短縮化を図り、半導体装置の小型化を実現すること
もできる。Effects of the Invention As explained above, the semiconductor device of the present invention has a grounding metal plate provided on the top surface of the ceramic base, and a thin metal wire for grounding is connected to the grounding metal plate. The length of the thin metal wire can be shortened by an amount corresponding to the thickness of the metal plate for use, reducing the grounding inductance and greatly improving the gain of the semiconductor device for high frequency amplification. In addition, by providing a concave processed part on the grounding metal plate and extending a thin metal wire for signal or power supply here, contact between the thin metal wire and the grounding metal plate can be prevented, and the thin metal wire can be shortened. It is also possible to achieve miniaturization of semiconductor devices.
【図１】本発明の一実施例を示し、（ａ）は平面図、（
ｂ）は（ａ）のＡ−Ａ線に沿う縦断面図である。FIG. 1 shows an embodiment of the present invention, (a) is a plan view, (a) is a plan view;
b) is a longitudinal sectional view taken along line A-A in (a).
【図２】本発明の他の実施例を示し、（ａ）は平面図、
（ｂ）は（ａ）のＢ−Ｂ線に沿う縦断面図である。FIG. 2 shows another embodiment of the present invention, (a) is a plan view;
(b) is a vertical cross-sectional view taken along line BB in (a).
【図３】従来の半導体装置の一例を示し、（ａ）は平面
図、（ｂ）は（ａ）のＣ−Ｃ線に沿う縦断面図、（ｃ）
は底面図である。FIG. 3 shows an example of a conventional semiconductor device, in which (a) is a plan view, (b) is a vertical cross-sectional view taken along line C-C in (a), and (c) is a top view.
is a bottom view.
１ セラミック基台
２ メタライズパターン
６ 集積回路素子
７ａ，７ｂ 金属細線
８ 接地用金属板
９ 封止用金属板
１０ キャップ
１２ 凹形状加工部1 Ceramic base
2 Metallized pattern 6 Integrated circuit element
7a, 7b Metal thin wire 8 Grounding metal plate
9 Sealing metal plate 10 Cap
12 Concave shape processing part
Claims (2)
パターンと、このセラミック基台の上面に搭載した集積
回路素子とを金属細線で説明してなる半導体装置におい
て、前記セラミック基台の上面には集積回路素子に近接
して接地用金属板を形成し、この接地用金属板と集積回
路素子の接地端子とを接地用の金属細線で接続したこと
を特徴とする半導体装置。1. A semiconductor device in which a metallized pattern formed on a ceramic base and an integrated circuit element mounted on the top surface of the ceramic base are illustrated by thin metal wires, wherein the top surface of the ceramic base has an integrated circuit element mounted on the top surface of the ceramic base. A semiconductor device characterized in that a grounding metal plate is formed close to an element, and the grounding metal plate and a grounding terminal of an integrated circuit element are connected by a grounding metal thin wire.
この凹形状加工部を跨ぐように前記集積回路素子とメタ
ライズパターンとを接続する信号又は電源端子用の金属
細線を延設してなる請求項１の半導体装置。[Claim 2] Providing a concave shaped part on the grounding metal plate,
2. The semiconductor device according to claim 1, further comprising a thin metal wire for a signal or power supply terminal connecting the integrated circuit element and the metallized pattern so as to straddle the concave portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3053607A JP2666588B2 (en) | 1991-02-27 | 1991-02-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3053607A JP2666588B2 (en) | 1991-02-27 | 1991-02-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04273153A true JPH04273153A (en) | 1992-09-29 |
| JP2666588B2 JP2666588B2 (en) | 1997-10-22 |
Family
ID=12947581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3053607A Expired - Fee Related JP2666588B2 (en) | 1991-02-27 | 1991-02-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2666588B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010192925A (en) * | 2003-02-10 | 2010-09-02 | Skyworks Solutions Inc | Semiconductor die package with reduced inductance and reduced die attach flow out |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6226056A (en) * | 1985-07-15 | 1987-02-04 | ゲブリユ−ダ− ズルツア− アクチエンゲゼルシヤフト | Plastic hip joint anchored in pelvis without cement |
| JPH04129250A (en) * | 1990-09-20 | 1992-04-30 | Nec Corp | Thin type hybrid integrated circuit substrate |
| JPH04162751A (en) * | 1990-10-26 | 1992-06-08 | Nec Yamagata Ltd | High frequency semiconductor device |
-
1991
- 1991-02-27 JP JP3053607A patent/JP2666588B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6226056A (en) * | 1985-07-15 | 1987-02-04 | ゲブリユ−ダ− ズルツア− アクチエンゲゼルシヤフト | Plastic hip joint anchored in pelvis without cement |
| JPH04129250A (en) * | 1990-09-20 | 1992-04-30 | Nec Corp | Thin type hybrid integrated circuit substrate |
| JPH04162751A (en) * | 1990-10-26 | 1992-06-08 | Nec Yamagata Ltd | High frequency semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010192925A (en) * | 2003-02-10 | 2010-09-02 | Skyworks Solutions Inc | Semiconductor die package with reduced inductance and reduced die attach flow out |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2666588B2 (en) | 1997-10-22 |
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