JPH02119168A - Flat-type semiconductor device - Google Patents

Flat-type semiconductor device

Info

Publication number
JPH02119168A
JPH02119168A JP27222688A JP27222688A JPH02119168A JP H02119168 A JPH02119168 A JP H02119168A JP 27222688 A JP27222688 A JP 27222688A JP 27222688 A JP27222688 A JP 27222688A JP H02119168 A JPH02119168 A JP H02119168A
Authority
JP
Japan
Prior art keywords
container
leads
semiconductor device
flat
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27222688A
Other languages
Japanese (ja)
Inventor
Katsushi Terajima
克司 寺島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP27222688A priority Critical patent/JPH02119168A/en
Publication of JPH02119168A publication Critical patent/JPH02119168A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To eliminate the necessity of reducing the widths and pitches of outer leads and reduce the manufacturing cost of a container for a semiconductor package by a method wherein a protrusion is formed on the bottom part of the container and the outer leads are attached to the respective steps of the protrusion. CONSTITUTION:A semiconductor element 1 is placed in the cavity 9 of a container 2 made of ceramics and connected to inner wirings 7 provided around it with bonding wires 3. The inner wirings 6 are drawn out of the container 2 as outer leads 6A and 6B provided on the steps of the bottom part of the container 2 which is so formed as to have a protruding shape through side wirings 8. The leads 6B are provided on the protrusion 2A so as to be in parallel with the bottom surface and the tip parts of the leads 6A provided or the upper step are bent so as to be in the same plane with the leads 6B. With this constitution, the outer leads can be provided over the two steps and the necessity of reducing the widths and pitches of the leads can be eliminated, so that the manufacturing cost of the container can be reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はフラット型半導体装置に関し、特に外部リード
の取り付は構造に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a flat type semiconductor device, and particularly relates to the structure of attaching external leads.

〔従来の技術〕[Conventional technology]

従来、ラミネートタイプのセラミックパッケージを利用
したフラット型半導体装置は、第3図(a)、(b)に
示すように、セラミックからなる容器2の中央のキャビ
ティ9に半導体素子1を搭載し、キャビティ9の周囲に
メタライズされた内部配線7にボンディングワイヤ3に
よりボンディング結線したのち、金属またはセラミック
の蓋4により気密封止し、容器2の底面部11の外周部
には側部配線8に接続される外部リード6が固着された
構造となっていた。
Conventionally, a flat semiconductor device using a laminate type ceramic package has a semiconductor element 1 mounted in a cavity 9 at the center of a container 2 made of ceramic, as shown in FIGS. 3(a) and 3(b). After bonding to the internal wiring 7 metalized around the container 9 using the bonding wire 3, it is hermetically sealed with a metal or ceramic lid 4, and the outer peripheral part of the bottom surface 11 of the container 2 is connected to the side wiring 8. It had a structure in which the external leads 6 were fixed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のフラット型半導体装置の外部リード6は
、半導体装置の側部または底面部の周囲に同一平面を成
して取り付けられているので、近年の高集積化した半導
体素子を搭載し、なおかつ小型化する半導体装置におい
て、フラット型半導体装置の外部リードは多ビン化に対
応するべくファイン化の傾向を採らざるを得ない、よっ
て、同一平面上の各辺に設けられた外部リードは、その
リード幅、リードピッチが小さくなるため容器の製造コ
ストを引き上げ、かつ歩留りを下げるのみではなく、実
装時の半田付けも含めて取り扱い精度が難しくなってき
ている。
The external leads 6 of the conventional flat semiconductor device described above are attached to the side or bottom of the semiconductor device so as to form the same plane. As semiconductor devices become smaller, the external leads of flat semiconductor devices have to become finer in order to accommodate the increased number of bins. Therefore, the external leads provided on each side of the same plane are As the lead width and lead pitch become smaller, not only does the manufacturing cost of the container increase and the yield decrease, but it also becomes difficult to handle accurately, including soldering during mounting.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のフラット型半導体装置は、上面にキャビティを
有する容器と、前記キャビティ内に固着された半導体素
子と、前記容器の底面の外周部に該底面と平行に設けら
れた外部リードと、前記半導体素子を密封する蓋とを有
するフラット型半導体装置において、前記容器の底面部
は凸状に形成され、該凸状部の各段部には外部リードが
固着されているものである。
The flat semiconductor device of the present invention includes a container having a cavity on the upper surface, a semiconductor element fixed in the cavity, an external lead provided on the outer periphery of the bottom surface of the container in parallel with the bottom surface, and a semiconductor element fixed in the cavity. In a flat semiconductor device having a lid for sealing an element, the bottom of the container is formed in a convex shape, and external leads are fixed to each step of the convex part.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)、(b)は本発明の第1の実施例の断面図
及び下面図である。
FIGS. 1(a) and 1(b) are a sectional view and a bottom view of a first embodiment of the present invention.

第1図(a)、(b)において半導体素子1はセラミッ
クからなる容器2のキャビティ9に搭載され、キャビテ
ィ9の周囲に設けられた内部配線7にボンディングワイ
ヤ3にて結線され、そこより導びかれな側部配線8にて
凸状に形成された容器2の底部の各段部に設けたコバー
ル等からなる外部リード6A、6Bに導出されている。
In FIGS. 1(a) and 1(b), a semiconductor element 1 is mounted in a cavity 9 of a container 2 made of ceramic, and is connected to an internal wiring 7 provided around the cavity 9 using a bonding wire 3, and from there a conductor is connected. The open side wiring 8 leads to external leads 6A and 6B made of Kovar or the like provided at each step on the bottom of the container 2 which is formed in a convex shape.

そして上段部周囲に設けられた外部リード6Aは、凸部
2Aに底面と平行になるように設けられた外部リード6
Bと同一平面になる様に、先端部を折り曲げ加工しであ
る。尚4はろう材5により容器2に密封された蓋である
The external leads 6A provided around the upper part are the external leads 6A provided on the convex part 2A so as to be parallel to the bottom surface.
The tip is bent so that it is flush with B. Note that 4 is a lid sealed to the container 2 with a brazing material 5.

このように構成された第1の実施例によれば、外部リー
ドを2段にわたって取付けることができ、外部リードの
幅やピッチを小さくする必要がないので、容器の製造コ
ストを低減させることができる。
According to the first embodiment configured in this way, the external leads can be attached in two stages, and there is no need to reduce the width or pitch of the external leads, so the manufacturing cost of the container can be reduced. .

第2図(a)、(b)は本発明の第2の実施例の断面図
および下面図である。
FIGS. 2(a) and 2(b) are a sectional view and a bottom view of a second embodiment of the present invention.

水弟2の実施例においては、容器2の凸部2Aの面、す
なわち下段に外部電極10を設けた以外は第1の実施例
と同じである。すなわち、外部電極10は容器2の底面
部にメタライズされてあり、いわゆるLCC(リードレ
スチップキャリア)と同等の構造をなしている。そして
、周囲に設けられた上段の外部リード6Aは、この外部
電極10と同一平面になる様にリード先端を折り曲げで
ある。
The embodiment of the second embodiment is the same as the first embodiment except that the external electrode 10 is provided on the surface of the convex portion 2A of the container 2, that is, on the lower stage. That is, the external electrode 10 is metallized on the bottom surface of the container 2, and has a structure similar to that of a so-called LCC (leadless chip carrier). The leading ends of the upper external leads 6A provided on the periphery are bent so as to be on the same plane as the external electrodes 10.

水弟2の実施例によれば、第1の実施例に比べ外部リー
ドフレームを一段設けるだけで良いなめ、リードフレー
ムの接着工数が削減できるだけでなく、半導体装置組立
後のリード切断、フォーミングも削減することができる
利点がある。
According to the embodiment of Sui-Tei 2, compared to the first embodiment, only one stage of external lead frame is required, which not only reduces the number of steps required for bonding the lead frame, but also reduces lead cutting and forming after semiconductor device assembly. There are advantages to being able to do so.

このように上記実施例によれば外部リードを2周に分割
して取り付けられることが可能となり、従来の同一平面
上のフラット型半導体装置の外部リードに比べ、リード
幅、ピッチを1.5〜2.0倍に拡張することが可能と
なる。また容器の製造のみならず、組立工程、仕上工程
のハンドリングによる外部リードの変形や損傷も抑制で
き、更に実装時のハンダ付は性や位置精度の向上も図る
ことができる。
In this way, according to the above embodiment, it is possible to attach the external leads by dividing them into two circumferences, and the lead width and pitch can be reduced by 1.5 to 1.5 mm compared to the conventional external leads of flat type semiconductor devices on the same plane. It becomes possible to expand by 2.0 times. In addition, it is possible to suppress deformation and damage to the external leads due to handling not only in the manufacturing of the container but also in the assembly process and finishing process, and furthermore, it is possible to improve soldering performance and positional accuracy during mounting.

また上記実施例は、半導体素子搭載面と反対側にリード
フレームを取り付けてあったが、同じ方向に外部リード
を設けても良く、必要に応じて素子搭載面の裏側にヒー
トシンクを取り付けることも可能となり表面実装対応の
高消費電力素子用半導体装置としてPGAに替わり有効
となる。
Also, in the above embodiment, the lead frame was attached to the side opposite to the semiconductor element mounting surface, but external leads may be provided in the same direction, and if necessary, a heat sink can be attached to the back side of the element mounting surface. Therefore, it becomes an effective alternative to PGA as a semiconductor device for high power consumption devices compatible with surface mounting.

さらに、上記実施例は外部リードの取り付は部が2段に
分割されたフラット型半導体装置であったが、3段以上
に分割されたものでも良く、容器もセラミック材料に限
定されるものではなく金属や樹脂等でも良い。
Furthermore, although the above embodiment is a flat type semiconductor device in which the external lead attachment section is divided into two stages, it may be divided into three or more stages, and the container is not limited to ceramic material. Instead, metal, resin, etc. may be used.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、パッケージを構成する容
器の底面部を凸状に形成し、この凸状部の各段に外部リ
ードを固着することにより、製造コストが低減され、か
つ実装時の半田付は等の取り扱いの容易なフラット型半
導体装置が得られる。
As explained above, the present invention reduces manufacturing costs by forming the bottom of the container constituting the package into a convex shape and fixing external leads to each stage of the convex part, and also reduces manufacturing costs during mounting. A flat semiconductor device that is easy to handle, such as soldering, can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)、(b)及び第2図(a)、(b)は本発
明の第1及び第2の実施例の断面図及び下面図、第3図
(a)、(b)は従来のフラット型半導体装置の断面図
及び下面図である。 1・・・半導体素子、2・・・容器、2A・・・凸部、
3・・・ボンディングワイヤ、4・・・蓋、5・・・ろ
う材、6゜6A、6B・・・外部リード、7・・・内部
配線、8・・・側部配線、9・・・キャビティ、10・
・・外部電極。
1(a), (b) and 2(a), (b) are sectional views and bottom views of the first and second embodiments of the present invention, and FIG. 3(a), (b) 1A and 1B are a cross-sectional view and a bottom view of a conventional flat type semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 2... Container, 2A... Convex part,
3... Bonding wire, 4... Lid, 5... Brazing metal, 6°6A, 6B... External lead, 7... Internal wiring, 8... Side wiring, 9... Cavity, 10・
...External electrode.

Claims (1)

【特許請求の範囲】[Claims] 上面にキャビティを有する容器と、前記キャビティ内に
固着された半導体素子と、前記容器の底面の外周部に該
底面と平行に設けられた外部リードと、前記半導体素子
を密封する蓋とを有するフラット型半導体装置において
、前記容器の底面部は凸状に形成され、該凸状部の各段
部には外部リードが固着されていることを特徴とするフ
ラット型半導体装置。
A flat container comprising a container having a cavity on the upper surface, a semiconductor element fixed in the cavity, an external lead provided on the outer periphery of the bottom surface of the container parallel to the bottom surface, and a lid for sealing the semiconductor element. A flat type semiconductor device, characterized in that the bottom surface of the container is formed in a convex shape, and an external lead is fixed to each step of the convex part.
JP27222688A 1988-10-27 1988-10-27 Flat-type semiconductor device Pending JPH02119168A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27222688A JPH02119168A (en) 1988-10-27 1988-10-27 Flat-type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27222688A JPH02119168A (en) 1988-10-27 1988-10-27 Flat-type semiconductor device

Publications (1)

Publication Number Publication Date
JPH02119168A true JPH02119168A (en) 1990-05-07

Family

ID=17510872

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27222688A Pending JPH02119168A (en) 1988-10-27 1988-10-27 Flat-type semiconductor device

Country Status (1)

Country Link
JP (1) JPH02119168A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5808357A (en) * 1992-06-02 1998-09-15 Fujitsu Limited Semiconductor device having resin encapsulated package structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5808357A (en) * 1992-06-02 1998-09-15 Fujitsu Limited Semiconductor device having resin encapsulated package structure
US6031280A (en) * 1992-06-02 2000-02-29 Fujitsu Limited Semiconductor device having resin encapsulated package structure
US6271583B1 (en) 1992-06-02 2001-08-07 Fujitsu Limited Semiconductor device having resin encapsulated package structure

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