JP2536431B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2536431B2
JP2536431B2 JP5265410A JP26541093A JP2536431B2 JP 2536431 B2 JP2536431 B2 JP 2536431B2 JP 5265410 A JP5265410 A JP 5265410A JP 26541093 A JP26541093 A JP 26541093A JP 2536431 B2 JP2536431 B2 JP 2536431B2
Authority
JP
Japan
Prior art keywords
semiconductor element
concave portion
metal wire
tab
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5265410A
Other languages
Japanese (ja)
Other versions
JPH07106350A (en
Inventor
智司 村田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP5265410A priority Critical patent/JP2536431B2/en
Publication of JPH07106350A publication Critical patent/JPH07106350A/en
Application granted granted Critical
Publication of JP2536431B2 publication Critical patent/JP2536431B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
半導体素子をアイランド部にマウント材で接着しかつア
イランド部に電気接続を行う半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor element is bonded to an island portion with a mount material and electrically connected to the island portion.

【０００２】[0002]

【従来の技術】一般に高周波用半導体装置では、半導体
素子の共振を防ぐために、半導体素子を搭載するアイラ
ンド部を接地（グランド）することが多い。また、半導
体素子の接地用電極を接地電位に接続するため、接地用
電極とアイランド部とを金属ワイヤによってボンディン
グを行っている。図５は従来のこの種の半導体装置の一
例を示す図である。Ｆｅ−Ｎｉ合金、あるいはＣｕ系合
金からなる板材をプレス加工、もしくはエッチング加工
してリードフレーム１を形成し、インナーリード４の先
端と、半導体素子３を搭載するタブ２にＡｕ，Ａｇ等の
貴金属めっきを施している。半導体素子をタブに搭載す
るために接着剤やろう材等のマウント材８を用いてい
る。また、マウントされた半導体素子３をインナーリー
ド４に電気接続するために、Ａｕ等の金属ワイヤ５によ
って半導体素子３の電極３ａとインナーリード４とを接
続する。同様に、半導体素子３の接地用電極３ｂをタブ
２に電気接続するために金属ワイヤ５のボンディングを
行っている。2. Description of the Related Art Generally, in a high frequency semiconductor device, an island portion on which a semiconductor element is mounted is often grounded in order to prevent resonance of the semiconductor element. Further, in order to connect the ground electrode of the semiconductor element to the ground potential, the ground electrode and the island portion are bonded by a metal wire. FIG. 5 is a diagram showing an example of a conventional semiconductor device of this type. A plate material made of a Fe-Ni alloy or a Cu-based alloy is pressed or etched to form a lead frame 1, and noble metals such as Au and Ag are formed on the tips of the inner leads 4 and the tab 2 on which the semiconductor element 3 is mounted. It is plated. A mount material 8 such as an adhesive or a brazing material is used to mount the semiconductor element on the tab. Further, in order to electrically connect the mounted semiconductor element 3 to the inner lead 4, the electrode 3 a of the semiconductor element 3 and the inner lead 4 are connected by a metal wire 5 such as Au. Similarly, the metal wire 5 is bonded to electrically connect the ground electrode 3b of the semiconductor element 3 to the tab 2.

【０００３】ところで、このような半導体装置では、半
導体素子３を搭載するタブ２の表面が平坦であるため、
マウント材８が半導体素子３の下面から周囲に流れ出し
易い。このため、半導体素子３の接地用電極３ｂに接続
された金属ワイヤ５の他端をタブ２に接続しようとした
ときに、その位置にまでマウント材８が流れ出している
と、好適なワイヤボンディングを行うことができなくな
るという問題がある。このため、マウント材８の流れ出
しを制御することが要求されているが、実際にはこの流
れ出す量を制御することは難しい。また、半導体素子３
をマウントするときの位置決めにおいても多少の誤差が
生じるため、このマウント材８の流れ出し量の制御誤差
と、半導体素子３の位置決め誤差によって、金属ワイヤ
５を接続する箇所にマウント材８が存在しないようにす
ることは極めて難しい。In such a semiconductor device, since the surface of the tab 2 on which the semiconductor element 3 is mounted is flat,
The mount material 8 easily flows out from the lower surface of the semiconductor element 3 to the periphery. For this reason, when the other end of the metal wire 5 connected to the ground electrode 3b of the semiconductor element 3 is to be connected to the tab 2, if the mount material 8 flows out to that position, suitable wire bonding is performed. There is a problem that you cannot do it. Therefore, it is required to control the outflow of the mount material 8, but it is actually difficult to control the outflow amount. In addition, the semiconductor element 3
Since a slight error occurs in the positioning when mounting the mounting member 8, it is possible that the mounting member 8 does not exist at the position where the metal wire 5 is connected due to the control error of the flow amount of the mounting member 8 and the positioning error of the semiconductor element 3. It is extremely difficult to do.

【０００４】因みに、マウント材８の流れ出し量は、半
導体素子３の側面からＸ１＝０．２〜０．４ｍｍ程度で
あり、半導体素子３のマウント位置誤差はＸ２＝ ０．
０６〜０．１ｍｍ程度である。このため、これらの値を
考慮して金属ワイヤ５のボンディングを行う必要があ
り、結果として接地用の金属ワイヤ５が長くなる。一般
に高周波帯域では、ワイヤはインダクタンスとして等価
されるため、接地用の金属ワイヤが長くなればインダク
タンスが大きくなり、半導体素子の高周波特性を大きく
低下させる原因となる。Incidentally, the flow-out amount of the mount material 8 is about X1 = 0.2 to 0.4 mm from the side surface of the semiconductor element 3, and the mounting position error of the semiconductor element 3 is X2 = 0.
It is about 06 to 0.1 mm. Therefore, it is necessary to bond the metal wire 5 in consideration of these values, and as a result, the metal wire 5 for grounding becomes long. In general, in the high frequency band, the wire is equivalent to an inductance, and therefore, the longer the metal wire for grounding becomes, the larger the inductance becomes, which causes the high frequency characteristics of the semiconductor element to be largely deteriorated.

【０００５】このため、従来では図６に示す半導体装置
が提案されている。この例ではマウント材８が周囲に流
れ出すのを防止するために、タブ１の表面をハーフエッ
チング加工、またはディンプル加工等して半導体素子３
の大きさより大きな凹状部１２を形成している。この凹
状部１２を設けることにより、マウント材８が凹状部１
２の外側に流れ出ないようにし、凹状部１２の外側直近
部位での接地用金属ワイヤ５のボンディングを可能と
し、金属ワイヤ５の短縮化を図っている。Therefore, the semiconductor device shown in FIG. 6 has been conventionally proposed. In this example, in order to prevent the mount material 8 from flowing out to the periphery, the surface of the tab 1 is subjected to a half etching process, a dimple process, or the like to form the semiconductor element 3
The recessed portion 12 has a size larger than the size. By providing the recessed portion 12, the mount material 8 is provided with the recessed portion 1.
It is possible to bond the grounding metal wire 5 at a portion immediately outside the concave portion 12 so as not to flow out to the outside of the concave portion 12 and to shorten the metal wire 5.

【０００６】[0006]

【発明が解決しようとする課題】しかしながら、この構
成においても、半導体素子３の寸法に対して凹状部１２
の寸法に余裕がないと凹状部１２の側面部に這い上がっ
たマウント材８が素子の側面部に這い上がり、素子表面
でのショート不良を起こす場合がある。このため、その
余裕寸法Ｘ３と、前記した例と同様に半導体素子をマウ
ントするときの位置精度Ｘ２との寸法を考慮して凹状部
１２の寸法を決定する必要があり、このために凹状部１
２が半導体素子３の寸法に比較して格段に大きくなり、
結果として接地用の金属ワイヤ５の長さを短くすること
が難しくなるという問題がある。長くなる。また、半導
体素子３を凹状部１２の底面に搭載するために、タブ２
の表面に対して半導体素子３の高さが低くなり、インナ
ーリード４に接続される金属ワイヤ５が撓んだときに、
金属ワイヤ５がタブ２のエッジに接触して電気的な短絡
が発生し易いという問題もある。本発明の目的は、接地
用の金属ワイヤの長さを短くし、高周波特性を改善する
ことを可能にした半導体装置を提供することにある。However, even in this structure, the concave portion 12 is different from the size of the semiconductor element 3.
If there is no allowance for the dimension, the mount material 8 crawling up on the side surface of the concave portion 12 may creep up on the side surface of the element, causing a short circuit defect on the element surface. Therefore, it is necessary to determine the size of the concave portion 12 in consideration of the size of the allowance X3 and the positional accuracy X2 when mounting the semiconductor element as in the above-described example.
2 is much larger than the size of the semiconductor element 3,
As a result, there is a problem that it is difficult to shorten the length of the metal wire 5 for grounding. become longer. In order to mount the semiconductor element 3 on the bottom surface of the concave portion 12, the tab 2
When the height of the semiconductor element 3 becomes lower than the surface of the metal wire 5 and the metal wire 5 connected to the inner lead 4 is bent,
There is also a problem that the metal wire 5 comes into contact with the edge of the tab 2 and an electrical short circuit easily occurs. An object of the present invention is to provide a semiconductor device capable of improving the high frequency characteristics by shortening the length of the metal wire for grounding.

【０００７】[0007]

【課題を解決するための手段】本発明は、半導体素子を
マウント材により搭載するアイランド部の表面に半導体
素子の底面積よりも小さい面積の凹状部を形成し、この
凹状部にマウント材を介装し、この凹状部を覆うように
半導体素子を搭載した構成とする。この場合、凹状部は
その縦横寸法が半導体素子の縦横寸法よりも小さくさ
れ、更に凹状部の容積は、マウント材の体積に略等しく
される。また、凹状部は、その一辺以上の辺において半
導体素子の外側に張り出す凹溝部を有する構成としても
よい。According to the present invention, a concave portion having an area smaller than a bottom area of a semiconductor element is formed on a surface of an island portion on which a semiconductor element is mounted by a mount material, and the mount material is interposed in the concave portion. Then, the semiconductor element is mounted so as to cover the concave portion. In this case, the vertical and horizontal dimensions of the concave portion are made smaller than the vertical and horizontal dimensions of the semiconductor element, and the volume of the concave portion is made substantially equal to the volume of the mount material. In addition, the recessed portion may have a recessed groove portion that extends to the outside of the semiconductor element at one or more sides thereof.

【０００８】[0008]

【作用】半導体素子をアイランド部の表面上に搭載する
一方で、凹状部によりマウント材が半導体素子の周辺部
に流れ出すことが防止され、金属ワイヤを半導体素子の
直近のタブの表面位置にボンディングでき、金属ワイヤ
の短縮を可能とする。The semiconductor element is mounted on the surface of the island portion, while the concave portion prevents the mount material from flowing out to the peripheral portion of the semiconductor element, and the metal wire can be bonded to the surface position of the tab in the immediate vicinity of the semiconductor element. Allows shortening of metal wires.

【０００９】[0009]

【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の一実施例の半導体装置の要部の構成
を示す断面図であり、リードフレーム１のタブ２上に半
導体素子３を搭載し、この半導体素子３の電極３ａとイ
ンナーリード４、及び接地用電極３ｂとタブ２をそれぞ
れ金属ワイヤ５で接続し、かつこれらを樹脂６で封止し
た構成の半導体装置とされている。図２はその要部を拡
大した平面図とそのＡ−Ａ線断面図である。前記リード
フレーム１は、Ｆｅ−Ｎｉ合金あるいはＣｕ系合金から
なる板材をプレス加工もしくはエッチング加工により所
要の形状とし、前記タブ２とインナーリード４を形成す
る。そして、前記タブ２の表面には半導体素子の底面積
よりも小さい凹状部７、即ち、半導体素子３の縦横寸法
よりも小さい縦横寸法の凹状部を形成する。The present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing a configuration of a main part of a semiconductor device according to an embodiment of the present invention. A semiconductor element 3 is mounted on a tab 2 of a lead frame 1, electrodes 3a and inner leads 4 of the semiconductor element 3 are mounted. , And the grounding electrode 3b and the tab 2 are respectively connected by a metal wire 5, and these are sealed with a resin 6 to provide a semiconductor device. FIG. 2 is an enlarged plan view of an essential part and a sectional view taken along the line AA. The lead frame 1 is formed by pressing or etching a plate material made of an Fe-Ni alloy or a Cu-based alloy into a desired shape to form the tab 2 and the inner lead 4. Then, a concave portion 7 smaller than the bottom area of the semiconductor element, that is, a concave portion having vertical and horizontal dimensions smaller than the vertical and horizontal dimensions of the semiconductor element 3 is formed on the surface of the tab 2.

【００１０】この場合、凹状部７は半導体素子３をタブ
２にマウントするときの位置精度のばらつきを考慮し、
マウント位置精度分小さい面積とする。また、この凹状
部７の深さはリードフレーム１の板材の厚さの１／４〜
３／４程度であり、結果として半導体素子３をマウント
する際に用いるマウント材の体積に略等しい容積となる
ようにする。なお、この凹状部７の形成に際しては、プ
レス加工もしくはエッチング加工により設けることがで
き、前記タブ２やインナーリード４の形成と同時に形成
することが可能である。また、タブ２及びインナーリー
ド４の表面には貴金属めっきを施しておく。In this case, the concave portion 7 takes into consideration variations in positional accuracy when the semiconductor element 3 is mounted on the tab 2,
The area should be smaller than the mounting position accuracy. The depth of the concave portion 7 is 1/4 of the thickness of the plate material of the lead frame 1 to
It is about 3/4, and as a result, the volume is made to be approximately equal to the volume of the mount material used when mounting the semiconductor element 3. The concave portion 7 can be formed by pressing or etching, and can be formed simultaneously with the formation of the tab 2 and the inner lead 4. In addition, the surfaces of the tabs 2 and the inner leads 4 are plated with noble metal.

【００１１】そして、タブ２に半導体素子３をマウント
するために、凹状部７内にマウント材８を流し込む。こ
のとき、マウント材８は表面張力によって凹状部７内に
おいてタブ２の表面上から多少盛り上がる程度の量に制
御する。その後、このマウント材８が盛り上がったとこ
ろに半導体素子３を載置し、マウントする。このとき、
マウント材８は前記した量に制御しているため、半導体
素子３の底面と凹状部７との間から半導体装置３の周囲
に流れ出すマウント材８を最小に抑えることができ、凹
状部７の周囲のタブ表面にマウント材８が大きく広がる
ことはない。Then, in order to mount the semiconductor element 3 on the tab 2, a mount material 8 is poured into the concave portion 7. At this time, the mount material 8 is controlled by surface tension so that the mount material 8 is slightly raised from the surface of the tab 2 in the concave portion 7. Thereafter, the semiconductor element 3 is placed and mounted on the place where the mount material 8 rises. At this time,
Since the mount material 8 is controlled to the above-described amount, the mount material 8 flowing out between the bottom surface of the semiconductor element 3 and the recessed portion 7 to the periphery of the semiconductor device 3 can be minimized, and the periphery of the recessed portion 7 can be minimized. The mount material 8 does not greatly spread on the tab surface of the.

【００１２】したがって、半導体素子３の接地用電極３
ａを金属ワイヤ５によりタブ２にボンディングを行う場
合、金属ワイヤ５のタブ２への接続箇所を凹状部７の近
傍位置に設定してもマウント材８によりボンディングが
阻害されることがなくなり、結果として最短のワイヤル
ープで接続することができ、金属ワイヤ５の長さを最短
にすることができる。これにより高周波特性を改善する
ことができる。また、この構成では、半導体素子３はタ
ブ２の表面上にマウントできるため、図６に示した凹状
部内にマウントする場合に比較して半導体素子３の表面
高さが低くされることはなく、特にインナーリード４に
接続を行うための金属ワイヤ５が撓んだときにタブ２の
エッジに接触して電気的に短絡することを有効に防止す
る。更に、この構成によれば、タブ２に対する半導体素
子３のマウント位置精度が低くても、半導体素子３が凹
状部７を覆う位置にさえマウントされていれば、前記し
た効果を得ることができ、マウント精度によって金属ワ
イヤ５の長さが影響されることはない。Therefore, the grounding electrode 3 of the semiconductor element 3
When a is bonded to the tab 2 by the metal wire 5, even if the connection position of the metal wire 5 to the tab 2 is set in the vicinity of the concave portion 7, the bonding is not hindered by the mount material 8. Can be connected by the shortest wire loop, and the length of the metal wire 5 can be minimized. Thereby, the high frequency characteristics can be improved. Further, in this configuration, since the semiconductor element 3 can be mounted on the surface of the tab 2, the surface height of the semiconductor element 3 is not lowered as compared with the case where the semiconductor element 3 is mounted in the concave portion shown in FIG. The metal wire 5 for connecting to the inner lead 4 is effectively prevented from coming into contact with the edge of the tab 2 and electrically short-circuiting when the metal wire 5 is bent. Further, according to this structure, even if the mounting position accuracy of the semiconductor element 3 with respect to the tab 2 is low, the above-described effect can be obtained as long as the semiconductor element 3 is mounted even at a position covering the concave portion 7, The mounting accuracy does not affect the length of the metal wire 5.

【００１３】図３は本発明の第２実施例の要部の平面図
及びＢ−Ｂ線断面図であり、第１実施例と同一部分には
同一符号を付してある。この実施例ではタブ２の表面に
形成する凹状部７の形状を第１実施例のものとは相違さ
せてある。即ち、凹状部７を半導体素子３の縦横寸法よ
りも小さく形成する点では同じであるが、金属ワイヤ５
を接続しない１つの辺或いは対向する２つの辺に、半導
体素子３の外側にはみ出す凹溝部９を凹状部７に連続し
て形成している。FIG. 3 is a plan view and a sectional view taken along line BB of the essential part of the second embodiment of the present invention, in which the same parts as those in the first embodiment are designated by the same reference numerals. In this embodiment, the shape of the concave portion 7 formed on the surface of the tab 2 is different from that of the first embodiment. That is, it is the same in that the concave portion 7 is formed smaller than the vertical and horizontal dimensions of the semiconductor element 3, but the metal wire 5
A concave groove portion 9 protruding outside the semiconductor element 3 is formed continuously with the concave portion 7 on one side that does not connect the two or opposite two sides.

【００１４】この凹溝部９を形成することにより、凹状
部７にマウント材８を盛り上げ、その上に半導体素子３
を載置してマウントを行った際に、マウント材８が凹状
部７の周辺に逃げる際に、マウント材８が凹溝部９に逃
げるようになり、タブ２の表面上に広がることをより有
効に防止できる。これにより、前記実施例に比較してマ
ウント材８の量に多少の誤差が生じている場合でもマウ
ント材８がタブ２の表面上に全く広がらない状態で半導
体素子３をタブ２にマウントすることが可能となり、マ
ウント材８の量の管理が容易になるとともに、タブ２に
接続する金属ワイヤ５の短縮化を更に進めることが可能
となる。なお、前記実施例では樹脂封止型の半導体装置
に本発明を適用した例を示しているが、図４に示すよう
に、セラミックで構成されたベース部１０やキャップ部
１１で構成されるセラミックパッケージ型の半導体装置
においても本発明を同様に適用でき、これにより接地用
の金属ワイヤを最短ボンディングすることができ、半導
体装置の高周波特性を改善することが可能となる。By forming the concave groove portion 9, the mount material 8 is raised in the concave portion 7 and the semiconductor element 3 is formed thereon.
When the mount material 8 is mounted and mounted, when the mount material 8 escapes to the periphery of the concave portion 7, the mount material 8 escapes to the concave groove portion 9, and it is more effective to spread on the surface of the tab 2. Can be prevented. As a result, the semiconductor element 3 is mounted on the tab 2 in a state in which the mount material 8 does not spread over the surface of the tab 2 at all even when the amount of the mount material 8 is slightly different from that in the above-described embodiment. Therefore, the amount of the mount material 8 can be easily controlled, and the metal wire 5 connected to the tab 2 can be further shortened. Although the above-described embodiment shows an example in which the present invention is applied to a resin-encapsulated semiconductor device, as shown in FIG. 4, a ceramic composed of a base portion 10 and a cap portion 11 made of ceramics. The present invention can be similarly applied to a package-type semiconductor device, whereby the metal wire for grounding can be bonded for the shortest time, and the high frequency characteristics of the semiconductor device can be improved.

【００１５】因みに、従来と同一規格の半導体装置に本
発明を適用したところ、従来では金属ワイヤの長さが７
００μｍで、そのアイソレーションが−２１．５ｄＢで
あったのに対し、本発明においては金属ワイヤの長さを
３００μｍに短縮でき、かつそのアイソレーションが−
２３．５ｄＢに改善されたことが確認された。Incidentally, when the present invention is applied to a semiconductor device of the same standard as the conventional one, the length of the metal wire is 7 in the conventional one.
In the present invention, the length of the metal wire can be shortened to 300 μm, and the isolation is −21.5 dB.
It was confirmed that it was improved to 23.5 dB.

【００１６】[0016]

【発明の効果】以上説明したように本発明は、アイラン
ド部の表面に半導体素子の底面積よりも小さい面積の凹
状部を形成し、この凹状部にマウント材を介装し、この
凹状部を覆うように半導体素子を搭載しているので、半
導体素子をアイランド部の表面上に搭載して金属ワイヤ
による短絡を防止する一方で、凹状部によりマウント材
が半導体素子の周辺部に流れ出すことが防止され、金属
ワイヤを半導体素子の直近のタブの表面位置にボンディ
ングでき、金属ワイヤの短縮を可能とし、その高周波特
性を改善することができる効果がある。また、凹状部
は、その一辺以上の辺において半導体素子の外側に張り
出す凹溝部を有する構成とすることで、マウント材の量
に多少の誤差が生じている場合でもマウント材がタブの
表面上に全く広がらない状態で半導体素子をタブにマウ
ントすることが可能となり、マウント材の量の管理が容
易になるとともに、タブに接続する金属ワイヤを短縮化
を更に進めることが可能となる。As described above, according to the present invention, a concave portion having an area smaller than the bottom area of the semiconductor element is formed on the surface of the island portion, a mount material is interposed in the concave portion, and the concave portion is formed. Since the semiconductor element is mounted so as to cover it, the semiconductor element is mounted on the surface of the island to prevent a short circuit due to the metal wire, while the concave portion prevents the mount material from flowing out to the peripheral portion of the semiconductor element. Thus, there is an effect that the metal wire can be bonded to the surface position of the tab in the immediate vicinity of the semiconductor element, the metal wire can be shortened, and its high frequency characteristic can be improved. In addition, the concave portion is configured to have a concave groove portion that protrudes to the outside of the semiconductor element at one or more sides thereof, so that even if there is some error in the amount of the mount material, the mount material is on the surface of the tab. It is possible to mount the semiconductor element on the tab in a state where it does not spread at all, and it becomes possible to easily control the amount of mounting material and further shorten the metal wire connected to the tab.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例の全体構成を示す断面図であ
る。FIG. 1 is a sectional view showing the overall configuration of an embodiment of the present invention.

【図２】図１の要部の平面図とそのＡ−Ａ線断面図であ
る。FIG. 2 is a plan view of a main part of FIG. 1 and a cross-sectional view taken along the line AA.

【図３】本発明の第二実施例の要部の平面図とそのＢ−
Ｂ線断面図である。FIG. 3 is a plan view of the essential part of the second embodiment of the present invention and its B-
It is a B sectional view.

【図４】本発明が適用可能な他の種類の半導体装置の全
体構成の断面図である。FIG. 4 is a cross-sectional view of the overall configuration of another type of semiconductor device to which the present invention can be applied.

【図５】従来の半導体装置の一部の断面図である。FIG. 5 is a partial cross-sectional view of a conventional semiconductor device.

【図６】従来の改善された半導体装置の一部の断面図で
ある。FIG. 6 is a partial cross-sectional view of a conventional improved semiconductor device.

【符号の説明】[Explanation of symbols]

１ リードフレーム ２ タブ（アイランド部） ３ 半導体素子 ４ インナーリード ５ 金属ワイヤ ７ 凹状部 ８ マウント材 1 lead frame 2 tab (island part) 3 semiconductor element 4 inner lead 5 metal wire 7 concave part 8 mounting material

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体素子をマウント材によりアイラン
ド部に搭載し、前記半導体素子の電極とアイランド部と
を金属ワイヤによりボンディングする半導体装置におい
て、前記アイランド部の表面に半導体素子の底面積より
も小さい面積の凹状部を形成し、この凹状部にマウント
材を介装し、この凹状部を覆うように前記半導体素子を
搭載したことを特徴とする半導体装置。1. A semiconductor device in which a semiconductor element is mounted on an island portion by a mount material, and an electrode of the semiconductor element and the island portion are bonded by a metal wire. The surface area of the island portion is smaller than the bottom area of the semiconductor element. A semiconductor device, wherein a concave portion having an area is formed, a mount material is interposed in the concave portion, and the semiconductor element is mounted so as to cover the concave portion. 【請求項２】 凹状部はその縦横寸法が半導体素子の縦
横寸法よりも小さくされてなる請求項１の半導体装置。2. The semiconductor device according to claim 1, wherein the vertical and horizontal dimensions of the concave portion are smaller than the vertical and horizontal dimensions of the semiconductor element. 【請求項３】 凹状部の容積は、マウント材の体積に略
等しい請求項２の半導体装置。3. The semiconductor device according to claim 2, wherein the volume of the concave portion is substantially equal to the volume of the mount material. 【請求項４】 凹状部は、その一辺以上の辺において半
導体素子の外側に張り出す凹溝部を有する請求項１また
は２の半導体装置。4. The semiconductor device according to claim 1, wherein the recessed portion has a recessed groove portion that extends to the outside of the semiconductor element at one or more sides thereof. 【請求項５】 金属ワイヤが半導体素子の直近のタブの
表面位置にボンディングされてなる請求項１または４の
いずれかの半導体装置。5. The semiconductor device according to claim 1, wherein a metal wire is bonded to a surface position of the tab immediately adjacent to the semiconductor element.
JP5265410A 1993-09-30 1993-09-30 Semiconductor device Expired - Fee Related JP2536431B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5265410A JP2536431B2 (en) 1993-09-30 1993-09-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5265410A JP2536431B2 (en) 1993-09-30 1993-09-30 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH07106350A JPH07106350A (en) 1995-04-21
JP2536431B2 true JP2536431B2 (en) 1996-09-18

Family

ID=17416784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5265410A Expired - Fee Related JP2536431B2 (en) 1993-09-30 1993-09-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2536431B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3924481B2 (en) * 2002-03-08 2007-06-06 ローム株式会社 Semiconductor device using semiconductor chip
AU2003211644A1 (en) * 2002-03-08 2003-09-22 Rohm Co., Ltd. Semiconductor device using semiconductor chip
JP2007096042A (en) * 2005-09-29 2007-04-12 Rohm Co Ltd Semiconductor device
JP2007134395A (en) * 2005-11-08 2007-05-31 Rohm Co Ltd Semiconductor device
US9293435B2 (en) 2009-09-11 2016-03-22 Rohm Co., Ltd. Semiconductor device and production method therefor
JP6124521B2 (en) * 2012-07-03 2017-05-10 Ｎｇｋエレクトロデバイス株式会社 Power module substrate manufacturing method
JP7064325B2 (en) * 2017-12-18 2022-05-10 スタンレー電気株式会社 A semiconductor light emitting device and a method for manufacturing a semiconductor light emitting device using the semiconductor light emitting device.

Also Published As

Publication number Publication date
JPH07106350A (en) 1995-04-21

Similar Documents

Publication Publication Date Title
KR100294719B1 (en) Molded semiconductor device and method for manufacturing the same, lead frame
US7102210B2 (en) Lead frame, manufacturing method of the same, and semiconductor device using the same
JP2569939B2 (en) Resin-sealed semiconductor device
JP4091050B2 (en) Manufacturing method of semiconductor device
JP2536431B2 (en) Semiconductor device
JP3403699B2 (en) Semiconductor device and method of manufacturing semiconductor device
KR100491657B1 (en) Lead Frame, Semiconductor Device Using the Same and Method of Producing the Semiconductor Device
JP2001035961A (en) Semiconductor and manufacture thereof
JP2524482B2 (en) QFP structure semiconductor device
JP3424184B2 (en) Resin-sealed semiconductor device
JP3454192B2 (en) Lead frame, resin-sealed semiconductor device using the same, and method of manufacturing the same
JP2970626B2 (en) Lead frame for semiconductor integrated circuit device and semiconductor integrated circuit device
JP2001177007A (en) Semiconductor device and manufacturing method thereof
JPH0621304A (en) Manufacture of lead frame and semiconductor device
JPS61241954A (en) Semiconductor device
JP2920066B2 (en) Semiconductor device and manufacturing method thereof
JP3342292B2 (en) Semiconductor device
JP2906753B2 (en) Lead frame
JP3644555B2 (en) Lead frame and semiconductor device
JPH0366150A (en) Semiconductor integrated circuit device
JPH0677284A (en) Semiconductor device
JP2726523B2 (en) Lead frame and semiconductor device using the same
JPH11186465A (en) Semiconductor device and its manufacture
JPH077023A (en) Resin sealed semiconductor device
JP2700434B2 (en) Semiconductor device

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees