JPH0426213B2 - - Google Patents
Info
- Publication number
- JPH0426213B2 JPH0426213B2 JP59148108A JP14810884A JPH0426213B2 JP H0426213 B2 JPH0426213 B2 JP H0426213B2 JP 59148108 A JP59148108 A JP 59148108A JP 14810884 A JP14810884 A JP 14810884A JP H0426213 B2 JPH0426213 B2 JP H0426213B2
- Authority
- JP
- Japan
- Prior art keywords
- etching
- film
- holes
- dry etching
- plasma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 10
- 239000007789 gas Substances 0.000 claims description 6
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 5
- 229910001882 dioxygen Inorganic materials 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims 2
- 238000000034 method Methods 0.000 description 11
- 239000005380 borophosphosilicate glass Substances 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052774 Proactinium Inorganic materials 0.000 description 1
- -1 as a second step Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は、半導体素子の金属配線接続用のコン
タクトホール及びスルーホールのドライエツチン
グ方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a method for dry etching contact holes and through holes for connecting metal wiring in semiconductor devices.
半導体素子は、通常数層からなる半導体膜（単
結晶シリコン、多結晶シリコン）、金属膜（アル
ミニウム、モリブデン、タングステン）、及び絶
縁膜（SiO2、PSG、BSG、BPSG、プラズマSiN
等）を有して構成される。絶縁膜は、半導体と金
属膜、及び金属膜と金属膜の層間膜として用いら
れ、コンタクトホール、及びスルーホールと呼ば
れる接続孔を設ける必要がある。この接続孔は、
素子の高集積化に伴つて、微細化しつつあるた
め、ドライエツチングによつて加工されることが
多い。
Semiconductor devices usually consist of several layers of semiconductor films (monocrystalline silicon, polycrystalline silicon), metal films (aluminum, molybdenum, tungsten), and insulating films (SiO 2 , PSG, BSG, BPSG, plasma SiN).
etc.). The insulating film is used as an interlayer film between a semiconductor and a metal film, and between a metal film and a metal film, and it is necessary to provide connection holes called contact holes and through holes. This connection hole is
As devices become more highly integrated, they are becoming increasingly finer, so they are often processed by dry etching.
従来、接続孔のドライエツチングは、第14回半
導体集積回路シンポジウム講演論文集（1978）
P297〜302にあるように、CF4とH2の混合ガスも
しくは、CHF3単独ガスを用いて行なわれてい
た。従来の方法によりドライエツチングされた接
続孔は、第１図ａに示すように半導体基板１上の
BPSG膜２の上にパタニングしたホトレジスト膜
３を設け、このホトレジスト３をマスクとしてド
ライエツチングすると第１図ｂに示すような断面
形状となる。この場合、エツチングされた側面が
垂直であるため、BPSG膜２ｂの接続孔の開口部
において鋭い角を生じ、後の工程において、アル
ミニウム配線が段差部において薄くなつたり、断
線したりするという欠点があつた。 Conventionally, dry etching of connection holes has been described in Proceedings of the 14th Semiconductor Integrated Circuit Symposium (1978).
As shown in pages 297 to 302, this was done using a mixed gas of CF 4 and H 2 or a single gas of CHF 3 . The contact holes dry etched by the conventional method are formed on the semiconductor substrate 1 as shown in FIG. 1a.
A patterned photoresist film 3 is provided on the BPSG film 2, and dry etching is performed using this photoresist 3 as a mask, resulting in a cross-sectional shape as shown in FIG. 1b. In this case, since the etched side surface is vertical, a sharp corner is formed at the opening of the contact hole of the BPSG film 2b, which causes the disadvantage that the aluminum wiring becomes thinner at the stepped portion or breaks in the subsequent process. It was hot.
本発明の目的は、加工精度が高くかつ角が傾斜
した側面が得られる接続孔のドライエツチング方
法を提供することである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method of dry etching a connecting hole with high processing accuracy and with which side surfaces with inclined corners can be obtained.
本発明のドライエツチング方法は、半導体素子
のコンタクトホール、スルーホールをエツチング
する方法であつて、エツチング室に炭素を含む弗
素系のエツチングガスを導入し、上記コンタクト
ホール、スルーホールをプラズマエツチングした
後、真空排気を行ない、引き続き、同一エツチン
グ室内に、酸素ガスを導入し、開口部分に傾斜を
もつたコンタクトホール、スルーホールエツチン
グを行うことによつて構成される。
The dry etching method of the present invention is a method for etching contact holes and through holes in semiconductor devices, in which a fluorine-based etching gas containing carbon is introduced into an etching chamber, and the contact holes and through holes are plasma etched. After evacuating the etching chamber, oxygen gas is subsequently introduced into the same etching chamber, and contact holes and through holes with inclined openings are etched.
次に本発明の実施例を図面を用いて説明する。
第２図ａ，ｂ，ｃは本発明の一実施例を説明する
ための半導体素子の工程断面図である。第２図ｃ
以外は、第１図ａ，ｂと同じである。第２図ａに
おいて半導体基板１上に、絶縁膜としてのBPSG
膜２、エツチングマスクとしての開口部を有する
ホトレジスト膜３が形成されている。このように
形成された半導体素子をドライエツチング装置に
載置し、第１段階としてCHF3ガス流量20c.c.／
min、圧力10Pa、高周波電力1000Wの条件のもと
で第２図ｂに示すようにBPSG膜をプラズマエツ
チングする。次にエツチング室を圧力0.3Paまで
真空排気した後、第２段階として、エツチング室
に酸素ガスを導入し流量30c.c.／minとし、圧力
3.5Pa、高周波電力900Wの条件のもとで、ホトレ
ジスト膜、及びBPSG膜をプラズマエツチングす
る。その結果、接続孔の開口部分が第２図ｃに示
したようにホトレジスト膜３ａ、BPSG膜２ｂは
傾斜した形状が得られる。この場合、第２段階の
酸素ガスプラズマにより、BPSG膜がエツチング
される理由は、第１段階で、エツチング室に吸着
したCHF3ガスが酸素ガスプラズマ中に供給され
るためである。
Next, embodiments of the present invention will be described using the drawings.
FIGS. 2a, 2b, and 2c are cross-sectional views of the process of a semiconductor device for explaining an embodiment of the present invention. Figure 2c
Other than that, it is the same as FIG. 1a and b. In FIG. 2a, BPSG as an insulating film is placed on the semiconductor substrate 1.
A film 2 and a photoresist film 3 having an opening serving as an etching mask are formed. The semiconductor element formed in this way was placed in a dry etching device, and as a first step, CHF 3 gas flow rate of 20 c.c./
The BPSG film was plasma etched as shown in FIG. 2b under the following conditions: min, pressure of 10 Pa, and high frequency power of 1000 W. Next, after evacuating the etching chamber to a pressure of 0.3 Pa, as a second step, oxygen gas was introduced into the etching chamber at a flow rate of 30 c.c./min, and the pressure was
The photoresist film and the BPSG film are plasma etched under the conditions of 3.5 Pa and high frequency power of 900 W. As a result, the photoresist film 3a and the BPSG film 2b have an inclined shape, as shown in FIG. 2c, at the openings of the connection holes. In this case, the reason why the BPSG film is etched by the oxygen gas plasma in the second stage is that the CHF 3 gas adsorbed in the etching chamber is supplied into the oxygen gas plasma in the first stage.
上記実施例では、絶縁膜として、BPSG膜を用
いたが、他の絶縁膜、すなわちSiO2膜、PSG膜、
プラズマSiN膜に対しても本発明は適用可能であ
る。 In the above example, a BPSG film was used as the insulating film, but other insulating films, such as SiO 2 film, PSG film,
The present invention is also applicable to plasma SiN films.
以上詳細に説明したように、本発明のドライエ
ツチング方法によれば、絶縁膜の接続孔開口部分
が傾斜することになり、後の工程において、アル
ミニウム膜の段差部でのカバレージが良くなり、
半導体素子の信頼性の向上に対して大きな効果が
ある。
As explained in detail above, according to the dry etching method of the present invention, the connection hole opening portion of the insulating film is inclined, which improves the coverage of the stepped portion of the aluminum film in the subsequent process.
This has a great effect on improving the reliability of semiconductor devices.
第１図は、従来のドライエツチング方法を用い
た場合の工程断面図、第２図は、本発明の一実施
例を説明するための工程断面図である。
１……半導体基板、２……BPSG膜、３……ホ
トレジスト膜。
FIG. 1 is a cross-sectional view of a process when a conventional dry etching method is used, and FIG. 2 is a cross-sectional view of a process for explaining an embodiment of the present invention. 1... Semiconductor substrate, 2... BPSG film, 3... Photoresist film.
Claims (1)
ルの形成におけるドライエツチングにおいて、炭
素を含む弗素系のエツチングガスを導入し、コン
タクトホールやスルーホールをプラズマエツチン
グで形成した後、上記エツチングを遮断して真空
排気を行い、次に、同一エツチング室に、酸素ガ
スを導入し前記コンタクトホールやスルーホール
の開口部分に傾斜をもつた形状を形成するプラズ
マエツチングを行うことを特徴とするドライエツ
チング方法。1. In dry etching for forming contact holes and through holes in semiconductor devices, a fluorine-based etching gas containing carbon is introduced, contact holes and through holes are formed by plasma etching, and then the etching is interrupted and vacuum evacuation is performed. and then plasma etching is performed in which oxygen gas is introduced into the same etching chamber to form a sloped shape at the opening of the contact hole or through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14810884A JPS6127636A (en) | 1984-07-17 | 1984-07-17 | Dry etching process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14810884A JPS6127636A (en) | 1984-07-17 | 1984-07-17 | Dry etching process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6127636A JPS6127636A (en) | 1986-02-07 |
| JPH0426213B2 true JPH0426213B2 (en) | 1992-05-06 |
Family
ID=15445425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14810884A Granted JPS6127636A (en) | 1984-07-17 | 1984-07-17 | Dry etching process |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6127636A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2563180B2 (en) * | 1987-07-27 | 1996-12-11 | 日本電信電話株式会社 | Method for manufacturing semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57192030A (en) * | 1981-05-20 | 1982-11-26 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS58127329A (en) * | 1982-01-26 | 1983-07-29 | Seiko Epson Corp | Etching method for insulating protection film of semiconductor substrate |
-
1984
- 1984-07-17 JP JP14810884A patent/JPS6127636A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57192030A (en) * | 1981-05-20 | 1982-11-26 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS58127329A (en) * | 1982-01-26 | 1983-07-29 | Seiko Epson Corp | Etching method for insulating protection film of semiconductor substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6127636A (en) | 1986-02-07 |
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