JPH04261017A - Fabrication of thin film transistor array substrate - Google Patents

Abstract

PURPOSE:To ensure a high reliability electrode by forming an electrode pattern on a transparent substrate and thereafter forming an insulating film and an amorphous silicon film, and etching those films with mixed gas of sulfur hexafluoride gas and nitrogen trifluoride gas or carbon fluoride chloride gas in a plasma state at a predetermined flow rate ratio is oxygen. CONSTITUTION:A transparent conductive film is formed on a glass substrate 1 and unnecessary parts are eliminated through patterning to yield a picture element electrode 2. A gate electrode 3 is formed with high melting point metal such as chromium, etc. Further, a silicon nitride gate insulating film 4 and an amorphous silicon film 5 are formed in order to form a desired pattern, and the gate insulating film and the amorphous silicon film are etched. The taper etching is carried out in mixed gas of sulfur hexafluoride gas and nitrogen trifluoride gas or carbon fluoride chloride gas in a plasma state with oxygen gas of a 10-38% flow rate ratio.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor array substrate used in, for example, a liquid crystal display device, and in particular to improving the covering properties of its electrodes.

0002

[Prior Art] Figures 3 and 4 are, for example, published in Japanese Patent Application Laid-Open No. 62-326.
The conventional thin film transistor (hereinafter referred to as
1 is a plan view and a cross-sectional view showing an array substrate (referred to as TFT); FIG. In the figure, 1 is a substrate made of a transparent insulating material such as glass, 2 is a pixel electrode made of a transparent conductive film formed on the substrate 1, 3 is a gate electrode, 4 is a gate insulating film, 5 is an amorphous silicon film, and 6 is a pixel electrode made of a transparent conductive film formed on the substrate 1. is a source electrode, and 7 is a drain electrode, and these electrodes 3 to 7 form a TFT. Such a TFT array substrate is manufactured through the following steps. First, a transparent conductive film layer is formed on the substrate 1 by sputtering or vapor deposition, and a pixel electrode 2 with a predetermined pattern is formed by photolithography and etching. Next, a conductive film is formed on the substrate 1 by sputtering, and then photolithography is performed in the same manner. Gate electrode 3 is formed by lithography and etching. Next, a gate insulating film 4 and an amorphous silicon film 5 are successively formed in this order by plasma CVD, and then the gate insulating film 4 and amorphous silicon film 5 are formed into a predetermined pattern by photolithography and anisotropic etching. Finally, amorphous silicon film 5
A conductive film is formed thereon by sputtering, and unnecessary conductive films are removed by photolithography and etching to form a source electrode 6 and a drain electrode 7.

[0003] Such a TFT functions as a switching element that is activated by applying a voltage to the gate electrode 3 and the source electrode 6, and supplies charge to the pixel electrode 2 through the drain electrode 7. Therefore, in order to supply charge to the pixel electrode 2, the gate electrode 3, the source electrode 6
It is minimum necessary that the drain electrode 7 and drain electrode 7 are not disconnected.On the other hand, when this TFT array substrate is used for a liquid crystal display device, for example, about 1 million TFTs in one liquid crystal display device are used. It is necessary for all of them to work, and it is necessary to extremely reduce the incidence of disconnection defects in the electrodes.

0004

[Problem to be Solved by the Invention] The conventional TFT is constructed as described above, and the gate insulating film 4 is formed in the same pattern.
The amorphous silicon film 5 is continuously etched. Therefore, when anisotropic vertical etching is performed using reactive ion etching, the shape of the etched step becomes steep, causing the problem that the source and drain electrodes formed later become constricted at the etching step, making wire breakage more likely. there were.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a TFT array substrate in which highly reliable electrodes can be stably formed.

[0006]

[Means for Solving the Problems] A method for manufacturing a TFT array substrate according to the present invention includes forming a gate insulating film and an amorphous silicon film using sulfur hexafluoride gas, nitrogen trifluoride gas, or carbon fluorochloride gas in a plasma state. Flow rate ratio 10~
The structure is such that etching is performed using 38% oxygen gas.

[0007]

[Operation] In the manufacturing method according to the present invention, since the taper angle of the etched step part can be controlled, the taper angle can be set to the maximum required for coverage, and as a result, it is not necessary to increase the pattern size due to the tapered shape. This can be minimized, and disconnection of the conductive film formed on the tapered shape can be suppressed.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of the structure of a TFT showing an embodiment of the present invention. After forming a transparent conductive film of indium tin oxide or the like obtained by a thin film forming method such as sputtering or vapor deposition on the glass substrate 1, unnecessary parts of the transparent conductive film are etched away through a patterning process to form pixels. This is called electrode 2. Next, the gate electrode 3 is formed using a high melting point metal such as chromium obtained by sputtering. After sequentially laminating a gate insulating film made of silicon nitride and an amorphous silicon film thereon using a plasma CVD method, a desired pattern is formed, and the gate insulating film and amorphous silicon film are sequentially etched using a plasma etching method. Obtain a tapered etched cross section. Taper etching is performed using, for example, sulfur hexafluoride gas (SF6 gas) and oxygen gas (O2 gas).
This is carried out by exposing the substrate to plasma using a mixed gas (gas), and a parallel plate type electrode device is usually used as the plasma generator. Finally, a source electrode 6 and a drain electrode 7 made of aluminum or the like are formed by sputtering.

FIG. 2 shows the relationship between the taper angle obtained by such a manufacturing method and the O2 gas composition. When the O2 gas composition is less than 10%, it becomes difficult to obtain a desired pattern shape; If the taper angle exceeds 60 degrees, the source electrode 6 and drain electrode 7 formed on the gate insulating film 4 and the amorphous silicon film 5 are likely to be disconnected.

In the TFT array substrate configured as described above, taper etching is performed in the process of sequentially etching the gate insulating film 4 and the amorphous silicon film 5, so that the source electrode 6 and drain electrode 7 formed later are The coverage is improved, no constriction occurs at the etched step portion, the number of disconnections in the source electrode 6 and drain electrode 7 is significantly reduced, and a defect-free TFT array substrate can be formed with a high yield. Also,
Since the taper angle can be controlled by adjusting the O2 gas composition, the increase in pattern size due to taper can be minimized, and a highly reliable electrode can be made stably without reducing the effective area of the pixel electrode 2. can be obtained.

[0011] In the above embodiment, SF6 gas and O2
A mixture of gases was used, but nitrogen trifluoride gas (NF3 gas) or CF2Cl gas was used instead of SF6 gas.
Taper etching can be similarly performed using a fluorochlorinated carbon gas such as No.2.

0012

As described above, according to the present invention, the gate insulating film and the amorphous silicon film are heated using a plasma state of sulfur hexafluoride gas, nitrogen trifluoride gas, or a mixture of carbon fluorochloride gas and oxygen gas. Since the electrode is etched by etching, the coverage of the electrode at the etched cross section is improved, making it possible to suppress the occurrence of wire breakage, and by controlling the taper angle, it is possible to minimize the increase in pattern size. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a TFT array substrate formed by a manufacturing method that is an embodiment of the present invention.

FIG. 2 is a characteristic diagram showing the relationship between taper angle and oxygen gas composition in the present invention.

FIG. 3 is a plan view showing the configuration of a conventional TFT array substrate.

FIG. 4 is a sectional view taken along line IV-IV in FIG. 3;

[Explanation of symbols]

1 Insulating substrate 2 Pixel electrode 3 Gate electrode 4 Gate insulating film 5 Amorphous silicon film 6 Source electrode 7 Drain electrode

Claims (1)

[Claims] 1. After forming an electrode pattern on a transparent substrate, an insulating film and an amorphous silicon film are laminated, and these are mixed with sulfur hexafluoride gas, nitrogen trifluoride gas, or carbon fluoride chloride gas in a plasma state at a flow rate ratio of A method for manufacturing a thin film transistor array substrate, characterized in that etching is performed using a mixed gas with 10 to 38% oxygen gas.