JPH04260351A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable the number of wires which has pass a wiring region which is provided at a semiconductor chip to be reduced by using a block passing wire which is formed by connecting an extra feed-through wire which remains within a third functional block. CONSTITUTION:There are a microcomputer core 2 as a first functional block, a plurality of peripheral I/O cells 3 as a second functional block, and a random logic portion 5 on a semiconductor chip 1, where remaining feed-through wires which are not used for wiring within the third functional blocks 4 and 5 are joined at a wiring layer between the functional cells and a block passing wire passing through the third functional block in a vertical row direction or a horizontal row direction is formed and then is used for connecting the first functional block 2 and the second functional block 3. Therefore, the number of wires passing through the wiring regions 6 and 7 is reduced so that the third functional blocks 4 and 5 may be avoided.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuit devices, and more particularly to improvements in the layout and wiring of integrated circuits designed using a cell-based method.

0002

2. Description of the Related Art FIG. 5 is a diagram showing wiring for connecting a plurality of functional blocks in a conventional example. (hereinafter abbreviated as microcomputer core), peripheral input/output cell 3 which is the second functional block,
Random logic section (A) 4 which is the third functional block
There is a random logic section (B) 5, and a microcontroller core 2.
Wiring 401 electrically connects the and peripheral input/output cells 3,
There is 501. Further, as shown in the figure, a wiring 401 connecting the first functional block 2 and the second functional block 3
, 501 avoids the third functional blocks 4, 5 (only this case is shown) in the direction where the third functional blocks 4, 5 are located, wiring area (A) 6, wiring area (B) 7.
and is arranged in the wiring area (C) 8.

0003

[Problems to be Solved by the Invention] Since the conventional semiconductor integrated circuit device is constructed as described above, there is a problem that there is a 3 functional blocks 4 and 5 are arranged,
Wiring lines 401 and 501 connecting the first functional block 2 and the second functional block 3 must be arranged to avoid the third functional blocks 4 and 5, so the wiring layout becomes complicated and the wiring area 6 , 7 and 8 increase, which poses a problem in that it impedes higher integration of the semiconductor chip 1.

[0004] This invention was made to solve the above-mentioned problems, and it facilitates the wiring layout for connecting the first functional block and the second functional block, and reduces the number of wiring lines in the wiring area. The object of the present invention is to obtain a semiconductor integrated circuit device with improved performance.

[0005]

[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention provides at least a first and a second electrically connected circuit.
It consists of a functional block, a third functional block placed between them, and a wiring area through which wiring connecting the first and second functional blocks passes, and a plurality of Functional cells are arranged so that they are in close contact in the parallel direction and in a vertical step shape with wiring layers in the column direction, or so that they are in close contact in the series direction and in a horizontal step shape with wiring layers in the horizontal direction. The plurality of functional cells have vertical or horizontal feed-through wiring that is not electrically connected to the inside of the functional cells, and the remaining wiring is not used for wiring in the third functional block. Feed-through wiring is connected in wiring layers between functional cells to form block passing wiring that passes through the third functional block in the column direction or the horizontal direction.

[0006]

[Function] Since the present invention has the above structure, the number of wires passing through the wiring area provided on the semiconductor chip can be reduced or eliminated, and the semiconductor chip can be highly integrated and the chip size can be reduced.

[0007]

Embodiment FIG. 1 is a diagram illustrating wiring for electrically connecting a plurality of functional blocks in a semiconductor integrated circuit device according to an embodiment of the present invention. There are a microcomputer core 2 as a functional block, a plurality of peripheral input/output cells 3 as a second functional block, and a random logic section (A) 4 and a random logic section (B) 5 as a third functional block. Furthermore, among the wiring from the microcomputer core 2 to the plurality of peripheral input/output cells 3, the wiring 401 going to the top and the wiring 502 going to the top right in the figure are all arranged in random logic sections ( The wiring 501 passing through the block passing wiring in A) 4 and going to the right is arranged so as to pass through the block passing wiring in the random logic section (B) 5, which also runs in the horizontal direction when viewed from the microcomputer core 2. Therefore, the wiring 401 no longer needs to pass through the wiring area (A) 6 and the wiring area (B) 7, and the wiring 501
The wiring area (C) 8 through which the line passed is no longer necessary.

FIG. 2 schematically shows the third functional blocks (A) 4 and (B) 5 of the semiconductor integrated circuit device according to the above embodiment. Functional cells are arranged in a vertically oriented step-like manner with interconnection layers sandwiched between a plurality of functional cells in the column direction and in close contact in the parallel direction. In the figure, the wiring for configuring the original function is omitted. Of the functional cells configuring the random logic section 4 or 5, 41 has 10 feed-through wirings, and 42 has 11 feed-through wirings. but,
43, each of the 12 feed-through wires remains unused, and these feed-through wires are joined together to form one block passing wire 13, so the size of the functional block itself does not change.

Further, FIG. 3 shows, as an example, a functional cell 41 constituting random logic sections 4 and 5, which is the third functional block of the semiconductor integrated circuit device according to the above embodiment. Function is inverter, 1 feed through wiring 10
It is equipped with

Generally, in a semiconductor integrated circuit device in which a plurality of large functional blocks are assembled, the problem is how to arrange wiring between the blocks. , shows an example of a pattern arrangement method such as a cell-based method in which basic cells having feed-through wiring are prepared in advance. The figure shows a state in which a plurality of functional cells, which are its constituent elements, are arranged in close contact in the parallel direction and in vertical steps with wiring layers sandwiched in the column direction. , 5, the block passing wiring of the wirings 401 and 502 in FIG. 1 was realized by the functional cells arranged in this manner. On the other hand, the block-passing wiring portion of the wiring 501 is the same example rotated by 90 degrees, that is, a plurality of functional cells are arranged in close contact in the serial direction and in horizontal steps with wiring layers in the horizontal direction. It is something.

That is, when arranging and wiring in the usual cell-based method, a maximum of three wirings can be arranged in the horizontal direction in the wiring area 410 between functional cells, and the vertical spacing between functional cells is determined by this. In the figure, there is still room for other wiring in other parts of the wiring area 410, such as area A 411 and area B 412. The vertical wiring in the functional cells having such a configuration is, for example, from functional cells 45 to 46.
The wiring 404 connected to the functional cell 46 is also connected to the functional cell 47 via an internal wiring 405, but this internal wiring 405 is connected to the signal input pin of the logic gate that constitutes the functional cell 46. Also serves as input wiring. On the other hand, external signals to be connected to the functional cell 49 are
It is connected through a feed-through wiring 406 inside. In this way, vertical wiring is divided into two types: one in which the internal wiring of the functional cell also serves as a signal input to the logic gate, and one in which the feed-through wiring within each functional cell is utilized.

FIG. 4(b) shows the wiring situation between these functional cells, for example, a functional cell 420 configured with NAND and N
A specific wiring example is shown using a functional cell 421 configured with an OR. In the figure, both functional cells are
One signal output wiring each on the output side and signal input wiring 422, 423, 424 and 425, 426, 427 on the input side
Each has 3 pieces. First, for input A, signal input wiring 4
23 is a signal input wiring to the signal input pin of the NAND gate 420, and is also an internal wiring that continues to the NOR gate 421. The NOR gate 421 also serves as a signal input wiring 426 of a signal input pin, and continues to the next stage functional cell. Similarly, for input B, the signal input wiring 425 and the signal input wiring 422 constitute an internal wiring, and simultaneously function as signal input wiring to the signal input pin of each gate. However, at input C, since the NAND gate 420 does not have a signal input pin, the signal input line 424 passes through the functional cell as a feed-through line, is connected to the NOR gate 421, and is then connected to the next signal input line 427 by the signal input line 427. Continuing to the next cell.

[0013] As described above, the vertical internal wiring within a functional cell can be divided into two types: those that also serve as signal input wiring to the signal input pins of the functional cell, and those that utilize feed-through wiring. , which naturally leaves unused feedthrough wiring. In the third functional blocks (A) 4 and (B) 5 in FIG. 2, the block passing wiring 13 is formed by joining these unused feed-through wirings in areas with room, such as the A area 402. By using the block passing wiring in the third functional block in the column direction or the horizontal direction, the number of wiring passing through the wiring areas (A) 6 and (B) 7 shown in FIG. 1 is reduced. However, it is possible to form a semiconductor chip 1 with no wiring region (C), a high degree of integration, and easy wiring layout.

[0014] In this embodiment, as described above, the third functional block is constructed by joining the remaining feed-through wiring that is not used for wiring in the third functional blocks 4 and 5 in the wiring layer between the functional cells. Since the block passing wiring that passes in the column direction or the horizontal direction is formed and used to connect the first functional block 2 and the second functional block 3, the wiring area is The number of wires passing through the wires 6 and 7 is reduced, and there are no wires that pass through the wire region 8, making the wire layout easier. Also, the area of the wire regions 6 and 7 is reduced, and the wire region 8 is no longer necessary. The semiconductor chip 1 can be highly integrated and the chip size can be reduced without changing the size of the functional blocks themselves.

Note that this embodiment is particularly effective when the first functional block is a microcomputer core or the like, and there are many wirings such as port outputs going to the third functional block.

[0016]

As described above, according to the present invention, by using the block passing wiring formed by joining the surplus feedthrough wiring in the third functional block,
The wiring that electrically connects the first functional block and the second functional block is routed through the third functional block located between the first functional block and the second functional block. It is possible to pass through the wiring without changing it, reduce the number of wires passing through the wiring area and the wiring area itself, and have the effect of achieving higher integration and smaller chip size of semiconductor chips.

[Brief explanation of the drawing]

FIG. 1 is a wiring diagram for electrically connecting a plurality of functional blocks in a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a third functional block in the semiconductor integrated circuit device according to the above embodiment.

FIG. 3 is a diagram showing an example of functional cells forming random logic in the semiconductor integrated circuit device according to the above embodiment.

FIG. 4 is a diagram showing an example of a pattern arrangement method in which basic cells having feed-through wiring are prepared in advance in a cell-based method or the like in the semiconductor integrated circuit device according to the above embodiment, and a specific wiring situation between each cell; be.

FIG. 5 is a wiring diagram for electrically connecting a plurality of functional blocks in a conventional semiconductor integrated circuit device.

[Explanation of symbols]

1 Semiconductor chip 2 Microcomputer core 3 which is the first functional block
Peripheral input/output cell 4, which is the second functional block
Random logic A5, which is the third functional block
Random logic B6, which is the third functional block
Wiring area A7 in the semiconductor chip Wiring area B10, 11, 12 in the semiconductor chip Feed-through wiring 13 Block passing wiring 41, 42, 43, 44, 45, 46, 47, 48, 4
9 Functional cells 401, 501, 502 Wiring 404 connecting the first functional block and second functional block Wiring 405 in the wiring area between functional cells
Internal wiring of functional cells 406 Feed-through wiring 410, 411, 412 Wiring area between functional cells 420 NAND gate 421 NOR gate 422, 423, 424 Signal input wiring of NAND gate 425, 426, 427 Signal input wiring of NOR gate

Claims (1)

[Claims] Claim 1: A first functional block, a second functional block, a third functional block disposed between the two blocks, and the first functional block and the second functional block. In a semiconductor integrated circuit device, a plurality of functional cells constituting the third functional block are arranged in vertical stages with wiring layers in close contact with each other in the parallel direction and with wiring layers in the column direction. Feed-through wiring in the column direction or row direction is arranged so that the series direction is in close contact with each other and the row direction is arranged in a horizontal step shape across the wiring layer, and there is no electrical connection to the inside of the functional cell. A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is provided on the functional cell, and the wiring is connected in a wiring layer between the functional cells to form a wiring that passes through the third functional block in a column direction or a row direction. .