JP2001313340A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that can easily modify the terminal connection of an LSI chip to a target package, that has a different number of terminals from the LSI chip, especially for QFP. SOLUTION: Lead-in wiring 211 to 216 for an external terminal, that are connected to external terminals 201 to 206, and lead-in wirings 221 to 226 for an internal circuit that are connected to the internal circuit are set to the same wiring layer, wiring segments 241 to 243 for lead-in wiring connection on two wiring layers for holding the wiring between the wiring segments are alternately arranged in upper and lower layers so that the two wiring layers cross the lead-in wiring for the internal circuit, and one of the two wiring layers crosses the lead-in wiring for the external terminal, and the arrangement of contacts 231 to 234 for connecting the wiring layers is changed, thus modifying the connection relationship between the internal circuit and external terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to an improvement in a circuit for connecting external terminals in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In order to shorten the design period of a semiconductor integrated circuit, a method of performing system verification by prototyping using a multifunctional integrated circuit is effective. In this case, since the integrated circuit is a multifunctional integrated circuit, the number of terminals of the LSI for prototyping is larger than that of the target integrated circuit, and it is often impossible to mount the LSI on an actual board.
As a solution to this, conventionally, a method has been used in which an LSI is first mounted on a relay board and connected to a board (motherboard) via the relay board.

However, with this method, there is a case where the relay board cannot be installed due to dimensional restrictions on the motherboard. Therefore, a method of mounting the LSI chip on a motherboard by sealing the LSI chip in a target package without connecting the unused terminals is conceivable. For example, CSP (cell si
In the case of zero package, the number of terminals can be reduced by wiring on the package due to the characteristics of the package.
Acquisition), in order to change the number of terminals,
It is necessary to change the position of the terminal on the integrated circuit due to restrictions at the time of bonding.

As a technique for changing the terminal position,
JP-A-61-45353 or JP-A-Heisei 05-2
There is a method of changing a circuit using a gate array described in Japanese Patent No. 59284, and a method of changing a circuit by externally applying energy after the diffusion step described in Japanese Patent Application Laid-Open No. 02-185796.

[0005]

However, in the above-described method using the conventional gate array, the layer to be repaired extends over the entire metal wiring layer, and the amount of repair becomes large especially in a process having multilayer wiring. There is.

Further, the conventional method of changing a circuit by applying energy from the outside after the completion of the diffusion step has a problem that the number of steps per integrated circuit is large.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a semiconductor integrated circuit in which the number of terminals of an LSI chip is different from that of an LSI chip, in particular, a semiconductor integrated circuit in which the terminal connection of the LSI chip to a QFP can be easily changed. And

[0008]

In order to achieve the above object, a first semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit having three or more wiring layers and connected to external terminals. An external terminal introduction wiring, and an internal circuit that is formed of the same wiring layer as the external terminal introduction wiring and that is connected to the external terminal introduction wiring to couple a signal between the external terminal and the internal circuit. Each group is formed by two wiring layers sandwiching the introductory wiring and the external terminal introductory wiring, and the external terminal introductory wiring continuously arranged is only one of the two wiring layers. Alternately intersecting, and the internal circuit introduction wiring is a plurality of introduction wiring connection wiring line segment sets each of which is arranged in parallel such that the two wiring layers intersect with each other, and the two wiring layers To connect the introductory wiring connection And a contact which is disposed a line segment set on, in accordance with the arrangement of the contact, the connection relationship between the external terminals for introducing wire and the introduction wires for the internal circuit is characterized in that it is changed.

[0009] In the first semiconductor integrated circuit, it is preferable that the wiring line segment for connecting the lead-in wiring is arranged so as to go around the internal circuit a plurality of times at a position inside the external terminal.

According to the first semiconductor integrated circuit, the number of external terminals of the integrated circuit can be reduced only by changing the contact layer for connecting the metal wiring. Further, since it can be realized with the minimum necessary number of wiring lines, the wiring capacity can be reduced as compared with the case where the circling wiring without using two layers is used. Further, since the same circuit wiring can be used for connection to a plurality of external terminals, it is possible to realize a function with a smaller number of circuits than the number of external terminals.

In the first semiconductor integrated circuit, when the ratio of the number of the external terminal introduction wirings actually used to the total number m of the external terminal introduction wirings is P, the introduction wiring connection wiring line The number of laps per minute is m × (1
-P) / 2. According to this configuration, when the number of external terminals to be used is small, it is possible to reduce the number of external terminals with the minimum number of peripheral wiring lines, and to reduce the chip area occupied by wiring. Will be possible.

In order to achieve the above object, a second semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit having three or more wiring layers, wherein an external terminal introduction wiring connected to an external terminal is provided. An internal circuit introduction wiring formed of the same wiring layer as the external terminal introduction wiring and connected to the external terminal introduction wiring to couple a signal between the external terminal and the internal circuit; Each set is formed by two wiring layers sandwiching the terminal introduction wiring, and only one of the two wiring layers alternately intersects with the external terminal introduction wiring arranged side by side, and And the internal circuit introduction wiring, and a plurality of introduction wiring connection wiring line segment sets each of which is arranged in parallel such that the two wiring layers intersect together,
A wiring line segment orthogonal to the introduction wiring connection wiring line set, formed of the same wiring layer as the external terminal introduction wiring, and connecting the introduction wiring connection wiring line segments of an adjacent set; A contact disposed on the lead-in connection wiring line segment set for connecting a wiring layer, and connecting the external terminal lead-in and the internal circuit lead-in according to the arrangement of the contact. The relationship is changed.

According to the second semiconductor integrated circuit, the number of peripheral circuits required can be reduced by changing the peripheral circuits and making connection, thereby reducing the chip area occupied by wiring. It becomes possible to plan.

In order to achieve the above object, a third semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit having three or more wiring layers, wherein an external terminal introduction wiring connected to an external terminal is provided. A normal external terminal introduction wiring, which is formed in the same wiring layer as the external terminal introduction wiring and is connected to the external terminal introduction wiring during normal operation, and is formed in the same wiring layer as the external terminal introduction wiring. A test external terminal lead-in line connected to the external terminal lead-in line during a test operation, and the normal external terminal lead-in line or the test external terminal lead-in line and the external terminal lead-in line And a selection circuit that switches between the external terminal and the internal circuit by being formed in the same wiring layer as the normal external terminal introduction wiring and being connected to the normal external terminal introduction wiring. Normal internal circuit introduction wiring, and the test external terminal introduction wiring is formed in the same wiring layer, and is connected to the test external terminal introduction wiring by the test external connection between the external terminal and the internal circuit. Each set is formed by two wiring layers sandwiching the test-time internal circuit introduction wiring that couples the signal and the normal-time external terminal introduction wiring, and the normal-time external terminal introduction wiring continuously arranged side by side. Only one of the two wiring layers intersects alternately, and the normal internal circuit introduction wiring is such that the two wiring layers intersect with each other at normal times when a plurality of sets are arranged in parallel. Each set is formed by two wiring layers sandwiching the lead wire for external terminal connection during test and the lead wire for external terminal for test which is continuously juxtaposed. Only one of the layers alternates Crossed, and,
The test-internal-circuit-introduction-wiring connects the test-introduction-wiring-connection wiring line segment set in which a plurality of sets are arranged in parallel such that the two wiring layers intersect with each other, and connects the two wiring layers. And a contact disposed on the normal-time lead-in connection wiring line sub-assembly and the test-in lead-in connection wiring line sub-assembly, and according to the arrangement of the contacts, the normal-time external terminal lead-in wiring. And the connection relationship between the normal internal circuit introduction wiring and the test external terminal introduction wiring and the test internal circuit introduction wiring are changed.

According to the third semiconductor integrated circuit, when reducing the number of external terminals, it is not necessary to make the combination of the normal operation and the test operation the same as when all the external terminals are used. The signal from the internal circuit coupled to the terminal can be selected independently of the signal during the test operation.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) First, a first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a plan view partially showing a configuration example of a terminal connection circuit in a semiconductor integrated circuit according to a first embodiment of the present invention.

In FIG. 1, reference numeral 101 denotes an external terminal of the integrated circuit, and reference numeral 102 denotes an external terminal introduction wiring connected to the external terminal 101. Reference numeral 103 denotes an internal circuit introduction wiring for connecting the external terminal introduction wiring 102 to output a signal from the internal circuit to the external terminal or to input a signal from the external terminal to the internal circuit. Also, 104
And 105 are wiring lines for connecting the wirings for connecting between the wirings 102 for external terminals and the wiring 103 for the internal circuit. Constitutes one set of wiring lines for connecting introductory wiring. Introductory wiring connection wiring line segments 104 and 105
Are composed of two layers of a metal wiring layer, such as a third layer and a first layer, which are further separated from each other. A wiring layer between the wiring layers on which the wiring lines 104 and 105 for connecting the wirings are formed, for example, a second-layer metal wiring is assigned to both the external terminal introducing wiring 102 and the internal circuit introducing wiring 103. .

Introductory wiring connection wiring line segments 104 and 10
5 is such that the upper-layer line segment 104 and the lower-layer line segment 105 alternately intersect with the external terminal introduction wiring 102, and both the line segments 104 and 105 intersect with the internal circuit introduction wiring 103. Be placed. In addition to the two introduction wirings, a contact line for arranging a contact connecting the two-layer introduction wiring connection wiring line segments 104 and 105 at a position other than the two introduction wirings is an intermediate line. The two introductory wiring connecting wiring lines are arranged between the wiring layers in which they are formed. In addition, the contact line is connected to one of the upper-layer or lower-layer lead-in wiring lines 104 and 105 by a contact so that the contact line does not become a floating line.

Introductory wiring connection wiring line segments 104 and 105
As shown in FIG. 4, a plurality of sets are arranged between the external terminal 101 and the internal circuit (core block) so as to go around the integrated circuit by the above-described arrangement method. By providing the wiring line segments 104 and 105 for connecting the introductory wiring on the nearer half of the inner circuit introducing wire 103 and the external terminal introducing wire 102, the maximum wiring length becomes the length of two sides,
As a result, the number of wirings to be circulated is half of the maximum number of external terminals.

Furthermore, by maintaining the original order of the signal assignment after the number of external terminals 101 is reduced, the number of circuit wirings can be further reduced. For example, the original integrated circuit has a total of m external terminal introductory lines on one side, and when the number of external terminal introductory lines is reduced to the ratio P to the number of external terminal introductory lines, a certain external terminal introductory line The number of wiring lines for the introductory wiring connecting across the introductory wiring for the internal circuit to be connected is
(M−m × P). This is because the number of internal circuit introduction wirings included from a certain external terminal as a base point to m from there is m, and the number of external terminal introduction wirings actually used is m × P, so that they are not connected. The number of signal lines is mx (1-P). Therefore, the maximum value of the number of orbiting wirings can be m × (1−P). For example, when the reduction ratio of the number of external terminals is at least １ ／, considering the external terminal introduction wiring included in a half circumference, m is の of the number of original external terminal introduction wirings. , The number of circuit wirings may be set to ４.

Further, the power supply wiring is arranged inside or outside of the lead wiring connecting line segments 104 and 105 so as to go around the integrated circuit. In FIG. 4, the external terminal introduction wiring 102 and the internal circuit introduction wiring 103 are
Removed for clarity.

Next, a wiring connection method will be described with reference to FIGS. 2, 3, 5, and 6. FIG.

FIG. 2 is a plan view partially showing an example of the wiring connection method in the present embodiment. In FIGS. 2 and 3, a first contact type (contact type 1) indicates a contact for connecting an upper layer and an intermediate layer, and a second contact type (contact type 2).
Represents a contact for connecting the lower layer and the intermediate layer.

First, the case where all the external terminals are used will be described with reference to FIGS.

In FIG. 2, reference numerals 201 to 206 denote external terminals, and 211 to 216 denote external terminals 20 respectively.
External terminal lead-in wires connected to 1 to 206;
221 to 226 are external terminals 201 to 20 respectively.
6 is used, the external terminal introduction wiring 211 is used.
To 216 are internal circuit introduction wirings. Reference numeral 242 denotes an upper layer line of the introductory wiring connection wiring,
Reference numerals 241 and 243 denote lower-layer line segments of the introductory wiring connection wiring. In this case, wirings adjacent to the external terminal introduction wirings 211 to 216 and the internal circuit introduction wirings 221 to 226 are connected. That is, the connection follows the original external terminal assignment. At this time, the external terminal introduction wiring 21
A contact for connecting the two introductory wirings is arranged on the introductory wiring connecting wiring line segment on the side intersecting 1 to 216. That is, the first type contacts 231 and 232 allow the internal circuit lead-in 221 and the external terminal lead-in 2
11 and the second type of contacts 233 and 234
Thus, the internal circuit introduction wiring 222 and the external terminal introduction wiring 212 are connected.

FIG. 5 is a schematic diagram showing an example of the wiring connection in this embodiment in a three-dimensional manner, as viewed from the external terminals 201 and 202 in FIG.

In FIG. 5, reference numerals 511 and 512 correspond to the external terminal introduction wirings 211 and 212 in FIG. 2, respectively. 521 and 522 correspond to the internal circuit introduction wirings 221 and 222 in FIG.
Reference numerals 543 denote wiring line segments 24 for connecting the lead-in wiring of FIG.
1, 242 and 243. The contacts 231, 232, 233, and 234 in FIG.
31, 532, 533, and 534 are arranged.

Next, a description will be given of a case where every other external terminal is used and a continuous wiring for introducing an internal circuit is sequentially connected to the corresponding external terminal with reference to FIGS. 3 and 6. FIG.

In FIG. 3, reference numerals 301 to 303 denote external terminals to be used. Reference numerals 311 to 313 denote external terminal introduction wirings connected to the external terminals 301 to 303, respectively, and reference numerals 321 to 323 denote internal circuit introduction wirings to be connected to the external terminal introduction wirings 311 to 313, respectively. Reference numerals 342, 344, 346, and 348 denote wiring lines for introducing wiring connection in the upper layer.
Reference numerals 3, 345, 347 denote lower-layer wiring lines for introducing wiring connection, 331, 332, 335, 336 are first type contacts, and 333, 334 are second type contacts.

If another external terminal introduction wiring or another internal circuit introduction wiring exists between the internal circuit introduction wiring and the external terminal introduction wiring to be connected thereto, the contact wiring line , A wiring line is formed by directly connecting the wiring lines for connecting the upper wiring and the lower wiring, and the wiring for the internal circuit and the wiring for the external terminal are connected by the wiring.

For example, as shown in FIG. 3, in order to couple a signal between the internal circuit connected to the internal circuit introduction wiring 322 and the external terminal 302 connected to the external terminal introduction wiring 312, When connecting the circuit introduction wiring 322 and the external terminal introduction wiring 312, the introduction wiring connection wiring line segments 347 and 348 are directly connected by the first type contact 334 and the second type contact 335, and the second type contact 333 is used. By connecting the internal circuit introduction wiring 322 and the introduction wiring connection wiring line segment 347, and connecting the external terminal introduction wiring 312 and the introduction wiring connection wiring line segment 348 by the first type contact 336, the thick line in FIG. 3 is obtained. Are connected between the internal circuit introduction wiring 322 and the external terminal introduction wiring 312.

FIG. 6 is a schematic diagram showing another example of the wiring connection in this embodiment in a three-dimensional manner, as viewed from the external terminals 301 and 302 in FIG.

In FIG. 6, the external terminal lead-in line 611 is shown.
And 612 respectively correspond to 311 and 312 in FIG. Also, the internal circuit introduction wirings 621 and 62
3 respectively correspond to 321 and 322 in FIG. 3, the wiring segments 641 to 648 for the lead-in connection correspond to 341 to 348 in FIG. 3, respectively, and the contacts 631 to 636 correspond to the contacts 331 to 331 in FIG. 336
Corresponding to

Of the lead-in wires for unused external terminals,
For an external terminal used as an input, it is connected to a power supply line via a contact to avoid a floating line.

In this embodiment, as long as the order of the two lead wires, ie, the external terminal lead wire, the internal circuit lead wire, and the lead wire connecting wire line, is satisfied.
The same effect can be obtained regardless of the used wiring layer.

For signals that are always required, such as a clock signal and a reset signal, the same effects can be obtained even if the signals are realized by a fixed circuit separately from the above circuit configuration.

Further, even if the wiring line for the lead-in connection is not used as a peripheral circuit but is applied to a specific side or a part, the same effect can be obtained for that part due to the characteristics of the integrated circuit. .

Further, in this embodiment, one external terminal lead-in wire is set for one external terminal. However, when a plurality of lead-in wires are required for each terminal for input / output terminals, etc. By regarding the introduction wiring as one of the above-described external terminal introduction wirings, an equivalent circuit can be configured and an equivalent effect can be obtained.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS.

FIG. 7 is a plan view partially showing a configuration example of a terminal connection circuit in a semiconductor integrated circuit according to a second embodiment of the present invention.

In FIG. 7, reference numeral 701 denotes an external terminal of the integrated circuit, and reference numeral 702 denotes an external terminal introduction wiring connected to the external terminal. Reference numeral 703 denotes an external terminal introduction wiring 7.
02 is an internal circuit introduction wiring for outputting a signal from the internal circuit to the external terminal 701 or inputting the signal from the external terminal 701 to the internal circuit. Also,
Reference numerals 704 and 705 denote wiring lines for connecting the wirings for connecting between the wiring 702 for the external terminal and the wiring 703 for the internal circuit, and the wiring lines 704 and 705 for the wiring connection. Together, these form a single lead wiring connection wiring line set. Reference numeral 706 denotes a wiring line for connecting adjacent wiring lines for introduction wiring connection.

FIG. 8 is a schematic diagram showing a three-dimensional example of the wiring connection in this embodiment, as viewed from the external terminal 701 side in FIG.

In FIG. 8, the external terminal introduction wiring 802 is used.
7 corresponds to 702 in FIG. 7, and the internal circuit introduction wiring 803 corresponds to 703 in FIG.
4 and 805 respectively correspond to 704 and 705 in FIG. Wiring line segments 706 for connecting adjacent wiring lines for introducing wiring in FIG. 7 are arranged as 806 in FIG. The wiring line segments 804 and 805 for connecting the introductory wiring are formed of two layers of a metal wiring layer, such as a third layer and a first layer, with a gap between them. The wiring layers for connecting the external terminal introduction wiring 802, the internal circuit introduction wiring 803, and the introduction wiring connection wiring line segments 804 and 805 are all wiring layers of the introduction wiring connection wiring line segments 804 and 805. A wiring layer between them, for example, a second layer is allocated.

The wiring line segment 806 for connecting the wiring line segments 804 and 805 for the introduction wiring connection is used to switch the connection to the adjacent wiring line line for the introduction wiring connection. It is possible to reduce it.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG.

FIG. 9 is a plan view partially showing a configuration example of the terminal connection circuit in the semiconductor integrated circuit according to the third embodiment of the present invention.

In FIG. 9, reference numeral 901 denotes an external terminal of the integrated circuit, and reference numeral 902 denotes an external terminal introduction wiring connected to the external terminal. Reference numeral 903 denotes a normal external terminal introduction wiring connected to a corresponding external terminal during a normal operation. Reference numeral 904 denotes a test external terminal introduction wiring connected to a corresponding external terminal during a test operation.

Reference numeral 912 denotes a normal external terminal lead-in line 90.
3 and a selection circuit (mux) for switching the signal path to the external terminal introduction wiring 904 at the time of test, and 911 is an operation selection signal wiring to which an operation selection signal for switching between normal operation and test operation is supplied. It is.

Reference numeral 905 denotes a normal internal circuit introduction wiring for outputting a signal from the internal circuit of the integrated circuit to the external terminal 901 or inputting the signal from the external terminal 901 to the internal circuit during a normal operation. Reference numeral 906 denotes a test internal circuit introduction wiring for outputting a signal from the internal circuit of the integrated circuit to the external terminal 901 or inputting a signal from the external terminal 901 to the internal circuit during a test operation.

Reference numerals 907 and 908 denote a normal external terminal introduction wiring 903 and a normal internal circuit introduction wiring 90.
5 is a wiring line for normal introduction wiring connection which constitutes a wiring for connection with the wiring 5. Reference numerals 909 and 910 are test-introduction-wiring connection wiring lines that constitute wiring for connecting between the external-terminal-introduction-in-test-in wiring 904 and the internal-circuit-introducing-in-test-in wiring 906. Note that the wiring lines 907 and 908 for connecting the normal wiring and the wiring lines 909 and 910 for connecting the wiring during the test are the two-layer wiring of the upper layer and the lower layer, respectively, as in the first embodiment. Composed of layers.

[0053]

As described above, according to the present invention,
The following effects are obtained.

(1) The number of external terminals of the integrated circuit can be reduced only by changing the contact layer for connecting the metal wiring. Further, since it can be realized with the minimum necessary number of wiring lines, the wiring capacity can be reduced as compared with the case where the circling wiring without using two layers is used. Further, since the same circuit wiring can be used for connection to a plurality of external terminals, it is possible to realize a function with a smaller number of circuits than the number of external terminals.

(2) When the number of external terminals to be used is small,
The number of external terminals can be reduced with the minimum number of circuit wiring lines, and the chip area occupied by wiring can be reduced.

(3) By connecting the peripheral circuits, the required number of peripheral circuits can be reduced, and the chip area occupied by the wiring can be reduced.

(4) When reducing the number of external terminals, the combination of normal operation and test operation does not need to be the same as when all external terminals are used. The signal can be selected independently of the signal in the test operation.

(5) According to the above (1) to (4), LS
Package with different number of terminals from I chip, especially Q
The terminal connection of the LSI chip to the FP can be easily changed.

[Brief description of the drawings]

FIG. 1 is a plan view partially showing a configuration example of a terminal connection circuit in a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 2 is a plan view partially showing an example of a wiring connection method in the semiconductor integrated circuit according to the first embodiment of the present invention;

FIG. 3 is a plan view partially showing another example of the wiring connection method in the semiconductor integrated circuit according to the first embodiment of the present invention;

FIG. 4 is a plan view schematically showing a state in which lead-in connection wiring is circulated between an external terminal and an internal circuit (core block) in the semiconductor integrated circuit according to the embodiment of the present invention;

FIG. 5 is a schematic diagram showing the example of the wiring connection method in the semiconductor integrated circuit according to the first embodiment of the present invention in a three-dimensional manner, viewed from the external terminals 201 and 202 in FIG. 2;

FIG. 6 is a schematic view showing another example of the wiring connection method in the semiconductor integrated circuit according to the first embodiment of the present invention, viewed from the external terminals 301 and 302 side in FIG.

FIG. 7 is a plan view partially showing a configuration example of a terminal connection circuit in a semiconductor integrated circuit according to a second embodiment of the present invention;

FIG. 8 is a schematic view showing the example of the wiring connection method in the semiconductor integrated circuit according to the second embodiment of the present invention, viewed from the external terminal 701 side in FIG.

FIG. 9 is a plan view partially showing a configuration example of a terminal connection circuit in a semiconductor integrated circuit according to a third embodiment of the present invention;

[Explanation of symbols]

101, 201-206, 301-303, 701, 9
01 External terminal 102, 211-216, 311-313, 511, 5
12, 611, 612, 702, 802, 902 Introducing wiring for external terminals 103, 221-226, 321-323, 521, 5
22, 621, 622, 703, 803 Internal circuit introduction wiring 104, 105, 241-243, 341-348, 5
41-543, 641-648, 704, 705, 80
4,805 Introductory wiring connection wiring line segment 231,232,331,332,335,336,5
31, 532, 631, 632, 635, 636 First
Type contacts 233,234,333,334,533,533,534,6
33, 634 Second type contact 706, 806 Wiring line for connecting adjacent pairs of wiring for connecting wiring for wiring 903 Normal wiring for external terminal 904 Normal wiring for external terminal at test 905 Normal internal circuit for wiring Introductory wiring 906 Introductory wiring for internal circuit during test 907, 908 Introductory wiring connecting wiring for normal operation 909, 910 Introductory wiring connecting wiring for test 911 Operation selection signal wiring 912 Selection circuit

Claims (5)

[Claims] 1. A semiconductor integrated circuit having three or more wiring layers, wherein the external terminal is formed of the same wiring layer as the external terminal introducing wiring connected to an external terminal. Each set is formed by two wiring layers sandwiching the internal terminal introduction wiring, and an internal circuit introduction wiring that couples a signal between the external terminal and the internal circuit by being connected to the introduction terminal wiring, In this case, only one of the two wiring layers alternately intersects with the external terminal introduction wiring, and the two wiring layers intersect with the internal circuit introduction wiring. As described above, each set includes a plurality of introductory wiring connecting wiring line sets arranged in parallel, and a contact disposed on the introductory wiring connecting wiring line set to connect the two wiring layers, Depending on the arrangement of the contacts, The semiconductor integrated circuit characterized in that connections of Kigaibu terminal introducing wire and said internal circuit introducing wiring is changed. 2. The semiconductor integrated circuit according to claim 1, wherein the wiring group for connecting the introduction wiring is arranged so as to go around the internal circuit a plurality of times at a position inside the external terminal. 3. The ratio of the number of the external terminal introduction wirings actually used to the total number m of the external terminal introduction wirings is P.
, The number of turns of the wiring line for the introduction wiring connection,
3. The semiconductor integrated circuit according to claim 2, wherein the value is set to mx (1-P) / 2. 4. A semiconductor integrated circuit having three or more wiring layers, wherein said external terminal is formed of an external terminal lead-in connected to an external terminal and the same wiring layer as said external terminal lead-in. Each set is formed by two wiring layers sandwiching the internal terminal introduction wiring, and an internal circuit introduction wiring that couples a signal between the external terminal and the internal circuit by being connected to the introduction terminal wiring, In this case, only one of the two wiring layers alternately intersects with the external terminal introduction wiring, and the two wiring layers intersect with the internal circuit introduction wiring. In this way, each of the sets is arranged in parallel with a plurality of lead-wiring connection wiring line sets, and the lead-wiring connection wiring line-segment groups are formed of the same wiring layer as the external terminal lead-wirings. Matching set of wiring lines for connecting the introduction wiring A wiring line segment to be connected, and a contact disposed on the wiring line segment for connecting the introduction wiring for connecting the two wiring layers, and the introduction wiring for the external terminal according to the arrangement of the contact. A connection relationship between the semiconductor integrated circuit and the internal circuit introduction wiring is changed. 5. A semiconductor integrated circuit having three or more wiring layers, comprising: an external terminal introducing wiring connected to an external terminal; and the same wiring layer as the external terminal introducing wiring, and formed during normal operation. A normal external terminal lead-in connected to the external terminal lead-in, and a test external terminal formed in the same wiring layer as the external terminal lead-in and connected to the external terminal lead-in during a test operation A selection circuit for switching the connection between the normal external terminal introduction wiring or the test external terminal introduction wiring and the external terminal introduction wiring; and the same wiring layer as the normal external terminal introduction wiring A normal internal circuit lead-in which is connected to the normal external terminal lead-in and couples a signal between the external terminal and the internal circuit by being connected to the normal external terminal lead-in. A test internal circuit introduction wiring which is formed of the same wiring layer as the wiring and is connected to the test external terminal introduction wiring to couple a signal between the external terminal and the internal circuit; Each set is formed by two wiring layers sandwiching the terminal introduction wiring, and only one of the two wiring layers alternately intersects with the normal external terminal introduction wiring continuously juxtaposed, and The normal internal circuit introduction wiring is a normal introduction wiring connection wiring line segment set in which a plurality of sets are arranged in parallel such that the two wiring layers intersect with each other, and the test external terminal introduction wiring. Each pair is formed by two wiring layers sandwiching the same, and only one of the two wiring layers alternately intersects with the external terminal introduction wiring for test which is continuously juxtaposed, and Introductory wiring for circuits A test-introduction wiring connection wiring line segment set in which a plurality of sets are arranged in parallel such that the wiring layers intersect with each other; and the normal-time introduction wiring connection wiring line segment set in order to connect the two wiring layers. And a contact disposed on the wiring line set for connection of the test-introduction wiring, and connection between the normal-time external terminal introduction wiring and the normal-time internal circuit introduction wiring in accordance with the arrangement of the contacts. A semiconductor integrated circuit, wherein a relationship and a connection relationship between the test-time external terminal lead-in and the test-time internal circuit lead-in are changed.